1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/imx_uart.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <platform_config.h> 42 #include <stdint.h> 43 #include <sm/optee_smc.h> 44 #include <tee/entry_fast.h> 45 #include <tee/entry_std.h> 46 47 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 48 defined(PLATFORM_FLAVOR_mx6qsabresd) 49 #include <kernel/tz_ssvce_pl310.h> 50 #endif 51 52 static void main_fiq(void); 53 static struct gic_data gic_data; 54 55 static const struct thread_handlers handlers = { 56 .std_smc = tee_entry_std, 57 .fast_smc = tee_entry_fast, 58 .nintr = main_fiq, 59 .cpu_on = pm_panic, 60 .cpu_off = pm_panic, 61 .cpu_suspend = pm_panic, 62 .cpu_resume = pm_panic, 63 .system_off = pm_panic, 64 .system_reset = pm_panic, 65 }; 66 67 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 68 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 69 70 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 71 defined(PLATFORM_FLAVOR_mx6qsabresd) 72 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 73 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE); 74 #endif 75 76 const struct thread_handlers *generic_boot_get_handlers(void) 77 { 78 return &handlers; 79 } 80 81 static void main_fiq(void) 82 { 83 panic(); 84 } 85 86 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 87 defined(PLATFORM_FLAVOR_mx6qsabresd) 88 void plat_cpu_reset_late(void) 89 { 90 uintptr_t addr; 91 92 if (!get_core_pos()) { 93 /* primary core */ 94 #if defined(CFG_BOOT_SYNC_CPU) 95 /* set secondary entry address and release core */ 96 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 8); 97 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 16); 98 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 24); 99 100 write32(SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR); 101 #endif 102 103 /* SCU config */ 104 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 105 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 106 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 107 108 /* SCU enable */ 109 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 110 SCU_BASE + SCU_CTRL); 111 112 /* configure imx6 CSU */ 113 114 /* first grant all peripherals */ 115 for (addr = CSU_BASE + CSU_CSL_START; 116 addr != CSU_BASE + CSU_CSL_END; 117 addr += 4) 118 write32(CSU_ACCESS_ALL, addr); 119 120 /* lock the settings */ 121 for (addr = CSU_BASE + CSU_CSL_START; 122 addr != CSU_BASE + CSU_CSL_END; 123 addr += 4) 124 write32(read32(addr) | CSU_SETTING_LOCK, addr); 125 } 126 } 127 #endif 128 129 static vaddr_t console_base(void) 130 { 131 static void *va; 132 133 if (cpu_mmu_enabled()) { 134 if (!va) 135 va = phys_to_virt(CONSOLE_UART_BASE, 136 MEM_AREA_IO_NSEC); 137 return (vaddr_t)va; 138 } 139 return CONSOLE_UART_BASE; 140 } 141 142 void console_init(void) 143 { 144 vaddr_t base = console_base(); 145 146 imx_uart_init(base); 147 } 148 149 void console_putc(int ch) 150 { 151 vaddr_t base = console_base(); 152 153 /* If \n, also do \r */ 154 if (ch == '\n') 155 imx_uart_putc('\r', base); 156 imx_uart_putc(ch, base); 157 } 158 159 void console_flush(void) 160 { 161 vaddr_t base = console_base(); 162 163 imx_uart_flush_tx_fifo(base); 164 } 165 166 void main_init_gic(void) 167 { 168 vaddr_t gicc_base; 169 vaddr_t gicd_base; 170 171 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 172 MEM_AREA_IO_SEC); 173 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 174 MEM_AREA_IO_SEC); 175 176 if (!gicc_base || !gicd_base) 177 panic(); 178 179 /* Initialize GIC */ 180 gic_init(&gic_data, gicc_base, gicd_base); 181 itr_init(&gic_data.chip); 182 } 183 184 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 185 defined(PLATFORM_FLAVOR_mx6qsabresd) 186 vaddr_t pl310_base(void) 187 { 188 static void *va __early_bss; 189 190 if (cpu_mmu_enabled()) { 191 if (!va) 192 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 193 return (vaddr_t)va; 194 } 195 return PL310_BASE; 196 } 197 198 void main_secondary_init_gic(void) 199 { 200 gic_cpu_init(&gic_data); 201 } 202 #endif 203