1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <console.h> 31 #include <drivers/imx_uart.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/panic.h> 35 #include <kernel/pm_stubs.h> 36 #include <mm/core_mmu.h> 37 #include <mm/core_memprot.h> 38 #include <platform_config.h> 39 #include <stdint.h> 40 #include <sm/optee_smc.h> 41 #include <tee/entry_std.h> 42 #include <tee/entry_fast.h> 43 44 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 45 defined(PLATFORM_FLAVOR_mx6qsabresd) 46 #include <drivers/gic.h> 47 #include <kernel/tz_ssvce_pl310.h> 48 #endif 49 50 static void main_fiq(void); 51 static void platform_tee_entry_fast(struct thread_smc_args *args); 52 53 static const struct thread_handlers handlers = { 54 .std_smc = tee_entry_std, 55 .fast_smc = platform_tee_entry_fast, 56 .fiq = main_fiq, 57 .cpu_on = pm_panic, 58 .cpu_off = pm_panic, 59 .cpu_suspend = pm_panic, 60 .cpu_resume = pm_panic, 61 .system_off = pm_panic, 62 .system_reset = pm_panic, 63 }; 64 65 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 66 defined(PLATFORM_FLAVOR_mx6qsabresd) 67 static struct gic_data gic_data; 68 69 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 70 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 71 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 72 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE); 73 #endif 74 75 const struct thread_handlers *generic_boot_get_handlers(void) 76 { 77 return &handlers; 78 } 79 80 static void main_fiq(void) 81 { 82 panic(); 83 } 84 85 static vaddr_t console_base(void) 86 { 87 static void *va; 88 89 if (cpu_mmu_enabled()) { 90 if (!va) 91 va = phys_to_virt(CONSOLE_UART_PA_BASE, 92 MEM_AREA_IO_NSEC); 93 return (vaddr_t)va; 94 } 95 return CONSOLE_UART_BASE; 96 } 97 98 void console_init(void) 99 { 100 vaddr_t base = console_base(); 101 102 imx_uart_init(base); 103 } 104 105 void console_putc(int ch) 106 { 107 vaddr_t base = console_base(); 108 109 /* If \n, also do \r */ 110 if (ch == '\n') 111 imx_uart_putc('\r', base); 112 imx_uart_putc(ch, base); 113 } 114 115 void console_flush(void) 116 { 117 vaddr_t base = console_base(); 118 119 imx_uart_flush_tx_fifo(base); 120 } 121 122 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 123 defined(PLATFORM_FLAVOR_mx6qsabresd) 124 #ifdef CFG_BOOT_SECONDARY_REQUEST 125 static vaddr_t src_base(void) 126 { 127 static void *va __data; /* in case it's used before .bss is cleared */ 128 129 if (cpu_mmu_enabled()) { 130 if (!va) 131 va = phys_to_virt(SRC_BASE, MEM_AREA_IO_SEC); 132 return (vaddr_t)va; 133 } 134 return SRC_BASE; 135 } 136 137 static int platform_smp_boot(size_t core_idx, uint32_t entry) 138 { 139 uint32_t val; 140 vaddr_t va = src_base(); 141 142 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) 143 return OPTEE_SMC_RETURN_EBADCMD; 144 145 /* set secondary cores' NS entry addresses */ 146 147 ns_entry_addrs[core_idx] = entry; 148 cache_maintenance_l1(DCACHE_AREA_CLEAN, 149 &ns_entry_addrs[core_idx], 150 sizeof(uint32_t)); 151 cache_maintenance_l2(L2CACHE_AREA_CLEAN, 152 (paddr_t)&ns_entry_addrs[core_idx], 153 sizeof(uint32_t)); 154 155 /* boot secondary cores from OP-TEE load address */ 156 157 write32((uint32_t)CFG_TEE_LOAD_ADDR, va + SRC_GPR1 + core_idx * 8); 158 159 /* release secondary core */ 160 161 val = read32(va + SRC_SCR); 162 val |= BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + (core_idx - 1)); 163 val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + (core_idx - 1)); 164 write32(val, va + SRC_SCR); 165 return OPTEE_SMC_RETURN_OK; 166 } 167 #endif /* CFG_BOOT_SECONDARY_REQUEST */ 168 169 vaddr_t pl310_base(void) 170 { 171 static void *va __data; /* in case it's used before .bss is cleared */ 172 173 if (cpu_mmu_enabled()) { 174 if (!va) 175 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 176 return (vaddr_t)va; 177 } 178 return PL310_BASE; 179 } 180 181 void main_init_gic(void) 182 { 183 vaddr_t gicc_base; 184 vaddr_t gicd_base; 185 186 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 187 MEM_AREA_IO_SEC); 188 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 189 MEM_AREA_IO_SEC); 190 191 if (!gicc_base || !gicd_base) 192 panic(); 193 194 /* Initialize GIC */ 195 gic_init(&gic_data, gicc_base, gicd_base); 196 197 itr_init(&gic_data.chip); 198 } 199 #endif 200 201 static void platform_tee_entry_fast(struct thread_smc_args *args) 202 { 203 #ifdef CFG_BOOT_SECONDARY_REQUEST 204 if (args->a0 == OPTEE_SMC_BOOT_SECONDARY) { 205 args->a0 = platform_smp_boot(args->a1, (uint32_t)(args->a3)); 206 return; 207 } 208 #endif /* CFG_BOOT_SECONDARY_REQUEST */ 209 tee_entry_fast(args); 210 } 211