1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019, 2023 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <imx.h> 36 #include <io.h> 37 #include <kernel/boot.h> 38 #include <mm/core_memprot.h> 39 #include <mm/core_mmu.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 43 static struct imx_uart_data console_data __nex_bss; 44 45 #ifdef CONSOLE_UART_BASE 46 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 47 CORE_MMU_PGDIR_SIZE); 48 #endif 49 #ifdef GIC_BASE 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 51 #endif 52 #ifdef ANATOP_BASE 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 54 #endif 55 #ifdef GICD_BASE 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 57 #endif 58 #ifdef AIPS0_BASE 59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE, 60 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE)); 61 #endif 62 #ifdef AIPS1_BASE 63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 64 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 65 #endif 66 #ifdef AIPS2_BASE 67 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 68 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 69 #endif 70 #ifdef AIPS3_BASE 71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 72 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 73 #endif 74 #ifdef IRAM_BASE 75 register_phys_mem(MEM_AREA_TEE_COHERENT, 76 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 77 CORE_MMU_PGDIR_SIZE); 78 #endif 79 #ifdef M4_AIPS_BASE 80 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE); 81 #endif 82 #ifdef IRAM_S_BASE 83 register_phys_mem(MEM_AREA_TEE_COHERENT, 84 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 85 CORE_MMU_PGDIR_SIZE); 86 #endif 87 88 #if defined(CFG_PL310) 89 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 90 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 91 CORE_MMU_PGDIR_SIZE); 92 #endif 93 94 #ifdef CFG_DRAM_BASE 95 register_ddr(CFG_DRAM_BASE, CFG_DDR_SIZE); 96 #endif 97 #ifdef CFG_NSEC_DDR_1_BASE 98 register_ddr(CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE); 99 #endif 100 101 void console_init(void) 102 { 103 #ifdef CONSOLE_UART_BASE 104 imx_uart_init(&console_data, CONSOLE_UART_BASE); 105 register_serial_console(&console_data.chip); 106 #endif 107 } 108 109 void boot_primary_init_intc(void) 110 { 111 #ifdef GICD_BASE 112 gic_init(0, GICD_BASE); 113 #else 114 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 115 #endif 116 } 117 118 #if CFG_TEE_CORE_NB_CORE > 1 119 void boot_secondary_init_intc(void) 120 { 121 gic_cpu_init(); 122 } 123 #endif 124