1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #include <arm32.h> 9 #include <io.h> 10 #include <kernel/generic_boot.h> 11 #include <kernel/tz_ssvce_def.h> 12 #include <kernel/tz_ssvce_pl310.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <platform_config.h> 16 #include <stdint.h> 17 18 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 19 20 void arm_cl2_config(vaddr_t pl310_base) 21 { 22 /* Disable PL310 */ 23 write32(0, pl310_base + PL310_CTRL); 24 25 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 26 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 27 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 28 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 29 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 30 31 /* invalidate all cache ways */ 32 arm_cl2_invbyway(pl310_base); 33 } 34 35 void arm_cl2_enable(vaddr_t pl310_base) 36 { 37 uint32_t val; 38 39 /* Enable PL310 ctrl -> only set lsb bit */ 40 write32(1, pl310_base + PL310_CTRL); 41 42 /* if L2 FLZW enable, enable in L1 */ 43 val = read32(pl310_base + PL310_AUX_CTRL); 44 if (val & 1) 45 write_actlr(read_actlr() | (1 << 3)); 46 } 47 48 vaddr_t pl310_base(void) 49 { 50 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC); 51 } 52 53