1 /* 2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #include <arm32.h> 30 #include <io.h> 31 #include <kernel/generic_boot.h> 32 #include <kernel/tz_ssvce_def.h> 33 #include <kernel/tz_ssvce_pl310.h> 34 #include <mm/core_memprot.h> 35 #include <mm/core_mmu.h> 36 #include <platform_config.h> 37 #include <stdint.h> 38 39 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 40 41 void arm_cl2_config(vaddr_t pl310_base) 42 { 43 /* Disable PL310 */ 44 write32(0, pl310_base + PL310_CTRL); 45 46 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 47 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 48 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 49 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 50 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 51 52 /* invalidate all cache ways */ 53 arm_cl2_invbyway(pl310_base); 54 } 55 56 void arm_cl2_enable(vaddr_t pl310_base) 57 { 58 uint32_t val; 59 60 /* Enable PL310 ctrl -> only set lsb bit */ 61 write32(1, pl310_base + PL310_CTRL); 62 63 /* if L2 FLZW enable, enable in L1 */ 64 val = read32(pl310_base + PL310_AUX_CTRL); 65 if (val & 1) 66 write_actlr(read_actlr() | (1 << 3)); 67 } 68 69 vaddr_t pl310_base(void) 70 { 71 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC); 72 } 73 74