1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #include <arm32.h> 9 #include <io.h> 10 #include <kernel/generic_boot.h> 11 #include <kernel/tz_ssvce_def.h> 12 #include <kernel/tz_ssvce_pl310.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <sm/optee_smc.h> 16 #include <platform_config.h> 17 #include <stdint.h> 18 #include "imx_pl310.h" 19 20 #define PL310_AUX_CTRL_FLZW BIT(0) 21 #define PL310_DEBUG_CTRL_DISABLE_WRITEBACK BIT(1) 22 #define PL310_DEBUG_CTRL_DISABLE_LINEFILL BIT(0) 23 24 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 25 26 void arm_cl2_config(vaddr_t pl310_base) 27 { 28 /* Disable PL310 */ 29 write32(0, pl310_base + PL310_CTRL); 30 31 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 32 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 33 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 34 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 35 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 36 37 /* invalidate all cache ways */ 38 arm_cl2_invbyway(pl310_base); 39 } 40 41 void arm_cl2_enable(vaddr_t pl310_base) 42 { 43 uint32_t val __maybe_unused; 44 45 /* Enable PL310 ctrl -> only set lsb bit */ 46 write32(1, pl310_base + PL310_CTRL); 47 48 #ifndef CFG_PL310_SIP_PROTOCOL 49 /* if L2 FLZW enable, enable in L1 */ 50 val = read32(pl310_base + PL310_AUX_CTRL); 51 if (val & PL310_AUX_CTRL_FLZW) 52 write_actlr(read_actlr() | ACTLR_CA9_WFLZ); 53 #endif 54 } 55 56 vaddr_t pl310_base(void) 57 { 58 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC); 59 } 60 61 #ifdef CFG_PL310_SIP_PROTOCOL 62 uint32_t pl310_enable(void) 63 { 64 vaddr_t base = pl310_base(); 65 66 arm_cl2_config(base); 67 arm_cl2_enable(base); 68 return OPTEE_SMC_RETURN_OK; 69 } 70 71 uint32_t pl310_disable(void) 72 { 73 EMSG("not implemented"); 74 return OPTEE_SMC_RETURN_ENOTAVAIL; 75 } 76 77 uint32_t pl310_enable_writeback(void) 78 { 79 vaddr_t base = pl310_base(); 80 81 write32(0, base + PL310_DEBUG_CTRL); 82 return OPTEE_SMC_RETURN_OK; 83 } 84 85 uint32_t pl310_disable_writeback(void) 86 { 87 vaddr_t base = pl310_base(); 88 uint32_t val = PL310_DEBUG_CTRL_DISABLE_WRITEBACK | 89 PL310_DEBUG_CTRL_DISABLE_LINEFILL; 90 91 write32(val, base + PL310_DEBUG_CTRL); 92 return OPTEE_SMC_RETURN_OK; 93 } 94 95 uint32_t pl310_enable_wflz(void) 96 { 97 write_actlr(read_actlr() | ACTLR_CA9_WFLZ); 98 return OPTEE_SMC_RETURN_OK; 99 } 100 #endif 101