1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #ifndef PLAT_IMX_IMX_REGS_H 30 #define PLAT_IMX_IMX_REGS_H 31 32 #ifdef CFG_MX6 33 #define UART1_BASE 0x2020000 34 #define IOMUXC_BASE 0x020E0000 35 #define IOMUXC_SIZE 0x4000 36 #define IOMUXC_GPR_BASE 0x020E4000 37 #define SRC_BASE 0x020D8000 38 #define SRC_SIZE 0x4000 39 #define CCM_BASE 0x020C4000 40 #define CCM_SIZE 0x4000 41 #define ANATOP_BASE 0x020C8000 42 #define ANATOP_SIZE 0x1000 43 #define SNVS_BASE 0x020CC000 44 #define GPC_BASE 0x020DC000 45 #define GPC_SIZE 0x4000 46 #define WDOG_BASE 0x020BC000 47 #define SEMA4_BASE 0x02290000 48 #define SEMA4_SIZE 0x4000 49 #define MMDC_P0_BASE 0x021B0000 50 #define MMDC_P0_SIZE 0x4000 51 #define MMDC_P1_BASE 0x021B4000 52 #define MMDC_P1_SIZE 0x4000 53 #define TZASC_BASE 0x21D0000 54 #define TZASC2_BASE 0x21D4000 55 #define UART2_BASE 0x021E8000 56 #define UART3_BASE 0x021EC000 57 #define UART4_BASE 0x021F0000 58 #define UART5_BASE 0x021F4000 59 #define AIPS1_BASE 0x02000000 60 #define AIPS1_SIZE 0x100000 61 #define AIPS2_BASE 0x02100000 62 #define AIPS2_SIZE 0x100000 63 #define AIPS3_BASE 0x02200000 64 #define AIPS3_SIZE 0x100000 65 66 #define SCU_BASE 0x00A00000 67 #define PL310_BASE 0x00A02000 68 #define SRC_BASE 0x020D8000 69 #define IRAM_BASE 0x00900000 70 71 #define OCOTP_BASE 0x021BC000 72 73 #define GIC_BASE 0x00A00000 74 #define GICD_OFFSET 0x1000 75 76 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) 77 #define GICC_OFFSET 0x2000 78 /* No CAAM on i.MX6ULL */ 79 #define CAAM_BASE 0x02140000 80 #else 81 #define GICC_OFFSET 0x100 82 #define CAAM_BASE 0x02100000 83 #endif 84 85 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) 86 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) 87 88 /* Central Security Unit register values */ 89 #define CSU_BASE 0x021C0000 90 #define CSU_CSL_START 0x0 91 #define CSU_CSL_END 0xA0 92 #define CSU_CSL5 0x14 93 #define CSU_CSL15 0x3C 94 #define CSU_CSL16 0x40 95 #define CSU_ACCESS_ALL 0x00FF00FF 96 #define CSU_SETTING_LOCK 0x01000100 97 98 /* Used in suspend/resume and low power idle */ 99 #define MX6Q_SRC_GPR1 0x20 100 #define MX6Q_SRC_GPR2 0x24 101 #define MX6Q_MMDC_MISC 0x18 102 #define MX6Q_MMDC_MAPSR 0x404 103 #define MX6Q_MMDC_MPDGCTRL0 0x83c 104 #define MX6Q_GPC_IMR1 0x08 105 #define MX6Q_GPC_IMR2 0x0c 106 #define MX6Q_GPC_IMR3 0x10 107 #define MX6Q_GPC_IMR4 0x14 108 #define MX6Q_CCM_CCR 0x0 109 #define MX6Q_ANATOP_CORE 0x140 110 111 #define IOMUXC_GPR9_OFFSET 0x24 112 #define IOMUXC_GPR10_OFFSET 0x28 113 114 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET 5 115 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5) 116 117 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET 4 118 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4) 119 120 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET 20 121 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20) 122 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET 21 123 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21) 124 125 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET_6UL 11 126 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11) 127 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET_6UL 10 128 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10) 129 130 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET_6UL 26 131 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26) 132 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL (27) 133 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27) 134 135 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) || defined(CFG_MX6SX) 136 #define DRAM0_BASE 0x80000000 137 #else 138 #define DRAM0_BASE 0x10000000 139 #endif 140 141 #elif defined(CFG_MX7) 142 #define GIC_BASE 0x31000000 143 #define GIC_SIZE 0x8000 144 #define GICC_OFFSET 0x2000 145 #define GICD_OFFSET 0x1000 146 147 #define CAAM_BASE 0x30900000 148 #define UART1_BASE 0x30860000 149 #define UART2_BASE 0x30890000 150 #define UART3_BASE 0x30880000 151 152 #define AIPS1_BASE 0x30000000 153 #define AIPS1_SIZE 0x400000 154 #define AIPS2_BASE 0x30400000 155 #define AIPS2_SIZE 0x400000 156 #define AIPS3_BASE 0x30800000 157 #define AIPS3_SIZE 0x400000 158 159 #define WDOG_BASE 0x30280000 160 #define LPSR_BASE 0x30270000 161 #define IOMUXC_BASE 0x30330000 162 #define IOMUXC_GPR_BASE 0x30340000 163 #define OCOTP_BASE 0x30350000 164 #define ANATOP_BASE 0x30360000 165 #define SNVS_BASE 0x30370000 166 #define CCM_BASE 0x30380000 167 #define SRC_BASE 0x30390000 168 #define GPC_BASE 0x303A0000 169 #define TZASC_BASE 0x30780000 170 #define DDRC_PHY_BASE 0x30790000 171 #define MMDC_P0_BASE 0x307A0000 172 #define DDRC_BASE 0x307A0000 173 #define IRAM_BASE 0x00900000 174 #define IRAM_S_BASE 0x00180000 175 176 #define CSU_CSL_START 0x303E0000 177 #define CSU_CSL_END 0x303E0100 178 #define CSU_CSL_59 (0x303E0000 + 59 * 4) 179 #define CSU_CSL_28 (0x303E0000 + 28 * 4) 180 #define CSU_CSL_15 (0x303E0000 + 15 * 4) 181 #define CSU_CSL_12 (0x303E0000 + 12 * 4) 182 #define CSU_ACCESS_ALL 0x00FF00FF 183 #define CSU_SETTING_LOCK 0x01000100 184 185 #define TRUSTZONE_OCRAM_START 0x180000 186 187 #define IOMUXC_GPR9_OFFSET 0x24 188 #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 189 190 #define IOMUXC_GPR11_OFFSET 0x2C 191 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 192 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 193 194 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 195 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 196 197 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 198 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 199 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 200 #else 201 #error "CFG_MX6/7 not defined" 202 #endif 203 204 #define IOMUXC_GPR4_OFFSET 0x10 205 #define IOMUXC_GPR5_OFFSET 0x14 206 #define ARM_WFI_STAT_MASK(n) BIT(n) 207 208 #define ARM_WFI_STAT_MASK_7D(n) BIT(25 + ((n) & 1)) 209 210 #define SRC_SCR 0x000 211 #define SRC_GPR1 0x020 212 #define SRC_GPR2 0x024 213 #define SRC_SCR_CORE1_RST_OFFSET 14 214 #define SRC_SCR_CORE1_ENABLE_OFFSET 22 215 #define SRC_SCR_CPU_ENABLE_ALL SHIFT_U32(0x7, 22) 216 217 #define SRC_GPR1_MX7 0x074 218 #define SRC_A7RCR0 0x004 219 #define SRC_A7RCR1 0x008 220 #define SRC_A7RCR0_A7_CORE_RESET0_OFFSET 0 221 #define SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET 1 222 223 #define SNVS_LPCR_OFF 0x38 224 #define SNVS_LPCR_TOP_MASK BIT(6) 225 #define SNVS_LPCR_DP_EN_MASK BIT(5) 226 #define SNVS_LPCR_SRTC_ENV_MASK 1 227 228 #define WCR_OFF 0 229 230 #define OFFSET_DIGPROG 0x260 231 #define OFFSET_DIGPROG_IMX6SL 0x280 232 #define OFFSET_DIGPROG_IMX7D 0x800 233 234 /* GPC V2 */ 235 #define GPC_PGC_C1 0x840 236 #define GPC_PGC_C1_PUPSCR 0x844 237 238 #define GPC_PGC_PCG_MASK BIT(0) 239 240 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 241 #define GPC_PU_PGC_SW_PUP_REQ 0xf8 242 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 243 #define GPC_PU_PGC_SW_PDN_REQ 0x104 244 #define GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK BIT(1) 245 #endif 246