1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef PLAT_IMX_IMX_REGS_H 31 #define PLAT_IMX_IMX_REGS_H 32 33 #ifdef CFG_MX6 34 #include <registers/imx6.h> 35 #elif defined(CFG_MX7) 36 #include <registers/imx7.h> 37 #elif defined(CFG_MX7ULP) 38 #include <registers/imx7ulp.h> 39 #elif defined(CFG_MX8MQ) || defined(CFG_MX8MM) || defined(CFG_MX8MN) 40 #include <registers/imx8m.h> 41 #elif defined(CFG_MX8QX) || defined(CFG_MX8QM) 42 #include <registers/imx8q.h> 43 #else 44 #error "CFG_MX6/7/7ULP or CFG_MX8MQ/8MM/8QX/8QM is not defined" 45 #endif 46 47 #define IOMUXC_GPR4_OFFSET 0x10 48 #define IOMUXC_GPR5_OFFSET 0x14 49 #define ARM_WFI_STAT_MASK(n) BIT(n) 50 51 #define ARM_WFI_STAT_MASK_7D(n) BIT(25 + ((n) & 1)) 52 53 #define SRC_SCR 0x000 54 #define SRC_GPR1 0x020 55 #define SRC_GPR2 0x024 56 #define SRC_SCR_CORE1_RST_OFFSET 14 57 #define SRC_SCR_CORE1_ENABLE_OFFSET 22 58 #define SRC_SCR_CPU_ENABLE_ALL SHIFT_U32(0x7, 22) 59 60 #define SRC_GPR1_MX7 0x074 61 #define SRC_A7RCR0 0x004 62 #define SRC_A7RCR1 0x008 63 #define SRC_A7RCR0_A7_CORE_RESET0_OFFSET 0 64 #define SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET 1 65 66 #define SNVS_LPCR_OFF 0x38 67 #define SNVS_LPCR_TOP_MASK BIT(6) 68 #define SNVS_LPCR_DP_EN_MASK BIT(5) 69 #define SNVS_LPCR_SRTC_ENV_MASK 1 70 71 #define WCR_OFF 0 72 73 /* GPC V2 */ 74 #define GPC_PGC_C1 0x840 75 #define GPC_PGC_C1_PUPSCR 0x844 76 77 #define GPC_PGC_PCG_MASK BIT(0) 78 79 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 80 #define GPC_PU_PGC_SW_PUP_REQ 0xf8 81 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 82 #define GPC_PU_PGC_SW_PDN_REQ 0x104 83 #define GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK BIT(1) 84 #endif 85