1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef PLAT_IMX_IMX_REGS_H 31 #define PLAT_IMX_IMX_REGS_H 32 33 #ifdef CFG_MX6 34 #define UART1_BASE 0x2020000 35 #define IOMUXC_BASE 0x020E0000 36 #define IOMUXC_SIZE 0x4000 37 #define IOMUXC_GPR_BASE 0x020E4000 38 #define SRC_BASE 0x020D8000 39 #define SRC_SIZE 0x4000 40 #define CCM_BASE 0x020C4000 41 #define CCM_SIZE 0x4000 42 #define ANATOP_BASE 0x020C8000 43 #define ANATOP_SIZE 0x1000 44 #define SNVS_BASE 0x020CC000 45 #define GPC_BASE 0x020DC000 46 #define GPC_SIZE 0x4000 47 #define WDOG_BASE 0x020BC000 48 #define CSU_BASE 0x021C0000 49 #define SEMA4_BASE 0x02290000 50 #define SEMA4_SIZE 0x4000 51 #define MMDC_P0_BASE 0x021B0000 52 #define MMDC_P0_SIZE 0x4000 53 #define MMDC_P1_BASE 0x021B4000 54 #define MMDC_P1_SIZE 0x4000 55 #define TZASC_BASE 0x21D0000 56 #define TZASC2_BASE 0x21D4000 57 #define UART2_BASE 0x021E8000 58 #define UART3_BASE 0x021EC000 59 #define UART4_BASE 0x021F0000 60 #define UART5_BASE 0x021F4000 61 #define AIPS1_BASE 0x02000000 62 #define AIPS1_SIZE 0x100000 63 #define AIPS2_BASE 0x02100000 64 #define AIPS2_SIZE 0x100000 65 #define AIPS3_BASE 0x02200000 66 #define AIPS3_SIZE 0x100000 67 68 #define SCU_BASE 0x00A00000 69 #define PL310_BASE 0x00A02000 70 #define SRC_BASE 0x020D8000 71 #define IRAM_BASE 0x00900000 72 73 #define OCOTP_BASE 0x021BC000 74 75 #define GIC_BASE 0x00A00000 76 #define GICD_OFFSET 0x1000 77 78 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) 79 #define GICC_OFFSET 0x2000 80 /* No CAAM on i.MX6ULL */ 81 #define CAAM_BASE 0x02140000 82 #else 83 #define GICC_OFFSET 0x100 84 #define CAAM_BASE 0x02100000 85 #endif 86 87 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) 88 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) 89 90 /* Central Security Unit register values */ 91 #define CSU_CSL_START 0x0 92 #define CSU_CSL_END 0xA0 93 #define CSU_ACCESS_ALL 0x00FF00FF 94 #define CSU_SETTING_LOCK 0x01000100 95 96 /* Used in suspend/resume and low power idle */ 97 #define MX6Q_SRC_GPR1 0x20 98 #define MX6Q_SRC_GPR2 0x24 99 #define MX6Q_MMDC_MISC 0x18 100 #define MX6Q_MMDC_MAPSR 0x404 101 #define MX6Q_MMDC_MPDGCTRL0 0x83c 102 #define MX6Q_GPC_IMR1 0x08 103 #define MX6Q_GPC_IMR2 0x0c 104 #define MX6Q_GPC_IMR3 0x10 105 #define MX6Q_GPC_IMR4 0x14 106 #define MX6Q_CCM_CCR 0x0 107 #define MX6Q_ANATOP_CORE 0x140 108 109 #define IOMUXC_GPR9_OFFSET 0x24 110 #define IOMUXC_GPR10_OFFSET 0x28 111 112 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET 5 113 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5) 114 115 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET 4 116 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4) 117 118 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET 20 119 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20) 120 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET 21 121 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21) 122 123 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET_6UL 11 124 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11) 125 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET_6UL 10 126 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10) 127 128 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET_6UL 26 129 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26) 130 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL (27) 131 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27) 132 133 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) || defined(CFG_MX6SX) 134 #define DRAM0_BASE 0x80000000 135 #else 136 #define DRAM0_BASE 0x10000000 137 #endif 138 139 #elif defined(CFG_MX7) 140 #define GIC_BASE 0x31000000 141 #define GIC_SIZE 0x8000 142 #define GICC_OFFSET 0x2000 143 #define GICD_OFFSET 0x1000 144 145 #define CAAM_BASE 0x30900000 146 #define UART1_BASE 0x30860000 147 #define UART2_BASE 0x30890000 148 #define UART3_BASE 0x30880000 149 #define UART4_BASE 0x30A60000 150 #define UART5_BASE 0x30A70000 151 152 #define AIPS1_BASE 0x30000000 153 #define AIPS1_SIZE 0x400000 154 #define AIPS2_BASE 0x30400000 155 #define AIPS2_SIZE 0x400000 156 #define AIPS3_BASE 0x30800000 157 #define AIPS3_SIZE 0x400000 158 159 #define WDOG_BASE 0x30280000 160 #define LPSR_BASE 0x30270000 161 #define IOMUXC_BASE 0x30330000 162 #define IOMUXC_GPR_BASE 0x30340000 163 #define OCOTP_BASE 0x30350000 164 #define ANATOP_BASE 0x30360000 165 #define SNVS_BASE 0x30370000 166 #define CCM_BASE 0x30380000 167 #define SRC_BASE 0x30390000 168 #define GPC_BASE 0x303A0000 169 #define CSU_BASE 0x303E0000 170 #define TZASC_BASE 0x30780000 171 #define DDRC_PHY_BASE 0x30790000 172 #define MMDC_P0_BASE 0x307A0000 173 #define DDRC_BASE 0x307A0000 174 #define IRAM_BASE 0x00900000 175 #define IRAM_S_BASE 0x00180000 176 177 #define CSU_CSL_START 0x0 178 #define CSU_CSL_END 0x100 179 #define CSU_ACCESS_ALL 0x00FF00FF 180 #define CSU_SETTING_LOCK 0x01000100 181 182 #define TRUSTZONE_OCRAM_START 0x180000 183 184 #define IOMUXC_GPR9_OFFSET 0x24 185 #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 186 187 #define IOMUXC_GPR11_OFFSET 0x2C 188 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 189 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 190 191 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 192 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 193 194 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 195 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 196 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 197 #elif defined(CFG_IMX8MQ) || defined(CFG_IMX8MM) 198 #define GICD_BASE 0x38800000 199 #define GICR_BASE 0x38880000 200 #define UART1_BASE 0x30860000 201 #define UART2_BASE 0x30890000 202 #define UART3_BASE 0x30880000 203 #define UART4_BASE 0x30A60000 204 #define TZASC_BASE 0x32F80000 205 #define CAAM_BASE 0x30900000 206 #define ANATOP_BASE 0x30360000 207 #else 208 #error "CFG_MX6/7 not defined" 209 #endif 210 211 #define IOMUXC_GPR4_OFFSET 0x10 212 #define IOMUXC_GPR5_OFFSET 0x14 213 #define ARM_WFI_STAT_MASK(n) BIT(n) 214 215 #define ARM_WFI_STAT_MASK_7D(n) BIT(25 + ((n) & 1)) 216 217 #define SRC_SCR 0x000 218 #define SRC_GPR1 0x020 219 #define SRC_GPR2 0x024 220 #define SRC_SCR_CORE1_RST_OFFSET 14 221 #define SRC_SCR_CORE1_ENABLE_OFFSET 22 222 #define SRC_SCR_CPU_ENABLE_ALL SHIFT_U32(0x7, 22) 223 224 #define SRC_GPR1_MX7 0x074 225 #define SRC_A7RCR0 0x004 226 #define SRC_A7RCR1 0x008 227 #define SRC_A7RCR0_A7_CORE_RESET0_OFFSET 0 228 #define SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET 1 229 230 #define SNVS_LPCR_OFF 0x38 231 #define SNVS_LPCR_TOP_MASK BIT(6) 232 #define SNVS_LPCR_DP_EN_MASK BIT(5) 233 #define SNVS_LPCR_SRTC_ENV_MASK 1 234 235 #define WCR_OFF 0 236 237 #define OFFSET_DIGPROG 0x260 238 #define OFFSET_DIGPROG_IMX6SL 0x280 239 #define OFFSET_DIGPROG_IMX7D 0x800 240 241 /* GPC V2 */ 242 #define GPC_PGC_C1 0x840 243 #define GPC_PGC_C1_PUPSCR 0x844 244 245 #define GPC_PGC_PCG_MASK BIT(0) 246 247 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 248 #define GPC_PU_PGC_SW_PUP_REQ 0xf8 249 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 250 #define GPC_PU_PGC_SW_PDN_REQ 0x104 251 #define GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK BIT(1) 252 #endif 253