1 /* 2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * All rights reserved. 5 * 6 * Peng Fan <peng.fan@nxp.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <console.h> 32 #include <io.h> 33 #include <imx.h> 34 #include <mm/core_mmu.h> 35 #include <mm/core_memprot.h> 36 #include <platform_config.h> 37 38 static uint32_t imx_digproc(void) 39 { 40 static uint32_t reg; 41 vaddr_t anatop_addr; 42 43 if (!reg) { 44 anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); 45 46 /* TODO: Handle SL here */ 47 #ifdef CFG_MX7 48 reg = read32(anatop_addr + OFFSET_DIGPROG_IMX7D); 49 #else 50 reg = read32(anatop_addr + OFFSET_DIGPROG); 51 #endif 52 } 53 54 return reg; 55 } 56 57 static uint32_t imx_soc_rev_major(void) 58 { 59 return ((imx_digproc() & 0xff00) >> 8) + 1; 60 } 61 62 uint32_t imx_soc_type(void) 63 { 64 return (imx_digproc() >> 16) & 0xff; 65 } 66 67 bool soc_is_imx6ul(void) 68 { 69 return imx_soc_type() == SOC_MX6UL; 70 } 71 72 bool soc_is_imx6ull(void) 73 { 74 return imx_soc_type() == SOC_MX6ULL; 75 } 76 77 bool soc_is_imx6sdl(void) 78 { 79 return imx_soc_type() == SOC_MX6DL; 80 } 81 82 bool soc_is_imx6dq(void) 83 { 84 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 1); 85 } 86 87 bool soc_is_imx6dqp(void) 88 { 89 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2); 90 } 91 92 bool soc_is_imx7s(void) 93 { 94 vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC); 95 uint32_t val = read32(addr); 96 97 if (soc_is_imx7ds()) { 98 if (val & 1) 99 return true; 100 else 101 return false; 102 } 103 104 return false; 105 } 106 107 bool soc_is_imx7d(void) 108 { 109 vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC); 110 uint32_t val = read32(addr); 111 112 if (soc_is_imx7ds()) { 113 if (val & 1) 114 return false; 115 else 116 return true; 117 } 118 119 return false; 120 } 121 122 bool soc_is_imx7ds(void) 123 { 124 return imx_soc_type() == SOC_MX7D; 125 } 126 127 uint32_t imx_get_src_gpr(int cpu) 128 { 129 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 130 131 if (soc_is_imx7d()) 132 return read32(va + SRC_GPR1_MX7 + cpu * 8 + 4); 133 else 134 return read32(va + SRC_GPR1 + cpu * 8 + 4); 135 } 136 137 void imx_set_src_gpr(int cpu, uint32_t val) 138 { 139 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 140 141 if (soc_is_imx7d()) 142 write32(val, va + SRC_GPR1_MX7 + cpu * 8 + 4); 143 else 144 write32(val, va + SRC_GPR1 + cpu * 8 + 4); 145 } 146