1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017 NXP 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #ifndef __CONFIG_IMX6SX_H 9 #define __CONFIG_IMX6SX_H 10 11 /* 12 * PL310 TAG RAM Control Register 13 * 14 * bit[10:8]:1 - 2 cycle of write accesses latency 15 * bit[6:4]:3 - 4 cycle of read accesses latency 16 * bit[2:0]:2 - 3 cycle of setup latency 17 */ 18 #ifndef PL310_TAG_RAM_CTRL_INIT 19 #define PL310_TAG_RAM_CTRL_INIT 0x00000132 20 #endif 21 22 /* 23 * PL310 DATA RAM Control Register 24 * 25 * bit[10:8]:1 - 2 cycle of write accesses latency 26 * bit[6:4]:3 - 4 cycle of read accesses latency 27 * bit[2:0]:2 - 3 cycle of setup latency 28 */ 29 #ifndef PL310_DATA_RAM_CTRL_INIT 30 #define PL310_DATA_RAM_CTRL_INIT 0x00000232 31 #endif 32 33 /* 34 * PL310 Auxiliary Control Register 35 * 36 * I/Dcache prefetch enabled (bit29:28=2b11) 37 * NS can access interrupts (bit27=1) 38 * NS can lockown cache lines (bit26=1) 39 * Pseudo-random replacement policy (bit25=0) 40 * Force write allocated (default) 41 * Shared attribute internally ignored (bit22=1, bit13=0) 42 * Parity disabled (bit21=0) 43 * Event monitor disabled (bit20=0) 44 * Platform fmavor specific way config (dual / quad): 45 * - 16kb way size (bit19:17=3b001) 46 * - 16-way associciativity (bit16=1) 47 * Store buffer device limitation enabled (bit11=1) 48 * Cacheable accesses have high prio (bit10=0) 49 * Full Line Zero (FLZ) disabled (bit0=0) 50 */ 51 #define PL310_AUX_CTRL_INIT 0x3C430800 52 53 /* 54 * PL310 Prefetch Control Register 55 * 56 * Double linefill disabled (bit30=0) 57 * I/D prefetch enabled (bit29:28=2b11) 58 * Prefetch drop enabled (bit24=1) 59 * Incr double linefill disable (bit23=0) 60 * Prefetch offset = 7 (bit4:0) 61 */ 62 #define PL310_PREFETCH_CTRL_INIT 0x31000007 63 64 /* 65 * PL310 Power Register 66 * 67 * Dynamic clock gating enabled 68 * Standby mode enabled 69 */ 70 #define PL310_POWER_CTRL_INIT 0x00000003 71 72 /* 73 * SCU Invalidate Register 74 * 75 * Invalidate all registers 76 */ 77 #define SCU_INV_CTRL_INIT 0xFFFFFFFF 78 79 /* 80 * SCU Access Register 81 * - both secure CPU access SCU 82 */ 83 #define SCU_SAC_CTRL_INIT 0x0000000F 84 85 /* 86 * SCU NonSecure Access Register 87 * - both nonsec cpu access SCU, private and global timer 88 */ 89 #define SCU_NSAC_CTRL_INIT 0x00000FFF 90 91 #endif 92