1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #ifndef __CONFIG_IMX6SX_H 9 #define __CONFIG_IMX6SX_H 10 11 /* 12 * PL310 TAG RAM Control Register 13 * 14 * bit[10:8]:1 - 2 cycle of write accesses latency 15 * bit[6:4]:3 - 4 cycle of read accesses latency 16 * bit[2:0]:2 - 3 cycle of setup latency 17 */ 18 #ifndef PL310_TAG_RAM_CTRL_INIT 19 #define PL310_TAG_RAM_CTRL_INIT 0x00000132 20 #endif 21 22 /* 23 * PL310 DATA RAM Control Register 24 * 25 * bit[10:8]:1 - 2 cycle of write accesses latency 26 * bit[6:4]:3 - 4 cycle of read accesses latency 27 * bit[2:0]:2 - 3 cycle of setup latency 28 */ 29 #ifndef PL310_DATA_RAM_CTRL_INIT 30 #define PL310_DATA_RAM_CTRL_INIT 0x00000132 31 #endif 32 33 /* 34 * PL310 Auxiliary Control Register 35 * 36 * Early BRESP enabled (bit30=1) 37 * I/Dcache prefetch enabled (bit29:28=2b11) 38 * NS can access interrupts (bit27=1) 39 * NS can lockown cache lines (bit26=1) 40 * Pseudo-random replacement policy (bit25=1) 41 * Force write allocated (default) (bit24:23=00) 42 * Shared attribute internally ignored (bit22=1, bit13=0) 43 * Parity disabled (bit21=0) 44 * Event monitor disabled (bit20=0) 45 * 16kb way size (bit19:17=3b001) 46 * 16-way associativity (bit16=1) 47 * Store buffer device limitation enabled (bit11=0) 48 * Cacheable accesses have high prio (bit10=0) 49 * Full Line Zero (FLZ) enabled (bit0=1) 50 */ 51 #ifndef PL310_AUX_CTRL_INIT 52 #define PL310_AUX_CTRL_INIT 0x7E430001 53 #endif 54 55 /* 56 * PL310 Prefetch Control Register 57 * 58 * Double linefill enabled (bit30=1) 59 * I/D prefetch enabled (bit29:28=2b11) 60 * Prefetch drop disabled (bit24=0) 61 * Incr double linefill disable (bit23=0) 62 * Prefetch offset = 0xF (bit4:0) 63 */ 64 #define PL310_PREFETCH_CTRL_INIT 0x7000000F 65 66 /* 67 * PL310 Power Register 68 * 69 * Dynamic clock gating enabled 70 * Standby mode enabled 71 */ 72 #define PL310_POWER_CTRL_INIT 0x00000003 73 #endif 74