1*64de482eSBai Ping /* SPDX-License-Identifier: BSD-2-Clause */ 2*64de482eSBai Ping /* 3*64de482eSBai Ping * Copyright 2017-2019 NXP 4*64de482eSBai Ping */ 5*64de482eSBai Ping 6*64de482eSBai Ping #ifndef _CONFIG_IMX6SL_H 7*64de482eSBai Ping #define _CONFIG_IMX6SL_H 8*64de482eSBai Ping 9*64de482eSBai Ping /* 10*64de482eSBai Ping * PL310 TAG RAM Control Register 11*64de482eSBai Ping * 12*64de482eSBai Ping * bit[10:8]:1 - 2 cycle of write accesses latency 13*64de482eSBai Ping * bit[6:4]:3 - 4 cycle of read accesses latency 14*64de482eSBai Ping * bit[2:0]:2 - 3 cycle of setup latency 15*64de482eSBai Ping */ 16*64de482eSBai Ping #ifndef PL310_TAG_RAM_CTRL_INIT 17*64de482eSBai Ping #define PL310_TAG_RAM_CTRL_INIT 0x00000132 18*64de482eSBai Ping #endif 19*64de482eSBai Ping 20*64de482eSBai Ping /* 21*64de482eSBai Ping * PL310 DATA RAM Control Register 22*64de482eSBai Ping * 23*64de482eSBai Ping * bit[10:8]:1 - 2 cycle of write accesses latency 24*64de482eSBai Ping * bit[6:4]:3 - 4 cycle of read accesses latency 25*64de482eSBai Ping * bit[2:0]:2 - 3 cycle of setup latency 26*64de482eSBai Ping */ 27*64de482eSBai Ping #ifndef PL310_DATA_RAM_CTRL_INIT 28*64de482eSBai Ping #define PL310_DATA_RAM_CTRL_INIT 0x00000132 29*64de482eSBai Ping #endif 30*64de482eSBai Ping 31*64de482eSBai Ping /* 32*64de482eSBai Ping * PL310 Auxiliary Control Register 33*64de482eSBai Ping * 34*64de482eSBai Ping * Early BRESP enabled (bit30=1) 35*64de482eSBai Ping * I/Dcache prefetch enabled (bit29:28=2b11) 36*64de482eSBai Ping * NS can access interrupts (bit27=1) 37*64de482eSBai Ping * NS can lockown cache lines (bit26=1) 38*64de482eSBai Ping * Pseudo-random replacement policy (bit25=1) 39*64de482eSBai Ping * Force write allocated (default) (bit24:23=00) 40*64de482eSBai Ping * Shared attribute internally ignored (bit22=1, bit13=0) 41*64de482eSBai Ping * Parity disabled (bit21=0) 42*64de482eSBai Ping * Event monitor disabled (bit20=0) 43*64de482eSBai Ping * 16kb way size (bit19:17=3b001) 44*64de482eSBai Ping * 16-way associativity (bit16=1) 45*64de482eSBai Ping * Store buffer device limitation enabled (bit11=0) 46*64de482eSBai Ping * Cacheable accesses have high prio (bit10=0) 47*64de482eSBai Ping * Full Line Zero (FLZ) enabled (bit0=1) 48*64de482eSBai Ping */ 49*64de482eSBai Ping #ifndef PL310_AUX_CTRL_INIT 50*64de482eSBai Ping #define PL310_AUX_CTRL_INIT 0x7E430001 51*64de482eSBai Ping #endif 52*64de482eSBai Ping 53*64de482eSBai Ping /* 54*64de482eSBai Ping * PL310 Prefetch Control Register 55*64de482eSBai Ping * 56*64de482eSBai Ping * Double linefill enabled (bit30=1) 57*64de482eSBai Ping * I/D prefetch enabled (bit29:28=2b11) 58*64de482eSBai Ping * Prefetch drop disabled (bit24=0) 59*64de482eSBai Ping * Incr double linefill disable (bit23=0) 60*64de482eSBai Ping * Prefetch offset = 0xF (bit4:0) 61*64de482eSBai Ping */ 62*64de482eSBai Ping #define PL310_PREFETCH_CTRL_INIT 0x7000000F 63*64de482eSBai Ping 64*64de482eSBai Ping /* 65*64de482eSBai Ping * PL310 Power Register 66*64de482eSBai Ping * 67*64de482eSBai Ping * Dynamic clock gating enabled 68*64de482eSBai Ping * Standby mode enabled 69*64de482eSBai Ping */ 70*64de482eSBai Ping #define PL310_POWER_CTRL_INIT 0x00000003 71*64de482eSBai Ping #endif 72