xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision c04a96a45ffe0e665a4d86e542ec921fae932aa8) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk
67
68mx8mn-flavorlist = \
69	mx8mnevk
70
71mx8mp-flavorlist = \
72	mx8mpevk
73
74mx8qm-flavorlist = \
75	mx8qmmek \
76
77mx8qx-flavorlist = \
78	mx8qxpmek \
79
80ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
81$(call force,CFG_MX6,y)
82$(call force,CFG_MX6UL,y)
83$(call force,CFG_TEE_CORE_NB_CORE,1)
84$(call force,CFG_TZC380,y)
85include core/arch/arm/cpu/cortex-a7.mk
86else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
87$(call force,CFG_MX6,y)
88$(call force,CFG_MX6ULL,y)
89$(call force,CFG_TEE_CORE_NB_CORE,1)
90$(call force,CFG_IMX_CAAM,n)
91$(call force,CFG_NXP_CAAM,n)
92$(call force,CFG_IMX_DCP,y)
93include core/arch/arm/cpu/cortex-a7.mk
94else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
95$(call force,CFG_MX6,y)
96$(call force,CFG_MX6Q,y)
97$(call force,CFG_TEE_CORE_NB_CORE,4)
98$(call force,CFG_TZC380,y)
99else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
100$(call force,CFG_MX6,y)
101$(call force,CFG_MX6QP,y)
102$(call force,CFG_TEE_CORE_NB_CORE,4)
103else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
104$(call force,CFG_MX6,y)
105$(call force,CFG_MX6D,y)
106$(call force,CFG_TEE_CORE_NB_CORE,2)
107$(call force,CFG_TZC380,y)
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6DL,y)
111$(call force,CFG_TEE_CORE_NB_CORE,2)
112$(call force,CFG_TZC380,y)
113else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
114$(call force,CFG_MX6,y)
115$(call force,CFG_MX6S,y)
116$(call force,CFG_TEE_CORE_NB_CORE,1)
117else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
118$(call force,CFG_MX6,y)
119$(call force,CFG_MX6SL,y)
120$(call force,CFG_TEE_CORE_NB_CORE,1)
121$(call force,CFG_IMX_CAAM,n)
122$(call force,CFG_NXP_CAAM,n)
123$(call force,CFG_IMX_DCP,y)
124else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
125$(call force,CFG_MX6,y)
126$(call force,CFG_MX6SLL,y)
127$(call force,CFG_TEE_CORE_NB_CORE,1)
128$(call force,CFG_IMX_CAAM,n)
129$(call force,CFG_NXP_CAAM,n)
130$(call force,CFG_IMX_DCP,y)
131else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
132$(call force,CFG_MX6,y)
133$(call force,CFG_MX6SX,y)
134$(call force,CFG_TEE_CORE_NB_CORE,1)
135else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
136$(call force,CFG_MX7,y)
137$(call force,CFG_TEE_CORE_NB_CORE,1)
138include core/arch/arm/cpu/cortex-a7.mk
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
140$(call force,CFG_MX7,y)
141$(call force,CFG_TEE_CORE_NB_CORE,2)
142include core/arch/arm/cpu/cortex-a7.mk
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
144$(call force,CFG_MX7ULP,y)
145$(call force,CFG_TEE_CORE_NB_CORE,1)
146$(call force,CFG_TZC380,n)
147$(call force,CFG_CSU,n)
148$(call force,CFG_NXP_CAAM,n)
149include core/arch/arm/cpu/cortex-a7.mk
150else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
151$(call force,CFG_MX8MQ,y)
152$(call force,CFG_ARM64_core,y)
153CFG_IMX_UART ?= y
154CFG_DRAM_BASE ?= 0x40000000
155CFG_TEE_CORE_NB_CORE ?= 4
156else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
157$(call force,CFG_MX8MM,y)
158$(call force,CFG_ARM64_core,y)
159CFG_IMX_UART ?= y
160CFG_DRAM_BASE ?= 0x40000000
161CFG_TEE_CORE_NB_CORE ?= 4
162else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
163$(call force,CFG_MX8MN,y)
164$(call force,CFG_ARM64_core,y)
165CFG_IMX_UART ?= y
166CFG_DRAM_BASE ?= 0x40000000
167CFG_TEE_CORE_NB_CORE ?= 4
168else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
169$(call force,CFG_MX8MP,y)
170$(call force,CFG_ARM64_core,y)
171CFG_IMX_UART ?= y
172CFG_DRAM_BASE ?= 0x40000000
173CFG_TEE_CORE_NB_CORE ?= 4
174else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
175$(call force,CFG_MX8QM,y)
176$(call force,CFG_ARM64_core,y)
177$(call force,CFG_IMX_SNVS,n)
178CFG_IMX_LPUART ?= y
179CFG_DRAM_BASE ?= 0x80000000
180CFG_TEE_CORE_NB_CORE ?= 6
181$(call force,CFG_NXP_CAAM,n)
182else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
183$(call force,CFG_MX8QX,y)
184$(call force,CFG_ARM64_core,y)
185CFG_IMX_LPUART ?= y
186CFG_DRAM_BASE ?= 0x80000000
187CFG_TEE_CORE_NB_CORE ?= 4
188$(call force,CFG_NXP_CAAM,n)
189else
190$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
191endif
192
193ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
194CFG_DDR_SIZE ?= 0x40000000
195CFG_NS_ENTRY_ADDR ?= 0x80800000
196endif
197
198ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
199CFG_DDR_SIZE ?= 0x40000000
200CFG_UART_BASE ?= UART1_BASE
201endif
202
203ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
204CFG_DDR_SIZE ?= 0x20000000
205CFG_NS_ENTRY_ADDR ?= 0x87800000
206CFG_DT_ADDR ?= 0x83100000
207CFG_UART_BASE ?= UART5_BASE
208CFG_BOOT_SECONDARY_REQUEST ?= n
209CFG_EXTERNAL_DTB_OVERLAY ?= y
210CFG_IMX_WDOG_EXT_RESET ?= y
211endif
212
213ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
214CFG_DDR_SIZE ?= 0x20000000
215CFG_NS_ENTRY_ADDR ?= 0x80800000
216CFG_BOOT_SECONDARY_REQUEST ?= n
217endif
218
219ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
220CFG_DDR_SIZE ?= 0x20000000
221CFG_NS_ENTRY_ADDR ?= 0x87800000
222CFG_DT_ADDR ?= 0x83100000
223CFG_BOOT_SECONDARY_REQUEST ?= n
224CFG_EXTERNAL_DTB_OVERLAY = y
225CFG_IMX_WDOG_EXT_RESET = y
226endif
227
228ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
229CFG_DDR_SIZE ?= 0x40000000
230CFG_NS_ENTRY_ADDR ?= 0x60800000
231CFG_UART_BASE ?= UART4_BASE
232endif
233
234ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
235	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
236	mx6dapalis mx6qapalis))
237CFG_DDR_SIZE ?= 0x40000000
238CFG_NS_ENTRY_ADDR ?= 0x12000000
239endif
240
241ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
242	mx6dlsabreauto mx6solosabreauto))
243CFG_DDR_SIZE ?= 0x80000000
244CFG_NS_ENTRY_ADDR ?= 0x12000000
245CFG_UART_BASE ?= UART4_BASE
246endif
247
248ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
249CFG_DDR_SIZE ?= 0x80000000
250CFG_UART_BASE ?= UART1_BASE
251endif
252
253ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
254CFG_DDR_SIZE ?= 0x40000000
255CFG_NS_ENTRY_ADDR ?= 0x12000000
256endif
257
258ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
259CFG_DDR_SIZE ?= 0x40000000
260CFG_NS_ENTRY_ADDR ?= 0x12000000
261CFG_UART_BASE ?= UART2_BASE
262endif
263
264ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
265CFG_NS_ENTRY_ADDR ?= 0x80800000
266CFG_DDR_SIZE ?= 0x40000000
267endif
268
269ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
270CFG_NS_ENTRY_ADDR ?= 0x80800000
271CFG_DDR_SIZE ?= 0x80000000
272endif
273
274ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
275CFG_DDR_SIZE ?= 0x80000000
276CFG_NS_ENTRY_ADDR ?= 0x80800000
277endif
278
279ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
280CFG_DDR_SIZE ?= 0x40000000
281CFG_NS_ENTRY_ADDR ?= 0x80800000
282endif
283
284ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
285CFG_DDR_SIZE ?= 0x40000000
286CFG_UART_BASE ?= UART1_BASE
287endif
288
289ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
290CFG_DDR_SIZE ?= 0x20000000
291CFG_NS_ENTRY_ADDR ?= 0x80800000
292endif
293
294ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
295CFG_DDR_SIZE ?= 0x10000000
296CFG_NS_ENTRY_ADDR ?= 0x80800000
297CFG_UART_BASE ?= UART5_BASE
298endif
299
300ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
301CFG_DDR_SIZE ?= 0x10000000
302CFG_NS_ENTRY_ADDR ?= 0x80800000
303endif
304
305ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
306CFG_DDR_SIZE ?= 0x10000000
307CFG_UART_BASE ?= UART7_BASE
308endif
309
310ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
311CFG_DDR_SIZE ?= 0xc0000000
312CFG_UART_BASE ?= UART1_BASE
313endif
314
315ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
316CFG_DDR_SIZE ?= 0x80000000
317CFG_UART_BASE ?= UART2_BASE
318endif
319
320ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
321CFG_DDR_SIZE ?= 0x80000000
322CFG_UART_BASE ?= UART2_BASE
323endif
324
325ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
326CFG_DDR_SIZE ?= UL(0x180000000)
327CFG_UART_BASE ?= UART2_BASE
328$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
329$(call force,CFG_CORE_ARM64_PA_BITS,36)
330endif
331
332ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
333CFG_DDR_SIZE ?= 0x80000000
334CFG_UART_BASE ?= UART0_BASE
335CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
336CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
337CFG_CORE_ARM64_PA_BITS ?= 40
338endif
339
340# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
341ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
342	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
343include core/arch/arm/cpu/cortex-a9.mk
344
345$(call force,CFG_PL310,y)
346
347CFG_PL310_LOCKED ?= y
348CFG_ENABLE_SCTLR_RR ?= y
349CFG_SCU ?= y
350endif
351
352ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
353CFG_DRAM_BASE ?= 0x10000000
354endif
355
356ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
357	$(CFG_MX6SX)))
358CFG_DRAM_BASE ?= 0x80000000
359endif
360
361ifeq ($(filter y, $(CFG_MX7)), y)
362CFG_INIT_CNTVOFF ?= y
363CFG_DRAM_BASE ?= 0x80000000
364endif
365
366ifeq ($(filter y, $(CFG_MX7ULP)), y)
367CFG_INIT_CNTVOFF ?= y
368CFG_DRAM_BASE ?= UL(0x60000000)
369$(call force,CFG_IMX_LPUART,y)
370$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
371endif
372
373ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
374$(call force,CFG_GIC,y)
375
376CFG_BOOT_SECONDARY_REQUEST ?= y
377CFG_DT ?= y
378CFG_PAGEABLE_ADDR ?= 0
379CFG_PSCI_ARM32 ?= y
380CFG_SECURE_TIME_SOURCE_REE ?= y
381CFG_UART_BASE ?= UART1_BASE
382endif
383
384ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8MM)))
385$(call force,CFG_IMX_UART,y)
386ifeq ($(CFG_RPMB_FS),y)
387CFG_IMX_SNVS ?= y
388endif
389endif
390
391ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
392CFG_CSU ?= y
393endif
394
395ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
396CFG_HWSUPP_MEM_PERM_WXN = n
397CFG_IMX_WDOG ?= y
398endif
399
400ifeq ($(CFG_ARM64_core),y)
401# arm-v8 platforms
402include core/arch/arm/cpu/cortex-armv8-0.mk
403$(call force,CFG_ARM_GICV3,y)
404$(call force,CFG_GIC,y)
405$(call force,CFG_WITH_LPAE,y)
406$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
407$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
408
409CFG_CRYPTO_WITH_CE ?= y
410
411supported-ta-targets = ta_arm64
412endif
413
414CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
415CFG_TZDRAM_SIZE ?= 0x01e00000
416CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
417CFG_SHMEM_SIZE ?= 0x00200000
418
419CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
420CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - 0x02000000)
421
422CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
423CFG_MMAP_REGIONS ?= 24
424
425# Almost all platforms include CAAM HW Modules, except the
426# ones forced to be disabled
427CFG_NXP_CAAM ?= n
428
429ifeq ($(CFG_NXP_CAAM),y)
430# As NXP CAAM Driver is enabled, disable the small local CAAM driver
431# used just to release Job Rings to Non-Secure world
432$(call force,CFG_IMX_CAAM,n)
433else
434
435ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
436CFG_IMX_CAAM ?= y
437endif
438endif
439
440# Cryptographic configuration
441include core/arch/arm/plat-imx/crypto_conf.mk
442