xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 5f7f88c6b9d618d1e068166bbf2b07757350791d) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81	mx8dxmek \
82
83mx8dxl-flavorlist = \
84	mx8dxlevk \
85
86mx8ulp-flavorlist = \
87	mx8ulpevk \
88
89mx93-flavorlist = \
90	mx93evk \
91
92ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
93$(call force,CFG_MX6,y)
94$(call force,CFG_MX6UL,y)
95$(call force,CFG_TEE_CORE_NB_CORE,1)
96$(call force,CFG_TZC380,y)
97include core/arch/arm/cpu/cortex-a7.mk
98else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
99$(call force,CFG_MX6,y)
100$(call force,CFG_MX6ULL,y)
101$(call force,CFG_TEE_CORE_NB_CORE,1)
102$(call force,CFG_TZC380,y)
103$(call force,CFG_IMX_CAAM,n)
104$(call force,CFG_NXP_CAAM,n)
105$(call force,CFG_IMX_DCP,y)
106include core/arch/arm/cpu/cortex-a7.mk
107else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
108$(call force,CFG_MX6,y)
109$(call force,CFG_MX6Q,y)
110$(call force,CFG_TEE_CORE_NB_CORE,4)
111$(call force,CFG_TZC380,y)
112else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
113$(call force,CFG_MX6,y)
114$(call force,CFG_MX6QP,y)
115$(call force,CFG_TEE_CORE_NB_CORE,4)
116else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
117$(call force,CFG_MX6,y)
118$(call force,CFG_MX6D,y)
119$(call force,CFG_TEE_CORE_NB_CORE,2)
120$(call force,CFG_TZC380,y)
121else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
122$(call force,CFG_MX6,y)
123$(call force,CFG_MX6DL,y)
124$(call force,CFG_TEE_CORE_NB_CORE,2)
125$(call force,CFG_TZC380,y)
126else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
127$(call force,CFG_MX6,y)
128$(call force,CFG_MX6S,y)
129$(call force,CFG_TEE_CORE_NB_CORE,1)
130else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
131$(call force,CFG_MX6,y)
132$(call force,CFG_MX6SL,y)
133$(call force,CFG_TEE_CORE_NB_CORE,1)
134$(call force,CFG_IMX_CAAM,n)
135$(call force,CFG_NXP_CAAM,n)
136$(call force,CFG_IMX_DCP,y)
137else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
138$(call force,CFG_MX6,y)
139$(call force,CFG_MX6SLL,y)
140$(call force,CFG_TEE_CORE_NB_CORE,1)
141$(call force,CFG_IMX_CAAM,n)
142$(call force,CFG_NXP_CAAM,n)
143$(call force,CFG_IMX_DCP,y)
144$(call force,CFG_NO_SMP,y)
145else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
146$(call force,CFG_MX6,y)
147$(call force,CFG_MX6SX,y)
148$(call force,CFG_TEE_CORE_NB_CORE,1)
149else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
150$(call force,CFG_MX7,y)
151$(call force,CFG_TEE_CORE_NB_CORE,1)
152include core/arch/arm/cpu/cortex-a7.mk
153else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
154$(call force,CFG_MX7,y)
155$(call force,CFG_TEE_CORE_NB_CORE,2)
156include core/arch/arm/cpu/cortex-a7.mk
157else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
158$(call force,CFG_MX7ULP,y)
159$(call force,CFG_TEE_CORE_NB_CORE,1)
160$(call force,CFG_TZC380,n)
161$(call force,CFG_IMX_CSU,n)
162include core/arch/arm/cpu/cortex-a7.mk
163else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
164$(call force,CFG_MX8MQ,y)
165$(call force,CFG_MX8M,y)
166$(call force,CFG_ARM64_core,y)
167CFG_DRAM_BASE ?= 0x40000000
168CFG_TEE_CORE_NB_CORE ?= 4
169else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
170$(call force,CFG_MX8MM,y)
171$(call force,CFG_MX8M,y)
172$(call force,CFG_ARM64_core,y)
173CFG_DRAM_BASE ?= 0x40000000
174CFG_TEE_CORE_NB_CORE ?= 4
175else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
176$(call force,CFG_MX8MN,y)
177$(call force,CFG_MX8M,y)
178$(call force,CFG_ARM64_core,y)
179CFG_DRAM_BASE ?= 0x40000000
180CFG_TEE_CORE_NB_CORE ?= 4
181else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
182$(call force,CFG_MX8MP,y)
183$(call force,CFG_MX8M,y)
184$(call force,CFG_ARM64_core,y)
185CFG_DRAM_BASE ?= 0x40000000
186CFG_TEE_CORE_NB_CORE ?= 4
187else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
188$(call force,CFG_MX8QM,y)
189$(call force,CFG_ARM64_core,y)
190$(call force,CFG_IMX_SNVS,n)
191CFG_IMX_LPUART ?= y
192CFG_DRAM_BASE ?= 0x80000000
193CFG_TEE_CORE_NB_CORE ?= 6
194$(call force,CFG_IMX_OCOTP,n)
195else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
196$(call force,CFG_MX8QX,y)
197$(call force,CFG_ARM64_core,y)
198$(call force,CFG_IMX_SNVS,n)
199CFG_IMX_LPUART ?= y
200CFG_DRAM_BASE ?= 0x80000000
201CFG_TEE_CORE_NB_CORE ?= 4
202$(call force,CFG_IMX_OCOTP,n)
203else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
204$(call force,CFG_MX8DXL,y)
205$(call force,CFG_ARM64_core,y)
206$(call force,CFG_IMX_SNVS,n)
207CFG_IMX_LPUART ?= y
208CFG_DRAM_BASE ?= 0x80000000
209$(call force,CFG_TEE_CORE_NB_CORE,2)
210$(call force,CFG_IMX_OCOTP,n)
211else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
212$(call force,CFG_MX8ULP,y)
213$(call force,CFG_ARM64_core,y)
214CFG_IMX_LPUART ?= y
215CFG_DRAM_BASE ?= 0x80000000
216CFG_TEE_CORE_NB_CORE ?= 2
217$(call force,CFG_NXP_SNVS,n)
218$(call force,CFG_IMX_OCOTP,n)
219CFG_IMX_MU ?= y
220CFG_IMX_ELE ?= n
221else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
222$(call force,CFG_MX93,y)
223$(call force,CFG_ARM64_core,y)
224CFG_IMX_LPUART ?= y
225CFG_DRAM_BASE ?= 0x80000000
226CFG_TEE_CORE_NB_CORE ?= 2
227$(call force,CFG_NXP_SNVS,n)
228$(call force,CFG_IMX_OCOTP,n)
229$(call force,CFG_TZC380,n)
230$(call force,CFG_CRYPTO_DRIVER,n)
231$(call force,CFG_NXP_CAAM,n)
232CFG_IMX_MU ?= y
233CFG_IMX_ELE ?= n
234else
235$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
236endif
237
238ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
239CFG_DDR_SIZE ?= 0x40000000
240CFG_NS_ENTRY_ADDR ?= 0x80800000
241CFG_IMX_WDOG_EXT_RESET ?= y
242endif
243
244ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
245CFG_DDR_SIZE ?= 0x40000000
246CFG_UART_BASE ?= UART1_BASE
247CFG_IMX_WDOG_EXT_RESET ?= y
248endif
249
250ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
251CFG_DDR_SIZE ?= 0x20000000
252CFG_NS_ENTRY_ADDR ?= 0x87800000
253CFG_DT_ADDR ?= 0x83100000
254CFG_UART_BASE ?= UART5_BASE
255CFG_BOOT_SECONDARY_REQUEST ?= n
256CFG_EXTERNAL_DTB_OVERLAY ?= y
257CFG_IMX_WDOG_EXT_RESET ?= y
258endif
259
260ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
261CFG_DDR_SIZE ?= 0x20000000
262CFG_NS_ENTRY_ADDR ?= 0x80800000
263CFG_BOOT_SECONDARY_REQUEST ?= n
264endif
265
266ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
267CFG_DDR_SIZE ?= 0x20000000
268CFG_NS_ENTRY_ADDR ?= 0x87800000
269CFG_DT_ADDR ?= 0x83100000
270CFG_BOOT_SECONDARY_REQUEST ?= n
271CFG_EXTERNAL_DTB_OVERLAY = y
272CFG_IMX_WDOG_EXT_RESET = y
273endif
274
275ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
276CFG_DDR_SIZE ?= 0x40000000
277CFG_NS_ENTRY_ADDR ?= 0x60800000
278CFG_UART_BASE ?= UART4_BASE
279endif
280
281ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
282	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
283	mx6dapalis mx6qapalis))
284CFG_DDR_SIZE ?= 0x40000000
285CFG_NS_ENTRY_ADDR ?= 0x12000000
286endif
287
288ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
289	mx6dlsabreauto mx6solosabreauto))
290CFG_DDR_SIZE ?= 0x80000000
291CFG_NS_ENTRY_ADDR ?= 0x12000000
292CFG_UART_BASE ?= UART4_BASE
293endif
294
295ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
296CFG_DDR_SIZE ?= 0x80000000
297CFG_UART_BASE ?= UART1_BASE
298endif
299
300ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
301CFG_DDR_SIZE ?= 0x40000000
302CFG_NS_ENTRY_ADDR ?= 0x12000000
303endif
304
305ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
306CFG_DDR_SIZE ?= 0x40000000
307CFG_NS_ENTRY_ADDR ?= 0x12000000
308CFG_UART_BASE ?= UART2_BASE
309endif
310
311ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
312CFG_NS_ENTRY_ADDR ?= 0x80800000
313CFG_DDR_SIZE ?= 0x40000000
314endif
315
316ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
317CFG_NS_ENTRY_ADDR ?= 0x80800000
318CFG_DDR_SIZE ?= 0x80000000
319endif
320
321ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
322CFG_DDR_SIZE ?= 0x80000000
323CFG_NS_ENTRY_ADDR ?= 0x80800000
324endif
325
326ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
327CFG_DDR_SIZE ?= 0x40000000
328CFG_NS_ENTRY_ADDR ?= 0x80800000
329endif
330
331ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
332CFG_DDR_SIZE ?= 0x40000000
333CFG_UART_BASE ?= UART1_BASE
334endif
335
336ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
337CFG_DDR_SIZE ?= 0x20000000
338CFG_NS_ENTRY_ADDR ?= 0x80800000
339endif
340
341ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
342CFG_DDR_SIZE ?= 0x10000000
343CFG_NS_ENTRY_ADDR ?= 0x80800000
344CFG_UART_BASE ?= UART5_BASE
345endif
346
347ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
348CFG_DDR_SIZE ?= 0x10000000
349CFG_NS_ENTRY_ADDR ?= 0x80800000
350endif
351
352ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
353CFG_DDR_SIZE ?= 0x10000000
354CFG_UART_BASE ?= UART7_BASE
355endif
356
357ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
358CFG_DDR_SIZE ?= 0xc0000000
359CFG_UART_BASE ?= UART1_BASE
360endif
361
362ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
363CFG_DDR_SIZE ?= 0x80000000
364CFG_UART_BASE ?= UART2_BASE
365endif
366
367ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
368CFG_DDR_SIZE ?= 0x40000000
369CFG_UART_BASE ?= UART3_BASE
370CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
371CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
372endif
373
374ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
375CFG_DDR_SIZE ?= 0x80000000
376CFG_UART_BASE ?= UART2_BASE
377endif
378
379ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
380CFG_DDR_SIZE ?= UL(0x180000000)
381CFG_UART_BASE ?= UART2_BASE
382$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
383$(call force,CFG_CORE_ARM64_PA_BITS,36)
384endif
385
386ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
387CFG_DDR_SIZE ?= UL(0x180000000)
388CFG_UART_BASE ?= UART3_BASE
389CFG_TZDRAM_START ?= 0x56000000
390$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
391$(call force,CFG_CORE_ARM64_PA_BITS,36)
392endif
393
394ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
395CFG_DDR_SIZE ?= 0x80000000
396CFG_UART_BASE ?= UART0_BASE
397CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
398CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
399CFG_CORE_ARM64_PA_BITS ?= 40
400endif
401
402ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
403CFG_DDR_SIZE ?= 0x40000000
404CFG_UART_BASE ?= UART0_BASE
405$(call force,CFG_MX8DX,y)
406endif
407
408ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
409CFG_DDR_SIZE ?= 0x40000000
410CFG_UART_BASE ?= UART0_BASE
411CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
412CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
413CFG_CORE_ARM64_PA_BITS ?= 40
414endif
415
416ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
417CFG_DDR_SIZE ?= 0x80000000
418CFG_UART_BASE ?= UART5_BASE
419endif
420
421ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk))
422CFG_DDR_SIZE ?= 0x80000000
423CFG_UART_BASE ?= UART1_BASE
424endif
425
426# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
427ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
428	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
429include core/arch/arm/cpu/cortex-a9.mk
430
431$(call force,CFG_PL310,y)
432
433CFG_PL310_LOCKED ?= y
434CFG_ENABLE_SCTLR_RR ?= y
435CFG_IMX_SCU ?= y
436endif
437
438ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
439CFG_DRAM_BASE ?= 0x10000000
440endif
441
442ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
443	$(CFG_MX6SX)))
444CFG_DRAM_BASE ?= 0x80000000
445endif
446
447ifeq ($(filter y, $(CFG_MX7)), y)
448CFG_INIT_CNTVOFF ?= y
449CFG_DRAM_BASE ?= 0x80000000
450endif
451
452ifeq ($(filter y, $(CFG_MX7ULP)), y)
453CFG_INIT_CNTVOFF ?= y
454CFG_DRAM_BASE ?= UL(0x60000000)
455$(call force,CFG_IMX_LPUART,y)
456$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
457endif
458
459ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
460$(call force,CFG_GIC,y)
461
462CFG_BOOT_SECONDARY_REQUEST ?= y
463CFG_DT ?= y
464CFG_DTB_MAX_SIZE ?= 0x20000
465CFG_PAGEABLE_ADDR ?= 0
466CFG_PSCI_ARM32 ?= y
467CFG_SECURE_TIME_SOURCE_REE ?= y
468CFG_UART_BASE ?= UART1_BASE
469endif
470
471ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
472$(call force,CFG_IMX_UART,y)
473CFG_IMX_SNVS ?= y
474endif
475
476ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
477CFG_IMX_CSU ?= y
478endif
479
480ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
481CFG_HWSUPP_MEM_PERM_WXN = n
482CFG_IMX_WDOG ?= y
483endif
484
485ifeq ($(CFG_ARM64_core),y)
486# arm-v8 platforms
487include core/arch/arm/cpu/cortex-armv8-0.mk
488$(call force,CFG_ARM_GICV3,y)
489$(call force,CFG_GIC,y)
490$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
491$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
492
493CFG_CRYPTO_WITH_CE ?= y
494
495supported-ta-targets = ta_arm64
496endif
497
498CFG_TZDRAM_SIZE ?= 0x01e00000
499CFG_SHMEM_SIZE ?= 0x00200000
500CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
501CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
502
503# Enable embedded tests by default
504CFG_ENABLE_EMBEDDED_TESTS ?= y
505
506# Set default heap size for imx platforms to 128k
507CFG_CORE_HEAP_SIZE ?= 131072
508
509CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
510CFG_MMAP_REGIONS ?= 24
511
512# SE05X and OCOTP both implement tee_otp_get_die_id()
513ifeq ($(CFG_NXP_SE05X),y)
514$(call force,CFG_IMX_OCOTP,n)
515endif
516CFG_IMX_OCOTP ?= y
517CFG_IMX_DIGPROG ?= y
518CFG_PKCS11_TA ?= y
519
520# Almost all platforms include CAAM HW Modules, except the
521# ones forced to be disabled
522CFG_NXP_CAAM ?= n
523
524ifeq ($(CFG_NXP_CAAM),y)
525ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
526CFG_IMX_SC ?= y
527CFG_IMX_MU ?= y
528endif
529
530else
531
532ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
533CFG_IMX_CAAM ?= y
534endif
535
536endif
537
538