xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 0960b6765c51598643bdb226a3bfaeab1b0e608f) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate \
68	mx8mm_phyboard_polis \
69	mx8mm_phygate_tauri_l
70
71mx8mn-flavorlist = \
72	mx8mnevk
73
74mx8mp-flavorlist = \
75	mx8mpevk \
76	mx8mp_rsb3720_6g \
77	mx8mp_phyboard_pollux \
78	mx8mp_libra_fpsc
79
80mx8qm-flavorlist = \
81	mx8qmmek \
82
83mx8qx-flavorlist = \
84	mx8qxpmek \
85	mx8dxmek \
86
87mx8dxl-flavorlist = \
88	mx8dxlevk \
89
90mx8ulp-flavorlist = \
91	mx8ulpevk \
92
93mx93-flavorlist = \
94	mx93evk \
95
96mx95-flavorlist = \
97	mx95evk \
98
99mx91-flavorlist = \
100	mx91evk \
101
102ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
103$(call force,CFG_MX6,y)
104$(call force,CFG_MX6UL,y)
105$(call force,CFG_TEE_CORE_NB_CORE,1)
106$(call force,CFG_TZC380,y)
107include core/arch/arm/cpu/cortex-a7.mk
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6ULL,y)
111$(call force,CFG_TEE_CORE_NB_CORE,1)
112$(call force,CFG_TZC380,y)
113$(call force,CFG_IMX_CAAM,n)
114$(call force,CFG_NXP_CAAM,n)
115$(call force,CFG_IMX_DCP,y)
116include core/arch/arm/cpu/cortex-a7.mk
117else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
118$(call force,CFG_MX6,y)
119$(call force,CFG_MX6Q,y)
120$(call force,CFG_TEE_CORE_NB_CORE,4)
121$(call force,CFG_TZC380,y)
122else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
123$(call force,CFG_MX6,y)
124$(call force,CFG_MX6QP,y)
125$(call force,CFG_TEE_CORE_NB_CORE,4)
126else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
127$(call force,CFG_MX6,y)
128$(call force,CFG_MX6D,y)
129$(call force,CFG_TEE_CORE_NB_CORE,2)
130$(call force,CFG_TZC380,y)
131else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
132$(call force,CFG_MX6,y)
133$(call force,CFG_MX6DL,y)
134$(call force,CFG_TEE_CORE_NB_CORE,2)
135$(call force,CFG_TZC380,y)
136else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
137$(call force,CFG_MX6,y)
138$(call force,CFG_MX6S,y)
139$(call force,CFG_TEE_CORE_NB_CORE,1)
140else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
141$(call force,CFG_MX6,y)
142$(call force,CFG_MX6SL,y)
143$(call force,CFG_TEE_CORE_NB_CORE,1)
144$(call force,CFG_IMX_CAAM,n)
145$(call force,CFG_NXP_CAAM,n)
146$(call force,CFG_IMX_DCP,y)
147else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
148$(call force,CFG_MX6,y)
149$(call force,CFG_MX6SLL,y)
150$(call force,CFG_TEE_CORE_NB_CORE,1)
151$(call force,CFG_IMX_CAAM,n)
152$(call force,CFG_NXP_CAAM,n)
153$(call force,CFG_IMX_DCP,y)
154$(call force,CFG_NO_SMP,y)
155else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
156$(call force,CFG_MX6,y)
157$(call force,CFG_MX6SX,y)
158$(call force,CFG_TEE_CORE_NB_CORE,1)
159else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
160$(call force,CFG_MX7,y)
161$(call force,CFG_TEE_CORE_NB_CORE,1)
162include core/arch/arm/cpu/cortex-a7.mk
163else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
164$(call force,CFG_MX7,y)
165$(call force,CFG_TEE_CORE_NB_CORE,2)
166include core/arch/arm/cpu/cortex-a7.mk
167else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
168$(call force,CFG_MX7ULP,y)
169$(call force,CFG_TEE_CORE_NB_CORE,1)
170$(call force,CFG_TZC380,n)
171$(call force,CFG_IMX_CSU,n)
172include core/arch/arm/cpu/cortex-a7.mk
173else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
174$(call force,CFG_MX8MQ,y)
175$(call force,CFG_MX8M,y)
176$(call force,CFG_ARM64_core,y)
177$(call force,CFG_TZC380,y)
178CFG_DRAM_BASE ?= 0x40000000
179CFG_TEE_CORE_NB_CORE ?= 4
180else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
181$(call force,CFG_MX8MM,y)
182$(call force,CFG_MX8M,y)
183$(call force,CFG_ARM64_core,y)
184$(call force,CFG_TZC380,y)
185CFG_DRAM_BASE ?= 0x40000000
186CFG_TEE_CORE_NB_CORE ?= 4
187else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
188$(call force,CFG_MX8MN,y)
189$(call force,CFG_MX8M,y)
190$(call force,CFG_ARM64_core,y)
191$(call force,CFG_TZC380,y)
192CFG_DRAM_BASE ?= 0x40000000
193CFG_TEE_CORE_NB_CORE ?= 4
194else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
195$(call force,CFG_MX8MP,y)
196$(call force,CFG_MX8M,y)
197$(call force,CFG_ARM64_core,y)
198$(call force,CFG_TZC380,y)
199CFG_DRAM_BASE ?= 0x40000000
200CFG_TEE_CORE_NB_CORE ?= 4
201else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
202$(call force,CFG_MX8QM,y)
203$(call force,CFG_ARM64_core,y)
204$(call force,CFG_IMX_SNVS,n)
205CFG_IMX_LPUART ?= y
206CFG_DRAM_BASE ?= 0x80000000
207CFG_TEE_CORE_NB_CORE ?= 6
208$(call force,CFG_IMX_OCOTP,n)
209else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
210$(call force,CFG_MX8QX,y)
211$(call force,CFG_ARM64_core,y)
212$(call force,CFG_IMX_SNVS,n)
213CFG_IMX_LPUART ?= y
214CFG_DRAM_BASE ?= 0x80000000
215CFG_TEE_CORE_NB_CORE ?= 4
216$(call force,CFG_IMX_OCOTP,n)
217else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
218$(call force,CFG_MX8DXL,y)
219$(call force,CFG_ARM64_core,y)
220$(call force,CFG_IMX_SNVS,n)
221CFG_IMX_LPUART ?= y
222CFG_DRAM_BASE ?= 0x80000000
223$(call force,CFG_TEE_CORE_NB_CORE,2)
224$(call force,CFG_IMX_OCOTP,n)
225else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
226$(call force,CFG_MX8ULP,y)
227$(call force,CFG_ARM64_core,y)
228CFG_IMX_LPUART ?= y
229CFG_DRAM_BASE ?= 0x80000000
230CFG_TEE_CORE_NB_CORE ?= 2
231$(call force,CFG_NXP_SNVS,n)
232$(call force,CFG_IMX_OCOTP,n)
233CFG_IMX_MU ?= y
234CFG_IMX_ELE ?= n
235else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
236$(call force,CFG_MX93,y)
237$(call force,CFG_ARM64_core,y)
238CFG_IMX_LPUART ?= y
239CFG_DRAM_BASE ?= 0x80000000
240CFG_TEE_CORE_NB_CORE ?= 2
241$(call force,CFG_NXP_SNVS,n)
242$(call force,CFG_IMX_OCOTP,n)
243$(call force,CFG_TZC380,n)
244$(call force,CFG_CRYPTO_DRIVER,n)
245$(call force,CFG_NXP_CAAM,n)
246CFG_IMX_MU ?= y
247CFG_IMX_ELE ?= y
248else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
249$(call force,CFG_MX95,y)
250$(call force,CFG_ARM64_core,y)
251CFG_IMX_LPUART ?= y
252CFG_DRAM_BASE ?= 0x80000000
253CFG_TEE_CORE_NB_CORE ?= 6
254$(call force,CFG_NXP_SNVS,n)
255$(call force,CFG_IMX_OCOTP,n)
256$(call force,CFG_TZC380,n)
257$(call force,CFG_NXP_CAAM,n)
258else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
259$(call force,CFG_MX91,y)
260$(call force,CFG_ARM64_core,y)
261CFG_IMX_LPUART ?= y
262CFG_DRAM_BASE ?= 0x80000000
263CFG_TEE_CORE_NB_CORE ?= 1
264$(call force,CFG_NXP_SNVS,n)
265$(call force,CFG_IMX_OCOTP,n)
266$(call force,CFG_TZC380,n)
267$(call force,CFG_NXP_CAAM,n)
268CFG_IMX_MU ?= y
269CFG_IMX_ELE ?= y
270else
271$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
272endif
273
274ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
275CFG_DDR_SIZE ?= 0x40000000
276CFG_NS_ENTRY_ADDR ?= 0x80800000
277CFG_IMX_WDOG_EXT_RESET ?= y
278endif
279
280ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
281CFG_DDR_SIZE ?= 0x40000000
282CFG_UART_BASE ?= UART1_BASE
283CFG_IMX_WDOG_EXT_RESET ?= y
284endif
285
286ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
287CFG_DDR_SIZE ?= 0x20000000
288CFG_NS_ENTRY_ADDR ?= 0x87800000
289CFG_DT_ADDR ?= 0x83100000
290CFG_UART_BASE ?= UART5_BASE
291CFG_BOOT_SECONDARY_REQUEST ?= n
292CFG_EXTERNAL_DTB_OVERLAY ?= y
293CFG_IMX_WDOG_EXT_RESET ?= y
294endif
295
296ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
297CFG_DDR_SIZE ?= 0x20000000
298CFG_NS_ENTRY_ADDR ?= 0x80800000
299CFG_BOOT_SECONDARY_REQUEST ?= n
300endif
301
302ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
303CFG_DDR_SIZE ?= 0x20000000
304CFG_NS_ENTRY_ADDR ?= 0x87800000
305CFG_DT_ADDR ?= 0x83100000
306CFG_BOOT_SECONDARY_REQUEST ?= n
307CFG_EXTERNAL_DTB_OVERLAY = y
308CFG_IMX_WDOG_EXT_RESET = y
309endif
310
311ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
312CFG_DDR_SIZE ?= 0x40000000
313CFG_NS_ENTRY_ADDR ?= 0x60800000
314CFG_UART_BASE ?= UART4_BASE
315endif
316
317ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
318	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
319	mx6dapalis mx6qapalis))
320CFG_DDR_SIZE ?= 0x40000000
321CFG_NS_ENTRY_ADDR ?= 0x12000000
322endif
323
324ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
325	mx6dlsabreauto mx6solosabreauto))
326CFG_DDR_SIZE ?= 0x80000000
327CFG_NS_ENTRY_ADDR ?= 0x12000000
328CFG_UART_BASE ?= UART4_BASE
329endif
330
331ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
332CFG_DDR_SIZE ?= 0x80000000
333CFG_UART_BASE ?= UART1_BASE
334endif
335
336ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
337CFG_DDR_SIZE ?= 0x40000000
338CFG_NS_ENTRY_ADDR ?= 0x12000000
339endif
340
341ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
342CFG_DDR_SIZE ?= 0x40000000
343CFG_NS_ENTRY_ADDR ?= 0x12000000
344CFG_UART_BASE ?= UART2_BASE
345endif
346
347ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
348CFG_NS_ENTRY_ADDR ?= 0x80800000
349CFG_DDR_SIZE ?= 0x40000000
350endif
351
352ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
353CFG_NS_ENTRY_ADDR ?= 0x80800000
354CFG_DDR_SIZE ?= 0x80000000
355endif
356
357ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
358CFG_DDR_SIZE ?= 0x80000000
359CFG_NS_ENTRY_ADDR ?= 0x80800000
360endif
361
362ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
363CFG_DDR_SIZE ?= 0x40000000
364CFG_NS_ENTRY_ADDR ?= 0x80800000
365endif
366
367ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
368CFG_DDR_SIZE ?= 0x40000000
369CFG_UART_BASE ?= UART1_BASE
370endif
371
372ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
373CFG_DDR_SIZE ?= 0x20000000
374CFG_NS_ENTRY_ADDR ?= 0x80800000
375endif
376
377ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
378CFG_DDR_SIZE ?= 0x10000000
379CFG_NS_ENTRY_ADDR ?= 0x80800000
380CFG_UART_BASE ?= UART5_BASE
381endif
382
383ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
384CFG_DDR_SIZE ?= 0x10000000
385CFG_NS_ENTRY_ADDR ?= 0x80800000
386endif
387
388ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
389CFG_DDR_SIZE ?= 0x10000000
390CFG_UART_BASE ?= UART7_BASE
391endif
392
393ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
394CFG_DDR_SIZE ?= 0xc0000000
395CFG_UART_BASE ?= UART1_BASE
396endif
397
398ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
399CFG_DDR_SIZE ?= 0x80000000
400CFG_UART_BASE ?= UART2_BASE
401endif
402
403ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
404CFG_DDR_SIZE ?= 0x40000000
405CFG_UART_BASE ?= UART3_BASE
406CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
407CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
408endif
409
410ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
411CFG_DDR_SIZE ?= 0x40000000
412CFG_UART_BASE ?= UART3_BASE
413$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
414$(call force,CFG_CORE_ARM64_PA_BITS,36)
415endif
416
417ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
418CFG_DDR_SIZE ?= 0x80000000
419CFG_UART_BASE ?= UART3_BASE
420$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
421$(call force,CFG_CORE_ARM64_PA_BITS,36)
422endif
423
424ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
425CFG_DDR_SIZE ?= 0x80000000
426CFG_UART_BASE ?= UART2_BASE
427endif
428
429ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
430CFG_DDR_SIZE ?= UL(0x180000000)
431CFG_UART_BASE ?= UART2_BASE
432$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
433$(call force,CFG_CORE_ARM64_PA_BITS,36)
434endif
435
436ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
437CFG_DDR_SIZE ?= 0x40000000
438CFG_UART_BASE ?= UART4_BASE
439$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
440$(call force,CFG_CORE_ARM64_PA_BITS,36)
441endif
442
443ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
444CFG_DDR_SIZE ?= 0x40000000
445CFG_UART_BASE ?= UART1_BASE
446$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
447$(call force,CFG_CORE_ARM64_PA_BITS,36)
448endif
449
450ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
451CFG_DDR_SIZE ?= UL(0x180000000)
452CFG_UART_BASE ?= UART3_BASE
453CFG_TZDRAM_START ?= 0x56000000
454$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
455$(call force,CFG_CORE_ARM64_PA_BITS,36)
456endif
457
458ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
459CFG_DDR_SIZE ?= 0x80000000
460CFG_UART_BASE ?= UART0_BASE
461CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
462CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
463CFG_CORE_ARM64_PA_BITS ?= 40
464endif
465
466ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
467CFG_DDR_SIZE ?= 0x40000000
468CFG_UART_BASE ?= UART0_BASE
469$(call force,CFG_MX8DX,y)
470endif
471
472ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
473CFG_DDR_SIZE ?= 0x40000000
474CFG_UART_BASE ?= UART0_BASE
475CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
476CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
477CFG_CORE_ARM64_PA_BITS ?= 40
478endif
479
480ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
481CFG_DDR_SIZE ?= 0x80000000
482CFG_UART_BASE ?= UART5_BASE
483endif
484
485ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
486CFG_DDR_SIZE ?= 0x80000000
487CFG_UART_BASE ?= UART1_BASE
488endif
489
490ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk))
491CFG_DDR_SIZE ?= 0x80000000
492CFG_UART_BASE ?= UART1_BASE
493CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
494CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
495CFG_CORE_ARM64_PA_BITS ?= 40
496endif
497
498# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
499ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
500	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
501include core/arch/arm/cpu/cortex-a9.mk
502
503$(call force,CFG_PL310,y)
504
505CFG_PL310_LOCKED ?= y
506CFG_ENABLE_SCTLR_RR ?= y
507CFG_IMX_SCU ?= y
508endif
509
510ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
511CFG_DRAM_BASE ?= 0x10000000
512endif
513
514ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
515	$(CFG_MX6SX)))
516CFG_DRAM_BASE ?= 0x80000000
517endif
518
519ifeq ($(filter y, $(CFG_MX7)), y)
520CFG_INIT_CNTVOFF ?= y
521CFG_DRAM_BASE ?= 0x80000000
522endif
523
524ifeq ($(filter y, $(CFG_MX7ULP)), y)
525CFG_INIT_CNTVOFF ?= y
526CFG_DRAM_BASE ?= UL(0x60000000)
527$(call force,CFG_IMX_LPUART,y)
528$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
529endif
530
531ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
532$(call force,CFG_GIC,y)
533
534CFG_BOOT_SECONDARY_REQUEST ?= y
535CFG_DT ?= y
536CFG_DTB_MAX_SIZE ?= 0x20000
537CFG_PAGEABLE_ADDR ?= 0
538CFG_PSCI_ARM32 ?= y
539CFG_SECURE_TIME_SOURCE_REE ?= y
540CFG_UART_BASE ?= UART1_BASE
541endif
542
543ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
544$(call force,CFG_IMX_UART,y)
545CFG_IMX_SNVS ?= y
546endif
547
548ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
549CFG_IMX_CSU ?= y
550endif
551
552ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
553CFG_HWSUPP_MEM_PERM_WXN = n
554CFG_IMX_WDOG ?= y
555endif
556
557ifeq ($(CFG_ARM64_core),y)
558# arm-v8 platforms
559include core/arch/arm/cpu/cortex-armv8-0.mk
560$(call force,CFG_ARM_GICV3,y)
561$(call force,CFG_GIC,y)
562$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
563$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
564
565CFG_CRYPTO_WITH_CE ?= y
566
567supported-ta-targets = ta_arm64
568endif
569
570CFG_TZDRAM_SIZE ?= 0x01e00000
571CFG_SHMEM_SIZE ?= 0x00200000
572CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
573CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
574
575# Enable embedded tests by default
576CFG_ENABLE_EMBEDDED_TESTS ?= y
577CFG_ATTESTATION_PTA ?= y
578
579# Set default heap size for imx platforms to 128k
580CFG_CORE_HEAP_SIZE ?= 131072
581
582CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
583CFG_MMAP_REGIONS ?= 24
584
585# SE05X and OCOTP both implement tee_otp_get_die_id()
586ifeq ($(CFG_NXP_SE05X),y)
587$(call force,CFG_IMX_OCOTP,n)
588$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
589endif
590CFG_IMX_OCOTP ?= y
591CFG_IMX_DIGPROG ?= y
592CFG_PKCS11_TA ?= y
593CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
594
595# Almost all platforms include CAAM HW Modules, except the
596# ones forced to be disabled
597CFG_NXP_CAAM ?= n
598
599ifeq ($(CFG_NXP_CAAM),y)
600ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
601CFG_IMX_SC ?= y
602CFG_IMX_MU ?= y
603endif
604
605else
606
607ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
608CFG_IMX_CAAM ?= y
609endif
610
611endif
612