1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, HiSilicon Technologies Co., Ltd. 4 */ 5 6 #include <console.h> 7 #include <io.h> 8 #include <kernel/generic_boot.h> 9 #include <kernel/misc.h> 10 #include <kernel/panic.h> 11 #include <kernel/pm_stubs.h> 12 #include <mm/core_mmu.h> 13 #include <mm/core_memprot.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <sm/optee_smc.h> 17 #include <sm/psci.h> 18 #include <tee/entry_std.h> 19 #include <tee/entry_fast.h> 20 21 #define REG_CPU_SUSSYS_RESET 0xcc 22 #define REG_CPU_START_COMMAND 0x0 23 #define REG_CPU_START_ADDR 0x4 24 #define REG_SYSCTRL_RESET 0x4 25 #define RELEASE_CORE_MASK (BIT32(25) | BIT32(1)) 26 27 int psci_features(uint32_t psci_fid) 28 { 29 switch (psci_fid) { 30 case PSCI_PSCI_FEATURES: 31 case PSCI_VERSION: 32 case PSCI_SYSTEM_RESET: 33 #ifdef CFG_BOOT_SECONDARY_REQUEST 34 case PSCI_CPU_ON: 35 #endif 36 return PSCI_RET_SUCCESS; 37 default: 38 return PSCI_RET_NOT_SUPPORTED; 39 } 40 } 41 42 uint32_t psci_version(void) 43 { 44 return PSCI_VERSION_1_0; 45 } 46 47 void psci_system_reset(void) 48 { 49 vaddr_t sysctrl = core_mmu_get_va(SYS_CTRL_BASE, MEM_AREA_IO_SEC); 50 51 if (!sysctrl) { 52 EMSG("no sysctrl mapping, hang here"); 53 panic(); 54 } 55 56 io_write32(sysctrl + REG_SYSCTRL_RESET, 0xdeadbeef); 57 } 58 59 #ifdef CFG_BOOT_SECONDARY_REQUEST 60 int psci_cpu_on(uint32_t core_idx, uint32_t entry, 61 uint32_t context_id) 62 { 63 uint32_t val = 0; 64 size_t pos = get_core_pos_mpidr(core_idx); 65 vaddr_t bootsram = core_mmu_get_va(BOOTSRAM_BASE, MEM_AREA_IO_SEC); 66 vaddr_t crg = core_mmu_get_va(CPU_CRG_BASE, MEM_AREA_IO_SEC); 67 68 if (!bootsram || !crg) { 69 EMSG("No bootsram or crg mapping"); 70 return PSCI_RET_INVALID_PARAMETERS; 71 } 72 73 if ((pos == 0) || (pos >= CFG_TEE_CORE_NB_CORE)) 74 return PSCI_RET_INVALID_PARAMETERS; 75 76 /* set secondary core's NS entry addresses */ 77 generic_boot_set_core_ns_entry(pos, entry, context_id); 78 79 val = virt_to_phys((void *)TEE_TEXT_VA_START); 80 io_write32(bootsram + REG_CPU_START_ADDR, val); 81 io_write32(bootsram + REG_CPU_START_COMMAND, 0xe51ff004); 82 83 /* release secondary core */ 84 io_clrbits32(crg + REG_CPU_SUSSYS_RESET, RELEASE_CORE_MASK); 85 86 return PSCI_RET_SUCCESS; 87 } 88 #endif 89