xref: /optee_os/core/arch/arm/plat-hisilicon/main.c (revision 5a913ee74d3c71af2a2860ce8a4e7aeab2916f9b)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2019, HiSilicon Technologies Co., Ltd.
4  */
5 
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/pl011.h>
9 #include <kernel/generic_boot.h>
10 #include <kernel/panic.h>
11 #include <kernel/pm_stubs.h>
12 #include <mm/tee_pager.h>
13 #include <mm/core_memprot.h>
14 #include <platform_config.h>
15 #include <stdint.h>
16 #include <tee/entry_std.h>
17 #include <tee/entry_fast.h>
18 
19 static const struct thread_handlers handlers = {
20 	.cpu_on = pm_panic,
21 	.cpu_off = pm_panic,
22 	.cpu_suspend = pm_panic,
23 	.cpu_resume = pm_panic,
24 	.system_off = pm_panic,
25 	.system_reset = pm_panic,
26 };
27 
28 static struct pl011_data console_data;
29 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
30 #ifdef BOOTSRAM_BASE
31 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
32 #endif
33 #ifdef CPU_CRG_BASE
34 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
35 #endif
36 #ifdef SYS_CTRL_BASE
37 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
38 #endif
39 
40 const struct thread_handlers *generic_boot_get_handlers(void)
41 {
42 	return &handlers;
43 }
44 
45 void console_init(void)
46 {
47 	pl011_init(&console_data, CONSOLE_UART_BASE,
48 		CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
49 	register_serial_console(&console_data.chip);
50 }
51