1*b7667020SZeng Tao /* SPDX-License-Identifier: BSD-2-Clause */ 2*b7667020SZeng Tao /* 3*b7667020SZeng Tao * Copyright (c) 2019, HiSilicon Technologies Co., Ltd. 4*b7667020SZeng Tao */ 5*b7667020SZeng Tao 6*b7667020SZeng Tao #ifndef __HI3519AV100_H__ 7*b7667020SZeng Tao #define __HI3519AV100_H__ 8*b7667020SZeng Tao 9*b7667020SZeng Tao #include <mm/generic_ram_layout.h> 10*b7667020SZeng Tao 11*b7667020SZeng Tao /* PL011 */ 12*b7667020SZeng Tao #define PL011_UART0_BASE 0x04540000 13*b7667020SZeng Tao #define PL011_BAUDRATE 115200 14*b7667020SZeng Tao #define PL011_UART0_CLK_IN_HZ 24000000 15*b7667020SZeng Tao 16*b7667020SZeng Tao /* BootSRAM */ 17*b7667020SZeng Tao #define BOOTSRAM_BASE 0x04200000 18*b7667020SZeng Tao #define BOOTSRAM_SIZE 0x1000 19*b7667020SZeng Tao 20*b7667020SZeng Tao /* CPU Reset Control */ 21*b7667020SZeng Tao #define CPU_CRG_BASE 0x04510000 22*b7667020SZeng Tao #define CPU_CRG_SIZE 0x1000 23*b7667020SZeng Tao 24*b7667020SZeng Tao /* Sysctrl Register */ 25*b7667020SZeng Tao #define SYS_CTRL_BASE 0x04520000 26*b7667020SZeng Tao #define SYS_CTRL_SIZE 0x1000 27*b7667020SZeng Tao 28*b7667020SZeng Tao #endif /* __HI3519AV100_H__ */ 29