1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <drivers/pl022_spi.h> 29 #include <drivers/pl061_gpio.h> 30 #include <hikey_peripherals.h> 31 #include <io.h> 32 #include <kernel/tee_time.h> 33 #include <stdint.h> 34 #include <trace.h> 35 #include <util.h> 36 37 #define PL022_STAT 0x00C 38 #define PL022_STAT_BSY SHIFT_U32(1, 4) 39 40 static void spi_cs_callback(enum gpio_level value) 41 { 42 static bool inited; 43 static struct pl061_data pd; 44 vaddr_t gpio6_base = nsec_periph_base(GPIO6_BASE); 45 vaddr_t spi_base = nsec_periph_base(SPI_BASE); 46 47 if (!inited) { 48 pl061_init(&pd); 49 pl061_register(gpio6_base, 6); 50 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 51 pd.chip.ops->set_interrupt(GPIO6_2, GPIO_INTERRUPT_DISABLE); 52 pd.chip.ops->set_direction(GPIO6_2, GPIO_DIR_OUT); 53 inited = true; 54 } 55 56 if (read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 57 DMSG("pl022 busy - do NOT set CS!"); 58 while (read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 59 ; 60 DMSG("pl022 done - set CS!"); 61 62 pd.chip.ops->set_value(GPIO6_2, value); 63 } 64 65 static void spi_set_cs_mux(uint32_t val) 66 { 67 uint32_t data; 68 vaddr_t pmx0_base = nsec_periph_base(PMX0_BASE); 69 70 if (val == PINMUX_SPI) { 71 DMSG("Configure gpio6 pin2 as SPI"); 72 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 73 } else { 74 DMSG("Configure gpio6 pin2 as GPIO"); 75 write32(PINMUX_GPIO, pmx0_base + PMX0_IOMG106); 76 } 77 78 data = read32(pmx0_base + PMX0_IOMG106); 79 if (data) 80 DMSG("gpio6 pin2 is SPI"); 81 else 82 DMSG("gpio6 pin2 is GPIO"); 83 } 84 85 static void spi_test_with_manual_cs_control(void) 86 { 87 struct pl022_data pd; 88 vaddr_t spi_base = nsec_periph_base(SPI_BASE); 89 uint8_t tx[3] = {0x01, 0x80, 0x00}; 90 uint8_t rx[3] = {0}; 91 size_t i, j, len = 3; 92 enum spi_result res; 93 94 spi_set_cs_mux(PINMUX_GPIO); 95 96 DMSG("Set CS callback"); 97 pd.cs_control = PL022_CS_CTRL_MANUAL; 98 99 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 100 DMSG("Configure SPI"); 101 pd.base = spi_base; 102 pd.clk_hz = SPI_CLK_HZ; 103 pd.speed_hz = SPI_10_KHZ; 104 pd.mode = SPI_MODE0; 105 pd.data_size_bits = 8; 106 pd.loopback = true; 107 108 pl022_init(&pd); 109 pd.chip.ops->configure(&pd.chip); 110 pd.chip.ops->start(&pd.chip); 111 112 /* 113 * Pulse CS only once for the whole transmission. 114 * This is the scheme used by the pl022 driver. 115 */ 116 spi_cs_callback(GPIO_LEVEL_HIGH); 117 tee_time_busy_wait(2); 118 spi_cs_callback(GPIO_LEVEL_LOW); 119 for (j = 0; j < 10; j++) { 120 DMSG("SPI test loop: %zu", j); 121 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 122 if (res) { 123 EMSG("SPI transceive error %d", res); 124 break; 125 } 126 127 for (i = 0; i < len; i++) 128 DMSG("rx[%zu] = 0x%x", i, rx[i]); 129 130 tee_time_busy_wait(20); 131 } 132 spi_cs_callback(GPIO_LEVEL_HIGH); 133 134 /* Pulse CS once per transfer */ 135 spi_cs_callback(GPIO_LEVEL_HIGH); 136 tee_time_busy_wait(2); 137 for (j = 10; j < 20; j++) { 138 DMSG("SPI test loop: %zu", j); 139 spi_cs_callback(GPIO_LEVEL_LOW); 140 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 141 if (res) { 142 EMSG("SPI transceive error %d", res); 143 break; 144 } 145 146 for (i = 0; i < len; i++) 147 DMSG("rx[%zu] = 0x%x", i, rx[i]); 148 149 tee_time_busy_wait(20); 150 spi_cs_callback(GPIO_LEVEL_HIGH); 151 } 152 153 /* Pulse CS once per word/byte */ 154 spi_set_cs_mux(PINMUX_SPI); 155 tee_time_busy_wait(2); 156 for (j = 20; j < 30; j++) { 157 DMSG("SPI test loop: %zu", j); 158 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 159 if (res) { 160 EMSG("SPI transceive error %d", res); 161 break; 162 } 163 164 for (i = 0; i < len; i++) 165 DMSG("rx[%zu] = 0x%x", i, rx[i]); 166 167 tee_time_busy_wait(20); 168 } 169 170 pd.chip.ops->end(&pd.chip); 171 } 172 173 static void spi_test_with_registered_cs_cb(void) 174 { 175 struct pl022_data pd; 176 vaddr_t spi_base = nsec_periph_base(SPI_BASE); 177 uint8_t tx[3] = {0x01, 0x80, 0x00}; 178 uint8_t rx[3] = {0}; 179 size_t i, j, len = 3; 180 enum spi_result res; 181 182 spi_set_cs_mux(PINMUX_GPIO); 183 184 DMSG("Set CS callback"); 185 pd.cs_data.cs_cb = spi_cs_callback; 186 pd.cs_control = PL022_CS_CTRL_CB; 187 188 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 189 DMSG("Configure SPI"); 190 pd.base = spi_base; 191 pd.clk_hz = SPI_CLK_HZ; 192 pd.speed_hz = SPI_10_KHZ; 193 pd.mode = SPI_MODE0; 194 pd.data_size_bits = 8; 195 pd.loopback = true; 196 197 pl022_init(&pd); 198 pd.chip.ops->configure(&pd.chip); 199 pd.chip.ops->start(&pd.chip); 200 201 for (j = 0; j < 20; j++) { 202 DMSG("SPI test loop: %zu", j); 203 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 204 if (res) { 205 EMSG("SPI transceive error %d", res); 206 break; 207 } 208 209 for (i = 0; i < len; i++) 210 DMSG("rx[%zu] = 0x%x", i, rx[i]); 211 212 tee_time_busy_wait(20); 213 } 214 215 pd.chip.ops->end(&pd.chip); 216 } 217 218 static void spi_test_with_builtin_cs_control(void) 219 { 220 struct pl061_data pd061; 221 struct pl022_data pd022; 222 vaddr_t gpio6_base = nsec_periph_base(GPIO6_BASE); 223 vaddr_t spi_base = nsec_periph_base(SPI_BASE); 224 uint8_t tx[3] = {0x01, 0x80, 0x00}; 225 uint8_t rx[3] = {0}; 226 size_t i, j, len = 3; 227 enum spi_result res; 228 229 spi_set_cs_mux(PINMUX_GPIO); 230 231 DMSG("gpio6_base: 0x%" PRIxVA "\n", gpio6_base); 232 DMSG("Configure GPIO"); 233 pl061_init(&pd061); 234 pl061_register(gpio6_base, 6); 235 DMSG("Enable software mode control for chip select"); 236 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 237 238 pd022.cs_data.gpio_data.chip = &pd061.chip; 239 pd022.cs_data.gpio_data.pin_num = GPIO6_2; 240 pd022.cs_control = PL022_CS_CTRL_AUTO_GPIO; 241 242 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 243 DMSG("Configure SPI"); 244 pd022.base = spi_base; 245 pd022.clk_hz = SPI_CLK_HZ; 246 pd022.speed_hz = SPI_10_KHZ; 247 pd022.mode = SPI_MODE0; 248 pd022.data_size_bits = 8; 249 pd022.loopback = true; 250 251 pl022_init(&pd022); 252 pd022.chip.ops->configure(&pd022.chip); 253 pd022.chip.ops->start(&pd022.chip); 254 255 for (j = 0; j < 20; j++) { 256 DMSG("SPI test loop: %zu", j); 257 res = pd022.chip.ops->txrx8(&pd022.chip, tx, rx, len); 258 if (res) { 259 EMSG("SPI transceive error %d", res); 260 break; 261 } 262 263 for (i = 0; i < len; i++) 264 DMSG("rx[%zu] = 0x%x", i, rx[i]); 265 266 tee_time_busy_wait(20); 267 } 268 269 pd022.chip.ops->end(&pd022.chip); 270 } 271 272 /* 273 * spi_init() MUST be run before calling this function! 274 * 275 * spi_test runs some loopback tests, so the SPI module will just receive 276 * what is transmitted, i.e. 0x01, 0x80, 0x00. 277 * 278 * In non-loopback mode, the transmitted value will elicit a readback of 279 * the measured value from the ADC chip on the Linksprite 96Boards 280 * Mezzanine card [1], which can be connected to either a sliding 281 * rheostat [2] or photoresistor [3]. 282 * 283 * [1] http://linksprite.com/wiki/index.php5?title=Linker_Mezzanine_card_for_96board 284 * [2] http://learn.linksprite.com/96-board/sliding-rheostat 285 * [3] http://learn.linksprite.com/96-board/photoresistor 286 */ 287 void spi_test(void) 288 { 289 spi_test_with_builtin_cs_control(); 290 spi_test_with_registered_cs_cb(); 291 spi_test_with_manual_cs_control(); 292 } 293