1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 */ 5 6 #include <drivers/pl022_spi.h> 7 #include <drivers/pl061_gpio.h> 8 #include <hikey_peripherals.h> 9 #include <io.h> 10 #include <kernel/tee_time.h> 11 #include <mm/core_memprot.h> 12 #include <stdint.h> 13 #include <trace.h> 14 #include <util.h> 15 16 #define PL022_STAT 0x00C 17 #define PL022_STAT_BSY SHIFT_U32(1, 4) 18 19 static void spi_cs_callback(enum gpio_level value) 20 { 21 static bool inited; 22 static struct pl061_data pd; 23 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC); 24 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 25 26 if (!inited) { 27 pl061_init(&pd); 28 pl061_register(gpio6_base, 6); 29 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 30 pd.chip.ops->set_interrupt(NULL, GPIO6_2, 31 GPIO_INTERRUPT_DISABLE); 32 pd.chip.ops->set_direction(NULL, GPIO6_2, GPIO_DIR_OUT); 33 inited = true; 34 } 35 36 if (io_read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 37 DMSG("pl022 busy - do NOT set CS!"); 38 while (io_read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 39 ; 40 DMSG("pl022 done - set CS!"); 41 42 pd.chip.ops->set_value(NULL, GPIO6_2, value); 43 } 44 45 static void spi_set_cs_mux(uint32_t val) 46 { 47 uint32_t data; 48 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 49 50 if (val == PINMUX_SPI) { 51 DMSG("Configure gpio6 pin2 as SPI"); 52 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 53 } else { 54 DMSG("Configure gpio6 pin2 as GPIO"); 55 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_GPIO); 56 } 57 58 data = io_read32(pmx0_base + PMX0_IOMG106); 59 if (data) 60 DMSG("gpio6 pin2 is SPI"); 61 else 62 DMSG("gpio6 pin2 is GPIO"); 63 } 64 65 static void spi_test_with_manual_cs_control(void) 66 { 67 struct pl022_data pd; 68 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 69 uint8_t tx[3] = {0x01, 0x80, 0x00}; 70 uint8_t rx[3] = {0}; 71 size_t i, j, len = 3; 72 enum spi_result res; 73 74 spi_set_cs_mux(PINMUX_GPIO); 75 76 DMSG("Set CS callback"); 77 pd.cs_control = PL022_CS_CTRL_MANUAL; 78 79 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 80 DMSG("Configure SPI"); 81 pd.base = spi_base; 82 pd.clk_hz = SPI_CLK_HZ; 83 pd.speed_hz = SPI_10_KHZ; 84 pd.mode = SPI_MODE0; 85 pd.data_size_bits = 8; 86 pd.loopback = true; 87 88 pl022_init(&pd); 89 pd.chip.ops->configure(&pd.chip); 90 pd.chip.ops->start(&pd.chip); 91 92 /* 93 * Pulse CS only once for the whole transmission. 94 * This is the scheme used by the pl022 driver. 95 */ 96 spi_cs_callback(GPIO_LEVEL_HIGH); 97 tee_time_busy_wait(2); 98 spi_cs_callback(GPIO_LEVEL_LOW); 99 for (j = 0; j < 10; j++) { 100 DMSG("SPI test loop: %zu", j); 101 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 102 if (res) { 103 EMSG("SPI transceive error %d", res); 104 break; 105 } 106 107 for (i = 0; i < len; i++) 108 DMSG("rx[%zu] = 0x%x", i, rx[i]); 109 110 tee_time_busy_wait(20); 111 } 112 spi_cs_callback(GPIO_LEVEL_HIGH); 113 114 /* Pulse CS once per transfer */ 115 spi_cs_callback(GPIO_LEVEL_HIGH); 116 tee_time_busy_wait(2); 117 for (j = 10; j < 20; j++) { 118 DMSG("SPI test loop: %zu", j); 119 spi_cs_callback(GPIO_LEVEL_LOW); 120 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 121 if (res) { 122 EMSG("SPI transceive error %d", res); 123 break; 124 } 125 126 for (i = 0; i < len; i++) 127 DMSG("rx[%zu] = 0x%x", i, rx[i]); 128 129 tee_time_busy_wait(20); 130 spi_cs_callback(GPIO_LEVEL_HIGH); 131 } 132 133 /* Pulse CS once per word/byte */ 134 spi_set_cs_mux(PINMUX_SPI); 135 tee_time_busy_wait(2); 136 for (j = 20; j < 30; j++) { 137 DMSG("SPI test loop: %zu", j); 138 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 139 if (res) { 140 EMSG("SPI transceive error %d", res); 141 break; 142 } 143 144 for (i = 0; i < len; i++) 145 DMSG("rx[%zu] = 0x%x", i, rx[i]); 146 147 tee_time_busy_wait(20); 148 } 149 150 pd.chip.ops->end(&pd.chip); 151 } 152 153 static void spi_test_with_registered_cs_cb(void) 154 { 155 struct pl022_data pd; 156 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 157 uint8_t tx[3] = {0x01, 0x80, 0x00}; 158 uint8_t rx[3] = {0}; 159 size_t i, j, len = 3; 160 enum spi_result res; 161 162 spi_set_cs_mux(PINMUX_GPIO); 163 164 DMSG("Set CS callback"); 165 pd.cs_data.cs_cb = spi_cs_callback; 166 pd.cs_control = PL022_CS_CTRL_CB; 167 168 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 169 DMSG("Configure SPI"); 170 pd.base = spi_base; 171 pd.clk_hz = SPI_CLK_HZ; 172 pd.speed_hz = SPI_10_KHZ; 173 pd.mode = SPI_MODE0; 174 pd.data_size_bits = 8; 175 pd.loopback = true; 176 177 pl022_init(&pd); 178 pd.chip.ops->configure(&pd.chip); 179 pd.chip.ops->start(&pd.chip); 180 181 for (j = 0; j < 20; j++) { 182 DMSG("SPI test loop: %zu", j); 183 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 184 if (res) { 185 EMSG("SPI transceive error %d", res); 186 break; 187 } 188 189 for (i = 0; i < len; i++) 190 DMSG("rx[%zu] = 0x%x", i, rx[i]); 191 192 tee_time_busy_wait(20); 193 } 194 195 pd.chip.ops->end(&pd.chip); 196 } 197 198 static void spi_test_with_builtin_cs_control(void) 199 { 200 struct pl061_data pd061; 201 struct pl022_data pd022; 202 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC); 203 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 204 uint8_t tx[3] = {0x01, 0x80, 0x00}; 205 uint8_t rx[3] = {0}; 206 size_t i, j, len = 3; 207 enum spi_result res; 208 209 spi_set_cs_mux(PINMUX_GPIO); 210 211 DMSG("gpio6_base: 0x%" PRIxVA "\n", gpio6_base); 212 DMSG("Configure GPIO"); 213 pl061_init(&pd061); 214 pl061_register(gpio6_base, 6); 215 DMSG("Enable software mode control for chip select"); 216 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 217 218 pd022.cs_data.gpio_data.chip = &pd061.chip; 219 pd022.cs_data.gpio_data.pin_num = GPIO6_2; 220 pd022.cs_control = PL022_CS_CTRL_AUTO_GPIO; 221 222 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 223 DMSG("Configure SPI"); 224 pd022.base = spi_base; 225 pd022.clk_hz = SPI_CLK_HZ; 226 pd022.speed_hz = SPI_10_KHZ; 227 pd022.mode = SPI_MODE0; 228 pd022.data_size_bits = 8; 229 pd022.loopback = true; 230 231 pl022_init(&pd022); 232 pd022.chip.ops->configure(&pd022.chip); 233 pd022.chip.ops->start(&pd022.chip); 234 235 for (j = 0; j < 20; j++) { 236 DMSG("SPI test loop: %zu", j); 237 res = pd022.chip.ops->txrx8(&pd022.chip, tx, rx, len); 238 if (res) { 239 EMSG("SPI transceive error %d", res); 240 break; 241 } 242 243 for (i = 0; i < len; i++) 244 DMSG("rx[%zu] = 0x%x", i, rx[i]); 245 246 tee_time_busy_wait(20); 247 } 248 249 pd022.chip.ops->end(&pd022.chip); 250 } 251 252 /* 253 * spi_init() MUST be run before calling this function! 254 * 255 * spi_test runs some loopback tests, so the SPI module will just receive 256 * what is transmitted, i.e. 0x01, 0x80, 0x00. 257 * 258 * In non-loopback mode, the transmitted value will elicit a readback of 259 * the measured value from the ADC chip on the Linksprite 96Boards 260 * Mezzanine card [1], which can be connected to either a sliding 261 * rheostat [2] or photoresistor [3]. 262 * 263 * [1] http://linksprite.com/wiki/index.php5?title=Linker_Mezzanine_card_for_96board 264 * [2] http://learn.linksprite.com/96-board/sliding-rheostat 265 * [3] http://learn.linksprite.com/96-board/photoresistor 266 */ 267 void spi_test(void) 268 { 269 spi_test_with_builtin_cs_control(); 270 spi_test_with_registered_cs_cb(); 271 spi_test_with_manual_cs_control(); 272 } 273