1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 */ 5 6 #include <drivers/pl022_spi.h> 7 #include <drivers/pl061_gpio.h> 8 #include <hikey_peripherals.h> 9 #include <io.h> 10 #include <kernel/tee_time.h> 11 #include <mm/core_memprot.h> 12 #include <stdint.h> 13 #include <trace.h> 14 #include <util.h> 15 16 #define PL022_STAT 0x00C 17 #define PL022_STAT_BSY SHIFT_U32(1, 4) 18 19 static void spi_cs_callback(enum gpio_level value) 20 { 21 static bool inited; 22 static struct pl061_data pd; 23 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC); 24 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 25 26 if (!inited) { 27 pl061_init(&pd); 28 pl061_register(gpio6_base, 6); 29 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 30 pd.chip.ops->set_interrupt(GPIO6_2, GPIO_INTERRUPT_DISABLE); 31 pd.chip.ops->set_direction(GPIO6_2, GPIO_DIR_OUT); 32 inited = true; 33 } 34 35 if (io_read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 36 DMSG("pl022 busy - do NOT set CS!"); 37 while (io_read8(spi_base + PL022_STAT) & PL022_STAT_BSY) 38 ; 39 DMSG("pl022 done - set CS!"); 40 41 pd.chip.ops->set_value(GPIO6_2, value); 42 } 43 44 static void spi_set_cs_mux(uint32_t val) 45 { 46 uint32_t data; 47 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 48 49 if (val == PINMUX_SPI) { 50 DMSG("Configure gpio6 pin2 as SPI"); 51 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 52 } else { 53 DMSG("Configure gpio6 pin2 as GPIO"); 54 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_GPIO); 55 } 56 57 data = io_read32(pmx0_base + PMX0_IOMG106); 58 if (data) 59 DMSG("gpio6 pin2 is SPI"); 60 else 61 DMSG("gpio6 pin2 is GPIO"); 62 } 63 64 static void spi_test_with_manual_cs_control(void) 65 { 66 struct pl022_data pd; 67 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 68 uint8_t tx[3] = {0x01, 0x80, 0x00}; 69 uint8_t rx[3] = {0}; 70 size_t i, j, len = 3; 71 enum spi_result res; 72 73 spi_set_cs_mux(PINMUX_GPIO); 74 75 DMSG("Set CS callback"); 76 pd.cs_control = PL022_CS_CTRL_MANUAL; 77 78 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 79 DMSG("Configure SPI"); 80 pd.base = spi_base; 81 pd.clk_hz = SPI_CLK_HZ; 82 pd.speed_hz = SPI_10_KHZ; 83 pd.mode = SPI_MODE0; 84 pd.data_size_bits = 8; 85 pd.loopback = true; 86 87 pl022_init(&pd); 88 pd.chip.ops->configure(&pd.chip); 89 pd.chip.ops->start(&pd.chip); 90 91 /* 92 * Pulse CS only once for the whole transmission. 93 * This is the scheme used by the pl022 driver. 94 */ 95 spi_cs_callback(GPIO_LEVEL_HIGH); 96 tee_time_busy_wait(2); 97 spi_cs_callback(GPIO_LEVEL_LOW); 98 for (j = 0; j < 10; j++) { 99 DMSG("SPI test loop: %zu", j); 100 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 101 if (res) { 102 EMSG("SPI transceive error %d", res); 103 break; 104 } 105 106 for (i = 0; i < len; i++) 107 DMSG("rx[%zu] = 0x%x", i, rx[i]); 108 109 tee_time_busy_wait(20); 110 } 111 spi_cs_callback(GPIO_LEVEL_HIGH); 112 113 /* Pulse CS once per transfer */ 114 spi_cs_callback(GPIO_LEVEL_HIGH); 115 tee_time_busy_wait(2); 116 for (j = 10; j < 20; j++) { 117 DMSG("SPI test loop: %zu", j); 118 spi_cs_callback(GPIO_LEVEL_LOW); 119 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 120 if (res) { 121 EMSG("SPI transceive error %d", res); 122 break; 123 } 124 125 for (i = 0; i < len; i++) 126 DMSG("rx[%zu] = 0x%x", i, rx[i]); 127 128 tee_time_busy_wait(20); 129 spi_cs_callback(GPIO_LEVEL_HIGH); 130 } 131 132 /* Pulse CS once per word/byte */ 133 spi_set_cs_mux(PINMUX_SPI); 134 tee_time_busy_wait(2); 135 for (j = 20; j < 30; j++) { 136 DMSG("SPI test loop: %zu", j); 137 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 138 if (res) { 139 EMSG("SPI transceive error %d", res); 140 break; 141 } 142 143 for (i = 0; i < len; i++) 144 DMSG("rx[%zu] = 0x%x", i, rx[i]); 145 146 tee_time_busy_wait(20); 147 } 148 149 pd.chip.ops->end(&pd.chip); 150 } 151 152 static void spi_test_with_registered_cs_cb(void) 153 { 154 struct pl022_data pd; 155 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 156 uint8_t tx[3] = {0x01, 0x80, 0x00}; 157 uint8_t rx[3] = {0}; 158 size_t i, j, len = 3; 159 enum spi_result res; 160 161 spi_set_cs_mux(PINMUX_GPIO); 162 163 DMSG("Set CS callback"); 164 pd.cs_data.cs_cb = spi_cs_callback; 165 pd.cs_control = PL022_CS_CTRL_CB; 166 167 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 168 DMSG("Configure SPI"); 169 pd.base = spi_base; 170 pd.clk_hz = SPI_CLK_HZ; 171 pd.speed_hz = SPI_10_KHZ; 172 pd.mode = SPI_MODE0; 173 pd.data_size_bits = 8; 174 pd.loopback = true; 175 176 pl022_init(&pd); 177 pd.chip.ops->configure(&pd.chip); 178 pd.chip.ops->start(&pd.chip); 179 180 for (j = 0; j < 20; j++) { 181 DMSG("SPI test loop: %zu", j); 182 res = pd.chip.ops->txrx8(&pd.chip, tx, rx, len); 183 if (res) { 184 EMSG("SPI transceive error %d", res); 185 break; 186 } 187 188 for (i = 0; i < len; i++) 189 DMSG("rx[%zu] = 0x%x", i, rx[i]); 190 191 tee_time_busy_wait(20); 192 } 193 194 pd.chip.ops->end(&pd.chip); 195 } 196 197 static void spi_test_with_builtin_cs_control(void) 198 { 199 struct pl061_data pd061; 200 struct pl022_data pd022; 201 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC); 202 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC); 203 uint8_t tx[3] = {0x01, 0x80, 0x00}; 204 uint8_t rx[3] = {0}; 205 size_t i, j, len = 3; 206 enum spi_result res; 207 208 spi_set_cs_mux(PINMUX_GPIO); 209 210 DMSG("gpio6_base: 0x%" PRIxVA "\n", gpio6_base); 211 DMSG("Configure GPIO"); 212 pl061_init(&pd061); 213 pl061_register(gpio6_base, 6); 214 DMSG("Enable software mode control for chip select"); 215 pl061_set_mode_control(GPIO6_2, PL061_MC_SW); 216 217 pd022.cs_data.gpio_data.chip = &pd061.chip; 218 pd022.cs_data.gpio_data.pin_num = GPIO6_2; 219 pd022.cs_control = PL022_CS_CTRL_AUTO_GPIO; 220 221 DMSG("spi_base: 0x%" PRIxVA "\n", spi_base); 222 DMSG("Configure SPI"); 223 pd022.base = spi_base; 224 pd022.clk_hz = SPI_CLK_HZ; 225 pd022.speed_hz = SPI_10_KHZ; 226 pd022.mode = SPI_MODE0; 227 pd022.data_size_bits = 8; 228 pd022.loopback = true; 229 230 pl022_init(&pd022); 231 pd022.chip.ops->configure(&pd022.chip); 232 pd022.chip.ops->start(&pd022.chip); 233 234 for (j = 0; j < 20; j++) { 235 DMSG("SPI test loop: %zu", j); 236 res = pd022.chip.ops->txrx8(&pd022.chip, tx, rx, len); 237 if (res) { 238 EMSG("SPI transceive error %d", res); 239 break; 240 } 241 242 for (i = 0; i < len; i++) 243 DMSG("rx[%zu] = 0x%x", i, rx[i]); 244 245 tee_time_busy_wait(20); 246 } 247 248 pd022.chip.ops->end(&pd022.chip); 249 } 250 251 /* 252 * spi_init() MUST be run before calling this function! 253 * 254 * spi_test runs some loopback tests, so the SPI module will just receive 255 * what is transmitted, i.e. 0x01, 0x80, 0x00. 256 * 257 * In non-loopback mode, the transmitted value will elicit a readback of 258 * the measured value from the ADC chip on the Linksprite 96Boards 259 * Mezzanine card [1], which can be connected to either a sliding 260 * rheostat [2] or photoresistor [3]. 261 * 262 * [1] http://linksprite.com/wiki/index.php5?title=Linker_Mezzanine_card_for_96board 263 * [2] http://learn.linksprite.com/96-board/sliding-rheostat 264 * [3] http://learn.linksprite.com/96-board/photoresistor 265 */ 266 void spi_test(void) 267 { 268 spi_test_with_builtin_cs_control(); 269 spi_test_with_registered_cs_cb(); 270 spi_test_with_manual_cs_control(); 271 } 272