1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <console.h> 29 #include <drivers/pl011.h> 30 #ifdef CFG_SPI 31 #include <drivers/pl022_spi.h> 32 #include <drivers/pl061_gpio.h> 33 #endif 34 #include <hikey_peripherals.h> 35 #include <initcall.h> 36 #include <io.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <mm/tee_pager.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <stdint.h> 44 #include <tee/entry_std.h> 45 #include <tee/entry_fast.h> 46 47 static void main_fiq(void); 48 49 static const struct thread_handlers handlers = { 50 .std_smc = tee_entry_std, 51 .fast_smc = tee_entry_fast, 52 .fiq = main_fiq, 53 .cpu_on = cpu_on_handler, 54 .cpu_off = pm_do_nothing, 55 .cpu_suspend = pm_do_nothing, 56 .cpu_resume = pm_do_nothing, 57 .system_off = pm_do_nothing, 58 .system_reset = pm_do_nothing, 59 }; 60 61 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 62 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 63 #ifdef CFG_SPI 64 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 65 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 66 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 67 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 68 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 69 #endif 70 71 const struct thread_handlers *generic_boot_get_handlers(void) 72 { 73 return &handlers; 74 } 75 76 static void main_fiq(void) 77 { 78 panic(); 79 } 80 81 static vaddr_t console_base(void) 82 { 83 static void *va; 84 85 if (cpu_mmu_enabled()) { 86 if (!va) 87 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_NSEC); 88 return (vaddr_t)va; 89 } 90 return CONSOLE_UART_BASE; 91 } 92 93 void console_init(void) 94 { 95 pl011_init(console_base(), CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 96 } 97 98 void console_putc(int ch) 99 { 100 vaddr_t base = console_base(); 101 102 if (ch == '\n') 103 pl011_putc('\r', base); 104 pl011_putc(ch, base); 105 } 106 107 void console_flush(void) 108 { 109 pl011_flush(console_base()); 110 } 111 112 vaddr_t nsec_periph_base(paddr_t pa) 113 { 114 if (cpu_mmu_enabled()) 115 return (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_NSEC); 116 return (vaddr_t)pa; 117 } 118 119 #ifdef CFG_SPI 120 void spi_init(void) 121 { 122 uint32_t shifted_val, read_val; 123 vaddr_t peri_base = nsec_periph_base(PERI_BASE); 124 vaddr_t pmx0_base = nsec_periph_base(PMX0_BASE); 125 vaddr_t pmx1_base = nsec_periph_base(PMX1_BASE); 126 127 DMSG("take SPI0 out of reset\n"); 128 shifted_val = PERI_RST3_SSP; 129 /* 130 * no need to read PERI_SC_PERIPH_RSTDIS3 first 131 * as all the bits are processed and cleared after writing 132 */ 133 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 134 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 135 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 136 137 /* 138 * wait until the requested device is out of reset 139 * and ready to be used 140 */ 141 do { 142 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 143 } while (read_val & shifted_val); 144 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 145 146 DMSG("enable SPI clock\n"); 147 /* 148 * no need to read PERI_SC_PERIPH_CLKEN3 first 149 * as all the bits are processed and cleared after writing 150 */ 151 shifted_val = PERI_CLK3_SSP; 152 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 153 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 154 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 155 156 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 157 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 158 159 /* 160 * gpio6_2 can be configured as pinmux_spi, in which case the hw 161 * will control the chip select pin and we don't have to manually 162 * do it, but hw will pulse it between each data word transfer, 163 * which will not work with all clients. There seems to be no 164 * option to configure it to stay enabled for the total duration 165 * of the transfer. 166 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 167 */ 168 DMSG("configure gpio6_{0,1,3} as SPI\n"); 169 DMSG("configure gpio6_2 as GPIO\n"); 170 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 171 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 172 write32(PINMUX_GPIO, pmx0_base + PMX0_IOMG106); 173 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 174 175 DMSG("configure gpio6_{0:3} as nopull\n"); 176 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 177 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 178 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 179 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 180 181 #ifdef CFG_SPI_TEST 182 spi_test(); 183 #endif 184 } 185 #endif 186 187 static TEE_Result peripherals_init(void) 188 { 189 vaddr_t pmussi_base = nsec_periph_base(PMUSSI_BASE); 190 191 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 192 /* 193 * Mezzanine cards usually use this to source level shifters for 194 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 195 * peripherals will not work either (during bootloader stage) 196 * until linux is booted. 197 */ 198 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 199 PMUSSI_LDO21_REG_VL_MASK); 200 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 201 202 #ifdef CFG_SPI 203 spi_init(); 204 #endif 205 return TEE_SUCCESS; 206 } 207 208 driver_init(peripherals_init); 209