1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <console.h> 29 #include <drivers/pl011.h> 30 #ifdef CFG_SPI 31 #include <drivers/pl022_spi.h> 32 #include <drivers/pl061_gpio.h> 33 #endif 34 #include <hikey_peripherals.h> 35 #include <initcall.h> 36 #include <io.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <mm/tee_pager.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <stdint.h> 44 #include <tee/entry_std.h> 45 #include <tee/entry_fast.h> 46 47 static void main_fiq(void); 48 49 static const struct thread_handlers handlers = { 50 .std_smc = tee_entry_std, 51 .fast_smc = tee_entry_fast, 52 .nintr = main_fiq, 53 .cpu_on = cpu_on_handler, 54 .cpu_off = pm_do_nothing, 55 .cpu_suspend = pm_do_nothing, 56 .cpu_resume = pm_do_nothing, 57 .system_off = pm_do_nothing, 58 .system_reset = pm_do_nothing, 59 }; 60 61 static struct pl011_data console_data; 62 63 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 64 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 65 #ifdef CFG_SPI 66 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 67 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 68 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 69 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 70 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 71 #endif 72 73 const struct thread_handlers *generic_boot_get_handlers(void) 74 { 75 return &handlers; 76 } 77 78 static void main_fiq(void) 79 { 80 panic(); 81 } 82 83 void console_init(void) 84 { 85 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 86 CONSOLE_BAUDRATE); 87 register_serial_console(&console_data.chip); 88 } 89 90 vaddr_t nsec_periph_base(paddr_t pa) 91 { 92 if (cpu_mmu_enabled()) 93 return (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_NSEC); 94 return (vaddr_t)pa; 95 } 96 97 #ifdef CFG_SPI 98 void spi_init(void) 99 { 100 uint32_t shifted_val, read_val; 101 vaddr_t peri_base = nsec_periph_base(PERI_BASE); 102 vaddr_t pmx0_base = nsec_periph_base(PMX0_BASE); 103 vaddr_t pmx1_base = nsec_periph_base(PMX1_BASE); 104 105 DMSG("take SPI0 out of reset\n"); 106 shifted_val = PERI_RST3_SSP; 107 /* 108 * no need to read PERI_SC_PERIPH_RSTDIS3 first 109 * as all the bits are processed and cleared after writing 110 */ 111 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 112 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 113 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 114 115 /* 116 * wait until the requested device is out of reset 117 * and ready to be used 118 */ 119 do { 120 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 121 } while (read_val & shifted_val); 122 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 123 124 DMSG("enable SPI clock\n"); 125 /* 126 * no need to read PERI_SC_PERIPH_CLKEN3 first 127 * as all the bits are processed and cleared after writing 128 */ 129 shifted_val = PERI_CLK3_SSP; 130 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 131 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 132 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 133 134 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 135 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 136 137 /* 138 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 139 * will control the chip select pin so we don't have to manually do it. 140 * The only concern is that the IP will pulse it between each packet, 141 * which might not work with certain clients. There seems to be no 142 * option to configure it to stay enabled for the total duration of the 143 * transfer. 144 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 145 */ 146 DMSG("configure gpio6 pins 0-3 as SPI\n"); 147 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 148 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 149 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 150 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 151 152 DMSG("configure gpio6 pins 0-3 as nopull\n"); 153 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 154 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 155 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 156 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 157 158 #ifdef CFG_SPI_TEST 159 spi_test(); 160 #endif 161 } 162 #endif 163 164 static TEE_Result peripherals_init(void) 165 { 166 vaddr_t pmussi_base = nsec_periph_base(PMUSSI_BASE); 167 168 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 169 /* 170 * Mezzanine cards usually use this to source level shifters for 171 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 172 * peripherals will not work either (during bootloader stage) 173 * until linux is booted. 174 */ 175 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 176 PMUSSI_LDO21_REG_VL_MASK); 177 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 178 179 #ifdef CFG_SPI 180 spi_init(); 181 #endif 182 return TEE_SUCCESS; 183 } 184 185 driver_init(peripherals_init); 186