1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <console.h> 29 #include <drivers/pl011.h> 30 #ifdef CFG_SPI 31 #include <drivers/pl022_spi.h> 32 #include <drivers/pl061_gpio.h> 33 #endif 34 #if defined(PLATFORM_FLAVOR_hikey) 35 #include <hikey_peripherals.h> 36 #endif 37 #include <initcall.h> 38 #include <io.h> 39 #include <kernel/generic_boot.h> 40 #include <kernel/panic.h> 41 #include <kernel/pm_stubs.h> 42 #include <mm/tee_pager.h> 43 #include <mm/core_memprot.h> 44 #include <platform_config.h> 45 #include <stdint.h> 46 #include <tee/entry_std.h> 47 #include <tee/entry_fast.h> 48 49 static void main_fiq(void); 50 51 static const struct thread_handlers handlers = { 52 .std_smc = tee_entry_std, 53 .fast_smc = tee_entry_fast, 54 .nintr = main_fiq, 55 .cpu_on = cpu_on_handler, 56 .cpu_off = pm_do_nothing, 57 .cpu_suspend = pm_do_nothing, 58 .cpu_resume = pm_do_nothing, 59 .system_off = pm_do_nothing, 60 .system_reset = pm_do_nothing, 61 }; 62 63 static struct pl011_data console_data; 64 65 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 66 #if defined(PLATFORM_FLAVOR_hikey) 67 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 68 #endif 69 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 70 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 71 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 72 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 73 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 74 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 75 #endif 76 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE_NSEC); 77 78 const struct thread_handlers *generic_boot_get_handlers(void) 79 { 80 return &handlers; 81 } 82 83 static void main_fiq(void) 84 { 85 panic(); 86 } 87 88 void console_init(void) 89 { 90 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 91 CONSOLE_BAUDRATE); 92 register_serial_console(&console_data.chip); 93 } 94 95 #if defined(PLATFORM_FLAVOR_hikey) 96 #ifdef CFG_SPI 97 void spi_init(void) 98 { 99 uint32_t shifted_val, read_val; 100 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 101 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 102 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 103 104 DMSG("take SPI0 out of reset\n"); 105 shifted_val = PERI_RST3_SSP; 106 /* 107 * no need to read PERI_SC_PERIPH_RSTDIS3 first 108 * as all the bits are processed and cleared after writing 109 */ 110 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 111 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 112 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 113 114 /* 115 * wait until the requested device is out of reset 116 * and ready to be used 117 */ 118 do { 119 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 120 } while (read_val & shifted_val); 121 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 122 123 DMSG("enable SPI clock\n"); 124 /* 125 * no need to read PERI_SC_PERIPH_CLKEN3 first 126 * as all the bits are processed and cleared after writing 127 */ 128 shifted_val = PERI_CLK3_SSP; 129 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 130 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 131 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 132 133 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 134 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 135 136 /* 137 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 138 * will control the chip select pin so we don't have to manually do it. 139 * The only concern is that the IP will pulse it between each packet, 140 * which might not work with certain clients. There seems to be no 141 * option to configure it to stay enabled for the total duration of the 142 * transfer. 143 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 144 */ 145 DMSG("configure gpio6 pins 0-3 as SPI\n"); 146 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 147 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 148 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 149 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 150 151 DMSG("configure gpio6 pins 0-3 as nopull\n"); 152 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 153 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 154 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 155 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 156 157 #ifdef CFG_SPI_TEST 158 spi_test(); 159 #endif 160 } 161 #endif 162 163 static TEE_Result peripherals_init(void) 164 { 165 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 166 167 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 168 /* 169 * Mezzanine cards usually use this to source level shifters for 170 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 171 * peripherals will not work either (during bootloader stage) 172 * until linux is booted. 173 */ 174 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 175 PMUSSI_LDO21_REG_VL_MASK); 176 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 177 178 #ifdef CFG_SPI 179 spi_init(); 180 #endif 181 return TEE_SUCCESS; 182 } 183 184 driver_init(peripherals_init); 185 #endif /* PLATFORM_FLAVOR_hikey */ 186