1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static void main_fiq(void); 28 29 static const struct thread_handlers handlers = { 30 .std_smc = tee_entry_std, 31 .fast_smc = tee_entry_fast, 32 .nintr = main_fiq, 33 .cpu_on = cpu_on_handler, 34 .cpu_off = pm_do_nothing, 35 .cpu_suspend = pm_do_nothing, 36 .cpu_resume = pm_do_nothing, 37 .system_off = pm_do_nothing, 38 .system_reset = pm_do_nothing, 39 }; 40 41 static struct pl011_data console_data; 42 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 44 #if defined(PLATFORM_FLAVOR_hikey) 45 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 46 #endif 47 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 48 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 53 #endif 54 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC); 55 #ifdef DRAM1_SIZE_NSEC 56 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC); 57 #endif 58 #ifdef DRAM2_SIZE_NSEC 59 register_dynamic_shm(DRAM2_BASE, DRAM2_SIZE_NSEC); 60 #endif 61 62 const struct thread_handlers *generic_boot_get_handlers(void) 63 { 64 return &handlers; 65 } 66 67 static void main_fiq(void) 68 { 69 panic(); 70 } 71 72 void console_init(void) 73 { 74 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 75 CONSOLE_BAUDRATE); 76 register_serial_console(&console_data.chip); 77 } 78 79 #if defined(PLATFORM_FLAVOR_hikey) 80 #ifdef CFG_SPI 81 void spi_init(void) 82 { 83 uint32_t shifted_val, read_val; 84 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 85 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 86 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 87 88 DMSG("take SPI0 out of reset\n"); 89 shifted_val = PERI_RST3_SSP; 90 /* 91 * no need to read PERI_SC_PERIPH_RSTDIS3 first 92 * as all the bits are processed and cleared after writing 93 */ 94 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); 95 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 96 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 97 98 /* 99 * wait until the requested device is out of reset 100 * and ready to be used 101 */ 102 do { 103 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 104 } while (read_val & shifted_val); 105 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 106 107 DMSG("enable SPI clock\n"); 108 /* 109 * no need to read PERI_SC_PERIPH_CLKEN3 first 110 * as all the bits are processed and cleared after writing 111 */ 112 shifted_val = PERI_CLK3_SSP; 113 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); 114 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 115 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 116 117 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 118 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 119 120 /* 121 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 122 * will control the chip select pin so we don't have to manually do it. 123 * The only concern is that the IP will pulse it between each packet, 124 * which might not work with certain clients. There seems to be no 125 * option to configure it to stay enabled for the total duration of the 126 * transfer. 127 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 128 */ 129 DMSG("configure gpio6 pins 0-3 as SPI\n"); 130 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); 131 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); 132 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 133 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); 134 135 DMSG("configure gpio6 pins 0-3 as nopull\n"); 136 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); 137 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); 138 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); 139 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); 140 141 #ifdef CFG_SPI_TEST 142 spi_test(); 143 #endif 144 } 145 #endif 146 147 static TEE_Result peripherals_init(void) 148 { 149 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 150 151 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 152 /* 153 * Mezzanine cards usually use this to source level shifters for 154 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 155 * peripherals will not work either (during bootloader stage) 156 * until linux is booted. 157 */ 158 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 159 PMUSSI_LDO21_REG_VL_MASK); 160 io_write8(pmussi_base + PMUSSI_ENA_LDO17_22, PMUSSI_ENA_LDO21); 161 162 #ifdef CFG_SPI 163 spi_init(); 164 #endif 165 return TEE_SUCCESS; 166 } 167 168 driver_init(peripherals_init); 169 #endif /* PLATFORM_FLAVOR_hikey */ 170