1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static void main_fiq(void); 28 29 static const struct thread_handlers handlers = { 30 .std_smc = tee_entry_std, 31 .fast_smc = tee_entry_fast, 32 .nintr = main_fiq, 33 .cpu_on = cpu_on_handler, 34 .cpu_off = pm_do_nothing, 35 .cpu_suspend = pm_do_nothing, 36 .cpu_resume = pm_do_nothing, 37 .system_off = pm_do_nothing, 38 .system_reset = pm_do_nothing, 39 }; 40 41 static struct pl011_data console_data; 42 43 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 44 #if defined(PLATFORM_FLAVOR_hikey) 45 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 46 #endif 47 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 48 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 49 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 50 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 51 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 52 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 53 #endif 54 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC); 55 #ifdef DRAM1_SIZE_NSEC 56 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC); 57 #endif 58 59 const struct thread_handlers *generic_boot_get_handlers(void) 60 { 61 return &handlers; 62 } 63 64 static void main_fiq(void) 65 { 66 panic(); 67 } 68 69 void console_init(void) 70 { 71 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 72 CONSOLE_BAUDRATE); 73 register_serial_console(&console_data.chip); 74 } 75 76 #if defined(PLATFORM_FLAVOR_hikey) 77 #ifdef CFG_SPI 78 void spi_init(void) 79 { 80 uint32_t shifted_val, read_val; 81 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 82 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 83 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 84 85 DMSG("take SPI0 out of reset\n"); 86 shifted_val = PERI_RST3_SSP; 87 /* 88 * no need to read PERI_SC_PERIPH_RSTDIS3 first 89 * as all the bits are processed and cleared after writing 90 */ 91 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 92 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 93 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 94 95 /* 96 * wait until the requested device is out of reset 97 * and ready to be used 98 */ 99 do { 100 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 101 } while (read_val & shifted_val); 102 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 103 104 DMSG("enable SPI clock\n"); 105 /* 106 * no need to read PERI_SC_PERIPH_CLKEN3 first 107 * as all the bits are processed and cleared after writing 108 */ 109 shifted_val = PERI_CLK3_SSP; 110 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 111 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 112 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 113 114 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 115 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 116 117 /* 118 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 119 * will control the chip select pin so we don't have to manually do it. 120 * The only concern is that the IP will pulse it between each packet, 121 * which might not work with certain clients. There seems to be no 122 * option to configure it to stay enabled for the total duration of the 123 * transfer. 124 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 125 */ 126 DMSG("configure gpio6 pins 0-3 as SPI\n"); 127 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 128 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 129 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 130 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 131 132 DMSG("configure gpio6 pins 0-3 as nopull\n"); 133 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 134 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 135 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 136 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 137 138 #ifdef CFG_SPI_TEST 139 spi_test(); 140 #endif 141 } 142 #endif 143 144 static TEE_Result peripherals_init(void) 145 { 146 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 147 148 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 149 /* 150 * Mezzanine cards usually use this to source level shifters for 151 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 152 * peripherals will not work either (during bootloader stage) 153 * until linux is booted. 154 */ 155 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 156 PMUSSI_LDO21_REG_VL_MASK); 157 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 158 159 #ifdef CFG_SPI 160 spi_init(); 161 #endif 162 return TEE_SUCCESS; 163 } 164 165 driver_init(peripherals_init); 166 #endif /* PLATFORM_FLAVOR_hikey */ 167