1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static const struct thread_handlers handlers = { 28 .cpu_on = cpu_on_handler, 29 .cpu_off = pm_do_nothing, 30 .cpu_suspend = pm_do_nothing, 31 .cpu_resume = pm_do_nothing, 32 .system_off = pm_do_nothing, 33 .system_reset = pm_do_nothing, 34 }; 35 36 static struct pl011_data console_data __nex_bss; 37 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 39 #if defined(PLATFORM_FLAVOR_hikey) 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 41 #endif 42 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 48 #endif 49 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC); 50 #ifdef DRAM1_SIZE_NSEC 51 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC); 52 #endif 53 #ifdef DRAM2_SIZE_NSEC 54 register_dynamic_shm(DRAM2_BASE, DRAM2_SIZE_NSEC); 55 #endif 56 57 const struct thread_handlers *generic_boot_get_handlers(void) 58 { 59 return &handlers; 60 } 61 62 void console_init(void) 63 { 64 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 65 CONSOLE_BAUDRATE); 66 register_serial_console(&console_data.chip); 67 } 68 69 #if defined(PLATFORM_FLAVOR_hikey) 70 #ifdef CFG_SPI 71 void spi_init(void) 72 { 73 uint32_t shifted_val, read_val; 74 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 75 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 76 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 77 78 DMSG("take SPI0 out of reset\n"); 79 shifted_val = PERI_RST3_SSP; 80 /* 81 * no need to read PERI_SC_PERIPH_RSTDIS3 first 82 * as all the bits are processed and cleared after writing 83 */ 84 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); 85 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 86 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 87 88 /* 89 * wait until the requested device is out of reset 90 * and ready to be used 91 */ 92 do { 93 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 94 } while (read_val & shifted_val); 95 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 96 97 DMSG("enable SPI clock\n"); 98 /* 99 * no need to read PERI_SC_PERIPH_CLKEN3 first 100 * as all the bits are processed and cleared after writing 101 */ 102 shifted_val = PERI_CLK3_SSP; 103 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); 104 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 105 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 106 107 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 108 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 109 110 /* 111 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 112 * will control the chip select pin so we don't have to manually do it. 113 * The only concern is that the IP will pulse it between each packet, 114 * which might not work with certain clients. There seems to be no 115 * option to configure it to stay enabled for the total duration of the 116 * transfer. 117 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 118 */ 119 DMSG("configure gpio6 pins 0-3 as SPI\n"); 120 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); 121 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); 122 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 123 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); 124 125 DMSG("configure gpio6 pins 0-3 as nopull\n"); 126 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); 127 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); 128 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); 129 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); 130 131 #ifdef CFG_SPI_TEST 132 spi_test(); 133 #endif 134 } 135 #endif 136 137 static TEE_Result peripherals_init(void) 138 { 139 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 140 141 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 142 /* 143 * Mezzanine cards usually use this to source level shifters for 144 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 145 * peripherals will not work either (during bootloader stage) 146 * until linux is booted. 147 */ 148 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 149 PMUSSI_LDO21_REG_VL_MASK); 150 io_write8(pmussi_base + PMUSSI_ENA_LDO17_22, PMUSSI_ENA_LDO21); 151 152 #ifdef CFG_SPI 153 spi_init(); 154 #endif 155 return TEE_SUCCESS; 156 } 157 158 driver_init(peripherals_init); 159 #endif /* PLATFORM_FLAVOR_hikey */ 160