1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/panic.h> 18 #include <mm/tee_pager.h> 19 #include <mm/core_memprot.h> 20 #include <platform_config.h> 21 #include <stdint.h> 22 23 static struct pl011_data console_data __nex_bss; 24 25 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 26 #if defined(PLATFORM_FLAVOR_hikey) 27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 28 #endif 29 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 35 #endif 36 register_ddr(DRAM0_BASE, DRAM0_SIZE_NSEC); 37 #ifdef DRAM1_SIZE_NSEC 38 register_ddr(DRAM1_BASE, DRAM1_SIZE_NSEC); 39 #endif 40 #ifdef DRAM2_SIZE_NSEC 41 register_ddr(DRAM2_BASE, DRAM2_SIZE_NSEC); 42 #endif 43 44 void plat_console_init(void) 45 { 46 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 47 CONSOLE_BAUDRATE); 48 register_serial_console(&console_data.chip); 49 } 50 51 #if defined(PLATFORM_FLAVOR_hikey) 52 #ifdef CFG_SPI 53 void spi_init(void) 54 { 55 uint32_t shifted_val, read_val; 56 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC, 57 PERI_BASE_REG_SIZE); 58 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, 59 PMX0_REG_SIZE); 60 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC, 61 PMX1_REG_SIZE); 62 63 DMSG("take SPI0 out of reset"); 64 shifted_val = PERI_RST3_SSP; 65 /* 66 * no need to read PERI_SC_PERIPH_RSTDIS3 first 67 * as all the bits are processed and cleared after writing 68 */ 69 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); 70 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x", 71 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 72 73 /* 74 * wait until the requested device is out of reset 75 * and ready to be used 76 */ 77 do { 78 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 79 } while (read_val & shifted_val); 80 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x", read_val); 81 82 DMSG("enable SPI clock"); 83 /* 84 * no need to read PERI_SC_PERIPH_CLKEN3 first 85 * as all the bits are processed and cleared after writing 86 */ 87 shifted_val = PERI_CLK3_SSP; 88 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); 89 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x", 90 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 91 92 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x", 93 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 94 95 /* 96 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 97 * will control the chip select pin so we don't have to manually do it. 98 * The only concern is that the IP will pulse it between each packet, 99 * which might not work with certain clients. There seems to be no 100 * option to configure it to stay enabled for the total duration of the 101 * transfer. 102 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 103 */ 104 DMSG("configure gpio6 pins 0-3 as SPI"); 105 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); 106 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); 107 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 108 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); 109 110 DMSG("configure gpio6 pins 0-3 as nopull"); 111 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); 112 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); 113 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); 114 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); 115 116 #ifdef CFG_SPI_TEST 117 spi_test(); 118 #endif 119 } 120 #endif 121 122 static TEE_Result peripherals_init(void) 123 { 124 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC, 125 PMUSSI_REG_SIZE); 126 127 DMSG("enable LD021_1V8 source (pin 35) on LS connector"); 128 /* 129 * Mezzanine cards usually use this to source level shifters for 130 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 131 * peripherals will not work either (during bootloader stage) 132 * until linux is booted. 133 */ 134 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 135 PMUSSI_LDO21_REG_VL_MASK); 136 io_write8(pmussi_base + PMUSSI_ENA_LDO17_22, PMUSSI_ENA_LDO21); 137 138 #ifdef CFG_SPI 139 spi_init(); 140 #endif 141 return TEE_SUCCESS; 142 } 143 144 driver_init(peripherals_init); 145 #endif /* PLATFORM_FLAVOR_hikey */ 146