1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2019 Broadcom. 4 */ 5 6 #include <console.h> 7 #include <drivers/gic.h> 8 #include <drivers/serial8250_uart.h> 9 #include <kernel/generic_boot.h> 10 #include <kernel/panic.h> 11 #include <kernel/pm_stubs.h> 12 #include <mm/core_memprot.h> 13 #include <mm/tee_pager.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <tee/entry_fast.h> 17 #include <tee/entry_std.h> 18 19 static void secure_intr_handler(void); 20 21 static const struct thread_handlers handlers = { 22 .std_smc = tee_entry_std, 23 .fast_smc = tee_entry_fast, 24 .nintr = secure_intr_handler, 25 .cpu_on = cpu_on_handler, 26 .cpu_off = pm_do_nothing, 27 .cpu_suspend = pm_do_nothing, 28 .cpu_resume = pm_do_nothing, 29 .system_off = pm_do_nothing, 30 .system_reset = pm_do_nothing, 31 }; 32 33 static struct gic_data gic_data; 34 struct serial8250_uart_data console_data; 35 36 #ifdef BCM_DEVICE0_BASE 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE); 38 #endif 39 #ifdef BCM_DEVICE1_BASE 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE); 41 #endif 42 #ifdef BCM_DEVICE2_BASE 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE); 44 #endif 45 #ifdef BCM_DEVICE3_BASE 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE); 47 #endif 48 #ifdef BCM_DRAM0_NS_BASE 49 register_dynamic_shm(BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE); 50 #endif 51 #ifdef BCM_DRAM1_NS_BASE 52 register_dynamic_shm(BCM_DRAM1_NS_BASE, BCM_DRAM1_NS_SIZE); 53 #endif 54 #ifdef BCM_DRAM2_NS_BASE 55 register_dynamic_shm(BCM_DRAM2_NS_BASE, BCM_DRAM2_NS_SIZE); 56 #endif 57 58 const struct thread_handlers *generic_boot_get_handlers(void) 59 { 60 return &handlers; 61 } 62 63 void console_init(void) 64 { 65 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 66 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 67 register_serial_console(&console_data.chip); 68 } 69 70 static void secure_intr_handler(void) 71 { 72 gic_it_handle(&gic_data); 73 } 74 75 void main_init_gic(void) 76 { 77 vaddr_t gicd_base; 78 79 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 80 81 if (!gicd_base) 82 panic(); 83 84 gic_init_base_addr(&gic_data, 0, gicd_base); 85 itr_init(&gic_data.chip); 86 87 } 88