1 /* 2 * Copyright 2015 Linaro Limited 3 * Copyright 2013-2014 Andrew Turner. 4 * Copyright 2013-2014 Ian Lepore. 5 * Copyright 2013-2014 Rui Paulo. 6 * Copyright 2013 Eitan Adler. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are 11 * met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 26 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <arm.h> 33 #include <kernel/misc.h> 34 #include <kernel/unwind.h> 35 #include <string.h> 36 #include <trace.h> 37 38 /* The register names */ 39 #define FP 11 40 #define SP 13 41 #define LR 14 42 #define PC 15 43 44 /* 45 * Definitions for the instruction interpreter. 46 * 47 * The ARM EABI specifies how to perform the frame unwinding in the 48 * Exception Handling ABI for the ARM Architecture document. To perform 49 * the unwind we need to know the initial frame pointer, stack pointer, 50 * link register and program counter. We then find the entry within the 51 * index table that points to the function the program counter is within. 52 * This gives us either a list of three instructions to process, a 31-bit 53 * relative offset to a table of instructions, or a value telling us 54 * we can't unwind any further. 55 * 56 * When we have the instructions to process we need to decode them 57 * following table 4 in section 9.3. This describes a collection of bit 58 * patterns to encode that steps to take to update the stack pointer and 59 * link register to the correct values at the start of the function. 60 */ 61 62 /* A special case when we are unable to unwind past this function */ 63 #define EXIDX_CANTUNWIND 1 64 65 /* 66 * Entry types. 67 * These are the only entry types that have been seen in the kernel. 68 */ 69 #define ENTRY_MASK 0xff000000 70 #define ENTRY_ARM_SU16 0x80000000 71 #define ENTRY_ARM_LU16 0x81000000 72 73 /* Instruction masks. */ 74 #define INSN_VSP_MASK 0xc0 75 #define INSN_VSP_SIZE_MASK 0x3f 76 #define INSN_STD_MASK 0xf0 77 #define INSN_STD_DATA_MASK 0x0f 78 #define INSN_POP_TYPE_MASK 0x08 79 #define INSN_POP_COUNT_MASK 0x07 80 #define INSN_VSP_LARGE_INC_MASK 0xff 81 82 /* Instruction definitions */ 83 #define INSN_VSP_INC 0x00 84 #define INSN_VSP_DEC 0x40 85 #define INSN_POP_MASKED 0x80 86 #define INSN_VSP_REG 0x90 87 #define INSN_POP_COUNT 0xa0 88 #define INSN_FINISH 0xb0 89 #define INSN_POP_REGS 0xb1 90 #define INSN_VSP_LARGE_INC 0xb2 91 92 /* An item in the exception index table */ 93 struct unwind_idx { 94 uint32_t offset; 95 uint32_t insn; 96 }; 97 98 /* Expand a 31-bit signed value to a 32-bit signed value */ 99 static int32_t expand_prel31(uint32_t prel31) 100 { 101 return prel31 | SHIFT_U32(prel31 & BIT32(30), 1); 102 } 103 104 /* 105 * Perform a binary search of the index table to find the function 106 * with the largest address that doesn't exceed addr. 107 */ 108 static struct unwind_idx *find_index(uint32_t addr, vaddr_t exidx, 109 size_t exidx_sz) 110 { 111 vaddr_t idx_start, idx_end; 112 unsigned int min, mid, max; 113 struct unwind_idx *start; 114 struct unwind_idx *item; 115 int32_t prel31_addr; 116 vaddr_t func_addr; 117 118 start = (struct unwind_idx *)exidx; 119 idx_start = exidx; 120 idx_end = exidx + exidx_sz; 121 122 min = 0; 123 max = (idx_end - idx_start) / sizeof(struct unwind_idx); 124 125 while (min != max) { 126 mid = min + (max - min + 1) / 2; 127 128 item = &start[mid]; 129 130 prel31_addr = expand_prel31(item->offset); 131 func_addr = (vaddr_t)&item->offset + prel31_addr; 132 133 if (func_addr <= addr) { 134 min = mid; 135 } else { 136 max = mid - 1; 137 } 138 } 139 140 return &start[min]; 141 } 142 143 /* Reads the next byte from the instruction list */ 144 static uint8_t unwind_exec_read_byte(struct unwind_state_arm32 *state) 145 { 146 uint8_t insn; 147 148 /* Read the unwind instruction */ 149 insn = (*state->insn) >> (state->byte * 8); 150 151 /* Update the location of the next instruction */ 152 if (state->byte == 0) { 153 state->byte = 3; 154 state->insn++; 155 state->entries--; 156 } else 157 state->byte--; 158 159 return insn; 160 } 161 162 /* Executes the next instruction on the list */ 163 static bool unwind_exec_insn(struct unwind_state_arm32 *state) 164 { 165 unsigned int insn; 166 uint32_t *vsp = (uint32_t *)(uintptr_t)state->registers[SP]; 167 int update_vsp = 0; 168 169 /* This should never happen */ 170 if (state->entries == 0) 171 return false; 172 173 /* Read the next instruction */ 174 insn = unwind_exec_read_byte(state); 175 176 if ((insn & INSN_VSP_MASK) == INSN_VSP_INC) { 177 state->registers[SP] += ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; 178 179 } else if ((insn & INSN_VSP_MASK) == INSN_VSP_DEC) { 180 state->registers[SP] -= ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; 181 182 } else if ((insn & INSN_STD_MASK) == INSN_POP_MASKED) { 183 unsigned int mask, reg; 184 185 /* Load the mask */ 186 mask = unwind_exec_read_byte(state); 187 mask |= (insn & INSN_STD_DATA_MASK) << 8; 188 189 /* We have a refuse to unwind instruction */ 190 if (mask == 0) 191 return false; 192 193 /* Update SP */ 194 update_vsp = 1; 195 196 /* Load the registers */ 197 for (reg = 4; mask && reg < 16; mask >>= 1, reg++) { 198 if (mask & 1) { 199 state->registers[reg] = *vsp++; 200 state->update_mask |= 1 << reg; 201 202 /* If we have updated SP kep its value */ 203 if (reg == SP) 204 update_vsp = 0; 205 } 206 } 207 208 } else if ((insn & INSN_STD_MASK) == INSN_VSP_REG && 209 ((insn & INSN_STD_DATA_MASK) != 13) && 210 ((insn & INSN_STD_DATA_MASK) != 15)) { 211 /* sp = register */ 212 state->registers[SP] = 213 state->registers[insn & INSN_STD_DATA_MASK]; 214 215 } else if ((insn & INSN_STD_MASK) == INSN_POP_COUNT) { 216 unsigned int count, reg; 217 218 /* Read how many registers to load */ 219 count = insn & INSN_POP_COUNT_MASK; 220 221 /* Update sp */ 222 update_vsp = 1; 223 224 /* Pop the registers */ 225 for (reg = 4; reg <= 4 + count; reg++) { 226 state->registers[reg] = *vsp++; 227 state->update_mask |= 1 << reg; 228 } 229 230 /* Check if we are in the pop r14 version */ 231 if ((insn & INSN_POP_TYPE_MASK) != 0) { 232 state->registers[14] = *vsp++; 233 } 234 235 } else if (insn == INSN_FINISH) { 236 /* Stop processing */ 237 state->entries = 0; 238 239 } else if (insn == INSN_POP_REGS) { 240 unsigned int mask, reg; 241 242 mask = unwind_exec_read_byte(state); 243 if (mask == 0 || (mask & 0xf0) != 0) 244 return false; 245 246 /* Update SP */ 247 update_vsp = 1; 248 249 /* Load the registers */ 250 for (reg = 0; mask && reg < 4; mask >>= 1, reg++) { 251 if (mask & 1) { 252 state->registers[reg] = *vsp++; 253 state->update_mask |= 1 << reg; 254 } 255 } 256 257 } else if ((insn & INSN_VSP_LARGE_INC_MASK) == INSN_VSP_LARGE_INC) { 258 unsigned int uleb128; 259 260 /* Read the increment value */ 261 uleb128 = unwind_exec_read_byte(state); 262 263 state->registers[SP] += 0x204 + (uleb128 << 2); 264 265 } else { 266 /* We hit a new instruction that needs to be implemented */ 267 DMSG("Unhandled instruction %.2x\n", insn); 268 return false; 269 } 270 271 if (update_vsp) { 272 state->registers[SP] = (uint32_t)(uintptr_t)vsp; 273 } 274 275 return true; 276 } 277 278 /* Performs the unwind of a function */ 279 static bool unwind_tab(struct unwind_state_arm32 *state) 280 { 281 uint32_t entry; 282 283 /* Set PC to a known value */ 284 state->registers[PC] = 0; 285 286 /* Read the personality */ 287 entry = *state->insn & ENTRY_MASK; 288 289 if (entry == ENTRY_ARM_SU16) { 290 state->byte = 2; 291 state->entries = 1; 292 } else if (entry == ENTRY_ARM_LU16) { 293 state->byte = 1; 294 state->entries = ((*state->insn >> 16) & 0xFF) + 1; 295 } else { 296 DMSG("Unknown entry: %x\n", entry); 297 return true; 298 } 299 300 while (state->entries > 0) { 301 if (!unwind_exec_insn(state)) 302 return true; 303 } 304 305 /* 306 * The program counter was not updated, load it from the link register. 307 */ 308 if (state->registers[PC] == 0) { 309 state->registers[PC] = state->registers[LR]; 310 311 /* 312 * If the program counter changed, flag it in the update mask. 313 */ 314 if (state->start_pc != state->registers[PC]) 315 state->update_mask |= 1 << PC; 316 } 317 318 return false; 319 } 320 321 bool unwind_stack_arm32(struct unwind_state_arm32 *state, uaddr_t exidx, 322 size_t exidx_sz) 323 { 324 struct unwind_idx *index; 325 bool finished; 326 327 /* Reset the mask of updated registers */ 328 state->update_mask = 0; 329 330 /* The pc value is correct and will be overwritten, save it */ 331 state->start_pc = state->registers[PC]; 332 333 /* Find the item to run */ 334 index = find_index(state->start_pc, exidx, exidx_sz); 335 336 finished = false; 337 if (index->insn != EXIDX_CANTUNWIND) { 338 if (index->insn & (1U << 31)) { 339 /* The data is within the instruction */ 340 state->insn = &index->insn; 341 } else { 342 /* A prel31 offset to the unwind table */ 343 state->insn = (uint32_t *) 344 ((uintptr_t)&index->insn + 345 expand_prel31(index->insn)); 346 } 347 /* Run the unwind function */ 348 finished = unwind_tab(state); 349 } 350 351 /* This is the top of the stack, finish */ 352 if (index->insn == EXIDX_CANTUNWIND) 353 finished = true; 354 355 return !finished; 356 } 357 358 #if defined(CFG_UNWIND) && defined(ARM32) && (TRACE_LEVEL > 0) 359 360 void print_kernel_stack(int level) 361 { 362 struct unwind_state_arm32 state; 363 364 memset(state.registers, 0, sizeof(state.registers)); 365 /* r7: Thumb-style frame pointer */ 366 state.registers[7] = read_r7(); 367 /* r11: ARM-style frame pointer */ 368 state.registers[FP] = read_fp(); 369 state.registers[SP] = read_sp(); 370 state.registers[LR] = read_lr(); 371 state.registers[PC] = (uint32_t)print_kernel_stack; 372 373 do { 374 switch (level) { 375 case TRACE_FLOW: 376 FMSG_RAW("pc 0x%08" PRIx32, state.registers[PC]); 377 break; 378 case TRACE_DEBUG: 379 DMSG_RAW("pc 0x%08" PRIx32, state.registers[PC]); 380 break; 381 case TRACE_INFO: 382 IMSG_RAW("pc 0x%08" PRIx32, state.registers[PC]); 383 break; 384 case TRACE_ERROR: 385 EMSG_RAW("pc 0x%08" PRIx32, state.registers[PC]); 386 break; 387 default: 388 break; 389 } 390 } while (unwind_stack_arm32(&state, 0, 0)); 391 } 392 393 #endif 394