1/* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <asm.S> 29#include <arm64_macros.S> 30#include <arm64.h> 31#include <sm/teesmc.h> 32#include <sm/teesmc_opteed_macros.h> 33#include <sm/teesmc_opteed.h> 34#include <kernel/thread_defs.h> 35#include <kernel/thread.h> 36#include "thread_private.h" 37 38 .macro get_thread_ctx core_local, res, tmp0, tmp1 39 ldr w\tmp0, [\core_local, \ 40 #THREAD_CORE_LOCAL_CURR_THREAD_OFFSET] 41 adr x\res, threads 42 mov x\tmp1, #THREAD_CTX_SIZE 43 madd x\res, x\tmp0, x\tmp1, x\res 44 .endm 45 46 .section .text.thread_asm 47LOCAL_FUNC vector_std_smc_entry , : 48 sub sp, sp, #THREAD_SMC_ARGS_SIZE 49 store_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 0, 7 50 mov x0, sp 51 bl thread_handle_std_smc 52 /* 53 * Normally thread_handle_std_smc() should return via 54 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 55 * hasn't switched stack (error detected) it will do a normal "C" 56 * return. 57 */ 58 load_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 1, 8 59 add sp, sp, #THREAD_SMC_ARGS_SIZE 60 ldr x0, =TEESMC_OPTEED_RETURN_CALL_DONE 61 smc #0 62 b . /* SMC should not return */ 63END_FUNC vector_std_smc_entry 64 65LOCAL_FUNC vector_fast_smc_entry , : 66 sub sp, sp, #THREAD_SMC_ARGS_SIZE 67 store_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 0, 7 68 mov x0, sp 69 bl thread_handle_fast_smc 70 load_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 1, 8 71 add sp, sp, #THREAD_SMC_ARGS_SIZE 72 ldr x0, =TEESMC_OPTEED_RETURN_CALL_DONE 73 smc #0 74 b . /* SMC should not return */ 75END_FUNC vector_fast_smc_entry 76 77LOCAL_FUNC vector_fiq_entry , : 78 /* Secure Monitor received a FIQ and passed control to us. */ 79 bl thread_check_canaries 80 adr x16, thread_fiq_handler_ptr 81 ldr x16, [x16] 82 blr x16 83 ldr x0, =TEESMC_OPTEED_RETURN_FIQ_DONE 84 smc #0 85 b . /* SMC should not return */ 86END_FUNC vector_fiq_entry 87 88LOCAL_FUNC vector_cpu_on_entry , : 89 adr x16, thread_cpu_on_handler_ptr 90 ldr x16, [x16] 91 blr x16 92 mov x1, x0 93 ldr x0, =TEESMC_OPTEED_RETURN_ON_DONE 94 smc #0 95 b . /* SMC should not return */ 96END_FUNC vector_cpu_on_entry 97 98LOCAL_FUNC vector_cpu_off_entry , : 99 adr x16, thread_cpu_off_handler_ptr 100 ldr x16, [x16] 101 blr x16 102 mov x1, x0 103 ldr x0, =TEESMC_OPTEED_RETURN_OFF_DONE 104 smc #0 105 b . /* SMC should not return */ 106END_FUNC vector_cpu_off_entry 107 108LOCAL_FUNC vector_cpu_suspend_entry , : 109 adr x16, thread_cpu_suspend_handler_ptr 110 ldr x16, [x16] 111 blr x16 112 mov x1, x0 113 ldr x0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 114 smc #0 115 b . /* SMC should not return */ 116END_FUNC vector_cpu_suspend_entry 117 118LOCAL_FUNC vector_cpu_resume_entry , : 119 adr x16, thread_cpu_resume_handler_ptr 120 ldr x16, [x16] 121 blr x16 122 mov x1, x0 123 ldr x0, =TEESMC_OPTEED_RETURN_RESUME_DONE 124 smc #0 125 b . /* SMC should not return */ 126END_FUNC vector_cpu_resume_entry 127 128LOCAL_FUNC vector_system_off_entry , : 129 adr x16, thread_system_off_handler_ptr 130 ldr x16, [x16] 131 blr x16 132 mov x1, x0 133 ldr x0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 134 smc #0 135 b . /* SMC should not return */ 136END_FUNC vector_system_off_entry 137 138LOCAL_FUNC vector_system_reset_entry , : 139 adr x16, thread_system_reset_handler_ptr 140 ldr x16, [x16] 141 blr x16 142 mov x1, x0 143 ldr x0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 144 smc #0 145 b . /* SMC should not return */ 146END_FUNC vector_system_reset_entry 147 148/* 149 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 150 * initialization. 151 * 152 * Note that ARM-TF depends on the layout of this vector table, any change 153 * in layout has to be synced with ARM-TF. 154 */ 155FUNC thread_vector_table , : 156 b vector_std_smc_entry 157 b vector_fast_smc_entry 158 b vector_cpu_on_entry 159 b vector_cpu_off_entry 160 b vector_cpu_resume_entry 161 b vector_cpu_suspend_entry 162 b vector_fiq_entry 163 b vector_system_off_entry 164 b vector_system_reset_entry 165END_FUNC thread_vector_table 166 167 168/* void thread_resume(struct thread_ctx_regs *regs) */ 169FUNC thread_resume , : 170 load_xregs x0, THREAD_CTX_REGS_SP_OFFSET, 1, 3 171 mov sp, x1 172 msr elr_el1, x2 173 msr spsr_el1, x3 174 load_xregs x0, THREAD_CTX_REGS_X_OFFSET(1), 1, 30 175 ldr x0, [x0, THREAD_CTX_REGS_X_OFFSET(0)] 176 eret 177END_FUNC thread_resume 178 179FUNC thread_std_smc_entry , : 180 /* pass x0-x7 in a struct thread_smc_args */ 181 sub sp, sp, #THREAD_SMC_ARGS_SIZE 182 store_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 0, 7 183 mov x0, sp 184 185 /* Call the registered handler */ 186 bl __thread_std_smc_entry 187 188 /* 189 * Load the returned x0-x3 into preserved registers and skip the 190 * "returned" x4-x7 since they will not be returned to normal 191 * world. 192 */ 193 load_xregs sp, THREAD_SMC_ARGS_X_OFFS(0), 20, 23 194 add sp, sp, #THREAD_SMC_ARGS_SIZE 195 196 /* Disable interrupts before switching to temporary stack */ 197 msr daifset, #(DAIFBIT_FIQ | DAIFBIT_IRQ) 198 bl thread_get_tmp_sp 199 mov sp, x0 200 201 bl thread_state_free 202 203 ldr x0, =TEESMC_OPTEED_RETURN_CALL_DONE 204 mov x1, x20 205 mov x2, x21 206 mov x3, x22 207 mov x4, x23 208 smc #0 209 b . /* SMC should not return */ 210END_FUNC thread_std_smc_entry 211 212/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 213FUNC thread_rpc , : 214 /* Read daif and create an SPSR */ 215 mrs x1, daif 216 orr x1, x1, #(SPSR_64_MODE_EL1 << SPSR_64_MODE_EL_SHIFT) 217 218 msr daifset, #DAIFBIT_ALL 219 push x0, xzr 220 push x1, x30 221 bl thread_get_ctx_regs 222 ldr x30, [sp, #8] 223 store_xregs x0, THREAD_CTX_REGS_X_OFFSET(19), 19, 30 224 mov x19, x0 225 226 bl thread_get_tmp_sp 227 pop x1, xzr /* Match "push x1, x30" above */ 228 mov x2, sp 229 str x2, [x19, #THREAD_CTX_REGS_SP_OFFSET] 230 ldr x20, [sp] /* Get pointer to rv[] */ 231 mov sp, x0 /* Switch to tmp stack */ 232 233 adr x2, .thread_rpc_return 234 mov w0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 235 bl thread_state_suspend 236 mov x4, x0 /* Supply thread index */ 237 ldr w0, =TEESMC_OPTEED_RETURN_CALL_DONE 238 load_wregs x20, 0, 1, 3 /* Load rv[] into x0-x2 */ 239 smc #0 240 b . /* SMC should not return */ 241 242.thread_rpc_return: 243 /* 244 * At this point has the stack pointer been restored to the value 245 * stored in THREAD_CTX above. 246 * 247 * Jumps here from thread_resume above when RPC has returned. The 248 * IRQ and FIQ bits are restored to what they where when this 249 * function was originally entered. 250 */ 251 pop x4, xzr /* Get pointer to rv[] */ 252 store_wregs x4, 0, 0, 2 /* Store x0-x2 into rv[] */ 253 ret 254END_FUNC thread_rpc 255 256FUNC thread_init_vbar , : 257 adr x0, thread_vect_table 258 msr vbar_el1, x0 259 ret 260END_FUNC thread_init_vbar 261 262/* 263 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 264 * unsigned long a2, unsigned long a3, unsigned long user_sp, 265 * unsigned long user_func, unsigned long spsr, 266 * uint32_t *exit_status0, uint32_t *exit_status1) 267 * 268 */ 269FUNC __thread_enter_user_mode , : 270 ldr x8, [sp] 271 /* 272 * Create the and fill in the struct thread_user_mode_rec 273 */ 274 sub sp, sp, #THREAD_USER_MODE_REC_SIZE 275 store_xregs sp, THREAD_USER_MODE_REC_EXIT_STATUS0_PTR_OFFSET, 7, 8 276 store_xregs sp, THREAD_USER_MODE_REC_X_OFFSET(19), 19, 30 277 278 /* 279 * Switch to SP_EL1 280 * Disable exceptions 281 * Save kern sp in x19 282 */ 283 msr daifset, #DAIFBIT_ALL 284 mov x19, sp 285 msr spsel, #1 286 287 /* 288 * Save the kernel stack pointer in the thread context 289 */ 290 /* get pointer to current thread context */ 291 get_thread_ctx sp, 21, 20, 22 292 /* save kernel stack pointer */ 293 str x19, [x21, #THREAD_CTX_KERN_SP_OFFSET] 294 295 /* 296 * Initialize SPSR, ELR_EL1, and SP_EL0 to enter user mode 297 */ 298 msr spsr_el1, x6 299 /* Set user sp */ 300 mov x13, x4 /* Used when running TA in Aarch32 */ 301 msr sp_el0, x4 /* Used when running TA in Aarch64 */ 302 /* Set user function */ 303 msr elr_el1, x5 304 305 /* Jump into user mode */ 306 eret 307END_FUNC __thread_enter_user_mode 308 309/* 310 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 311 * uint32_t exit_status1); 312 * See description in thread.h 313 */ 314FUNC thread_unwind_user_mode , : 315 /* Store the exit status */ 316 ldp x3, x4, [sp, #THREAD_USER_MODE_REC_EXIT_STATUS0_PTR_OFFSET] 317 str w1, [x3] 318 str w2, [x4] 319 /* Restore x19..x30 */ 320 load_xregs sp, THREAD_USER_MODE_REC_X_OFFSET(19), 19, 30 321 add sp, sp, #THREAD_USER_MODE_REC_SIZE 322 /* Return from the call of thread_enter_user_mode() */ 323 ret 324END_FUNC thread_unwind_user_mode 325 326 /* 327 * This macro verifies that the a given vector doesn't exceed the 328 * architectural limit of 32 instructions. This is meant to be placed 329 * immedately after the last instruction in the vector. It takes the 330 * vector entry as the parameter 331 */ 332 .macro check_vector_size since 333 .if (. - \since) > (32 * 4) 334 .error "Vector exceeds 32 instructions" 335 .endif 336 .endm 337 338 339 .align 11 340LOCAL_FUNC thread_vect_table , : 341 /* ----------------------------------------------------- 342 * EL1 with SP0 : 0x0 - 0x180 343 * ----------------------------------------------------- 344 */ 345 .align 7 346sync_el1_sp0: 347 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 348 b el1_sync_abort 349 check_vector_size sync_el1_sp0 350 351 .align 7 352irq_el1_sp0: 353 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 354 b elx_irq 355 check_vector_size irq_el1_sp0 356 357 .align 7 358fiq_el1_sp0: 359 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 360 b elx_fiq 361 check_vector_size fiq_el1_sp0 362 363 .align 7 364SErrorSP0: 365 b SErrorSP0 366 check_vector_size SErrorSP0 367 368 /* ----------------------------------------------------- 369 * Current EL with SPx: 0x200 - 0x380 370 * ----------------------------------------------------- 371 */ 372 .align 7 373SynchronousExceptionSPx: 374 b SynchronousExceptionSPx 375 check_vector_size SynchronousExceptionSPx 376 377 .align 7 378IrqSPx: 379 b IrqSPx 380 check_vector_size IrqSPx 381 382 .align 7 383FiqSPx: 384 b FiqSPx 385 check_vector_size FiqSPx 386 387 .align 7 388SErrorSPx: 389 b SErrorSPx 390 check_vector_size SErrorSPx 391 392 /* ----------------------------------------------------- 393 * Lower EL using AArch64 : 0x400 - 0x580 394 * ----------------------------------------------------- 395 */ 396 .align 7 397el0_sync_a64: 398 b el0_sync_a64 399 check_vector_size el0_sync_a64 400 401 .align 7 402IrqA64: 403 b IrqA64 404 check_vector_size IrqA64 405 406 .align 7 407FiqA64: 408 b FiqA64 409 check_vector_size FiqA64 410 411 .align 7 412SErrorA64: 413 b SErrorA64 414 check_vector_size SErrorA64 415 416 /* ----------------------------------------------------- 417 * Lower EL using AArch32 : 0x0 - 0x180 418 * ----------------------------------------------------- 419 */ 420 .align 7 421el0_sync_a32: 422 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 423 mrs x2, esr_el1 424 mrs x3, sp_el0 425 lsr x2, x2, #ESR_EC_SHIFT 426 cmp x2, #ESR_EC_AARCH32_SVC 427 b.eq el0_sync_a32_svc 428 b el0_sync_abort 429 check_vector_size el0_sync_a32 430 431 .align 7 432el0_irq_a32: 433 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 434 b elx_irq 435 check_vector_size el0_irq_a32 436 437 .align 7 438el0_fiq_a32: 439 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 440 b elx_fiq 441 check_vector_size el0_fiq_a32 442 443 .align 7 444SErrorA32: 445 b SErrorA32 446 check_vector_size SErrorA32 447 448END_FUNC thread_vect_table 449 450LOCAL_FUNC el0_sync_a32_svc , : 451 /* get pointer to current thread context in x0 */ 452 get_thread_ctx sp, 0, 1, 2 453 /* load saved kernel sp */ 454 ldr x0, [x0, #THREAD_CTX_KERN_SP_OFFSET] 455 /* Keep pointer to initial recod in x1 */ 456 mov x1, sp 457 /* Switch to SP_EL0 and restore kernel sp */ 458 msr spsel, #0 459 mov sp, x0 460 /* Restore x0-x3 */ 461 ldp x2, x3, [x1, #THREAD_CORE_LOCAL_X_OFFSET(2)] 462 ldp x0, x1, [x1, #THREAD_CORE_LOCAL_X_OFFSET(0)] 463 464 /* Prepare the argument for the handler */ 465 sub sp, sp, #THREAD_SVC_REG_SIZE 466 store_xregs sp, THREAD_SVC_REG_X_OFFS(0), 0, 14 467 mrs x0, elr_el1 468 mrs x1, spsr_el1 469 store_xregs sp, THREAD_SVC_REG_ELR_OFFS, 0, 1 470 mov x0, sp 471 472 /* 473 * Unmask FIQ, Serror, and debug exceptions since we have nothing 474 * left in sp_el1. Note that the SVC handler is excepted to 475 * re-enable IRQs by itself. 476 */ 477 msr daifclr, #(DAIFBIT_FIQ | DAIFBIT_ABT | DAIFBIT_DBG) 478 479 /* Call the registered handler */ 480 adr x16, thread_svc_handler_ptr 481 ldr x16, [x16] 482 blr x16 483 484 /* Mask all maskable exceptions since we're switching back to sp_el1 */ 485 msr daifset, #DAIFBIT_ALL 486 487 /* Save kernel sp we'll have after the add below */ 488 msr spsel, #1 489 get_thread_ctx sp, 0, 1, 2 490 msr spsel, #0 491 add x1, sp, #THREAD_SVC_REG_SIZE 492 str x1, [x0, #THREAD_CTX_KERN_SP_OFFSET] 493 494 /* Restore registers to the required state and return*/ 495 load_xregs sp, THREAD_SVC_REG_ELR_OFFS, 0, 1 496 msr elr_el1, x0 497 msr spsr_el1, x1 498 load_xregs sp, THREAD_SVC_REG_X_OFFS(0), 0, 14 499 add sp, sp, #THREAD_SVC_REG_SIZE 500 501 eret 502END_FUNC el0_sync_a32_svc 503 504LOCAL_FUNC el1_sync_abort , : 505 mov x0, sp 506 msr spsel, #0 507 508 /* Update core local flags */ 509 ldr w1, [x0, #THREAD_CORE_LOCAL_FLAGS_OFFSET] 510 lsl w1, w1, #THREAD_CLF_SAVED_SHIFT 511 orr w1, w1, #THREAD_CLF_ABORT 512 str w1, [x0, #THREAD_CORE_LOCAL_FLAGS_OFFSET] 513 514 /* 515 * Check if we should initialize SP_EL0 or use it as is (recursive 516 * aborts). 517 */ 518 tst w1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 519 mov x3, sp /* Save original sp unconditionally */ 520 beq .keep_sp 521 ldr x2, [x0, #THREAD_CORE_LOCAL_ABT_STACK_VA_END_OFFSET] 522 mov sp, x2 523.keep_sp: 524 525 /* 526 * Save state on stack 527 */ 528 sub sp, sp, #THREAD_ABT_REGS_SIZE 529 mrs x2, spsr_el1 530 /* Store spsr, sp_el0 */ 531 stp x2, x3, [sp, #THREAD_ABT_REG_SPSR_OFFS] 532 /* Store original x0, x1 */ 533 ldp x2, x3, [x0, #THREAD_CORE_LOCAL_X_OFFSET(0)] 534 stp x2, x3, [sp, #THREAD_ABT_REG_X_OFFS(0)] 535 /* Store original x2, x3 and x4 to x29 */ 536 ldp x2, x3, [x0, #THREAD_CORE_LOCAL_X_OFFSET(2)] 537 store_xregs sp, THREAD_ABT_REG_X_OFFS(2), 2, 29 538 /* Store x30, elr_el1 */ 539 mrs x0, elr_el1 540 stp x30, x0, [sp, #THREAD_ABT_REG_X_OFFS(30)] 541 542 /* 543 * Call handler 544 */ 545 mov x0, #0 546 mov x1, sp 547 bl thread_handle_abort 548 549 /* 550 * Restore state from stack 551 */ 552 /* Load x30, elr_el1 */ 553 ldp x30, x0, [sp, #THREAD_ABT_REG_X_OFFS(30)] 554 msr elr_el1, x0 555 /* Load x0 to x29 */ 556 load_xregs sp, THREAD_ABT_REG_X_OFFS(0), 0, 29 557 /* Switch to SP_EL1 */ 558 msr spsel, #1 559 /* Save x0 to x3 in CORE_LOCAL */ 560 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 561 /* Restore spsr_el1 and sp_el0 */ 562 mrs x3, sp_el0 563 ldp x0, x1, [x3, #THREAD_ABT_REG_SPSR_OFFS] 564 msr spsr_el1, x0 565 msr sp_el0, x1 566 567 /* Update core local flags */ 568 ldr w0, [sp, #THREAD_CORE_LOCAL_FLAGS_OFFSET] 569 lsr w0, w0, #THREAD_CLF_SAVED_SHIFT 570 str w0, [sp, #THREAD_CORE_LOCAL_FLAGS_OFFSET] 571 572 /* Restore x0 to x3 */ 573 load_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 574 575 /* Return from exception */ 576 eret 577END_FUNC el1_sync_abort 578 579 /* sp_el0 in x3 */ 580LOCAL_FUNC el0_sync_abort , : 581 /* load abt_stack_va_end */ 582 ldr x1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END_OFFSET] 583 /* Keep pointer to initial record in x0 */ 584 mov x0, sp 585 /* Switch to SP_EL0 */ 586 msr spsel, #0 587 mov sp, x1 588 sub sp, sp, #THREAD_ABT_REGS_SIZE 589 mrs x2, spsr_el1 590 /* Store spsr, sp_el0 */ 591 stp x2, x3, [sp, #THREAD_ABT_REG_SPSR_OFFS] 592 /* Store original x0, x1 */ 593 ldp x2, x3, [x0, #THREAD_CORE_LOCAL_X_OFFSET(0)] 594 stp x2, x3, [sp, #THREAD_ABT_REG_X_OFFS(0)] 595 /* Store original x2, x3 and x4 to x29 */ 596 ldp x2, x3, [x0, #THREAD_CORE_LOCAL_X_OFFSET(2)] 597 store_xregs sp, THREAD_ABT_REG_X_OFFS(2), 2, 29 598 /* Store x30, elr_el1 */ 599 mrs x0, elr_el1 600 stp x30, x0, [sp, #THREAD_ABT_REG_X_OFFS(30)] 601 /* Call handler */ 602 mov x0, #0 603 mov x1, sp 604 bl thread_handle_abort 605 /* Load x30, elr_el1 */ 606 ldp x30, x0, [sp, #THREAD_ABT_REG_X_OFFS(30)] 607 msr elr_el1, x0 608 /* Load x0 to x29 */ 609 load_xregs sp, THREAD_ABT_REG_X_OFFS(0), 0, 29 610 /* Switch to SP_EL1 */ 611 msr spsel, #1 612 /* Save x0 to x3 in EL1_REC */ 613 store_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 614 /* Restore spsr_el1 and sp_el0 */ 615 mrs x3, sp_el0 616 ldp x0, x1, [x3, #THREAD_ABT_REG_SPSR_OFFS] 617 msr spsr_el1, x0 618 msr sp_el0, x1 619 /* Restore x0 to x3 */ 620 load_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 621 /* Return from exception */ 622 eret 623END_FUNC el0_sync_abort 624 625/* 626 * struct elx_itr_rec { 627 * uint64_t x[19 - 4]; x4..x18 628 * uint64_t init_rec; 629 * uint64_t pad; 630 * uint64_t lr; 631 * uint64_t sp_el0; 632 * }; 633 */ 634#define ELX_ITR_REC_X_OFFSET(x) (8 * ((x) - 4)) 635#define ELX_ITR_REC_INIT_REC_OFFSET (8 + ELX_ITR_REC_X_OFFSET(19)) 636#define ELX_ITR_REC_PAD_OFFSET (8 + ELX_ITR_REC_INIT_REC_OFFSET) 637#define ELX_ITR_REC_LR_OFFSET (8 + ELX_ITR_REC_PAD_OFFSET) 638#define ELX_ITR_REC_SP_EL0_OFFSET (8 + ELX_ITR_REC_LR_OFFSET) 639#define ELX_ITR_REC_SIZE (8 + ELX_ITR_REC_SP_EL0_OFFSET) 640 641LOCAL_FUNC elx_irq , : 642 /* load tmp_stack_va_end */ 643 ldr x1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END_OFFSET] 644 /* Keep pointer to initial record in x0 */ 645 mov x0, sp 646 /* Keep original SP_EL0 */ 647 mrs x2, sp_el0 648 /* Switch to SP_EL0 */ 649 msr spsel, #0 650 mov sp, x1 651 652 /* 653 * Save registers on stack that can be corrupted by a call to 654 * thread_get_ctx_regs(). 655 */ 656 /* Make room for struct elx_itr_rec */ 657 sub sp, sp, #ELX_ITR_REC_SIZE 658 /* Store x4..x18 */ 659 store_xregs sp, ELX_ITR_REC_X_OFFSET(4), 4, 18 660 /* Store pointer to initial record */ 661 str x0, [sp, #ELX_ITR_REC_INIT_REC_OFFSET] 662 /* Store lr and original sp_el0 */ 663 stp x30, x2, [sp, #ELX_ITR_REC_LR_OFFSET] 664 665 /* 666 * Get pointer to struct thread_ctx_regs and store context 667 */ 668 bl thread_get_ctx_regs 669 /* Restore lr and original sp_el0 */ 670 ldp x30, x1, [sp, #ELX_ITR_REC_LR_OFFSET] 671 /* Store original sp_el0 */ 672 str x1, [x0, #THREAD_CTX_REGS_SP_OFFSET] 673 /* Restore x4..x18 */ 674 load_xregs sp, ELX_ITR_REC_X_OFFSET(4), 4, 18 675 /* store x4..x30 */ 676 store_xregs x0, THREAD_CTX_REGS_X_OFFSET(4), 4, 30 677 /* get pointer to initial record */ 678 ldr x4, [sp, #ELX_ITR_REC_INIT_REC_OFFSET] 679 /* Load original x0..x3 into x10..x13 */ 680 load_xregs x4, THREAD_CORE_LOCAL_X_OFFSET(0), 10, 13 681 /* Save original x0..x3 */ 682 store_xregs x0, THREAD_CTX_REGS_X_OFFSET(0), 10, 13 683 684 /* Remove struct elx_itr_rec from stack */ 685 add sp, sp, #ELX_ITR_REC_SIZE 686 687 /* 688 * Mark current thread as suspended 689 */ 690 mov w0, #THREAD_FLAGS_EXIT_ON_IRQ 691 mrs x1, spsr_el1 692 mrs x2, elr_el1 693 bl thread_state_suspend 694 mov w4, w0 /* Supply thread index */ 695 696 ldr w0, =TEESMC_OPTEED_RETURN_CALL_DONE 697 ldr w1, =TEESMC_RETURN_RPC_IRQ 698 mov w2, #0 699 mov w3, #0 700 /* w4 is already filled in above */ 701 smc #0 702 b . /* SMC should not return */ 703END_FUNC elx_irq 704 705LOCAL_FUNC elx_fiq , : 706 /* load tmp_stack_va_end */ 707 ldr x1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END_OFFSET] 708 /* Keep pointer to initial record in x0 */ 709 mov x0, sp 710 /* Keep original SP_EL0 */ 711 mrs x2, sp_el0 712 /* Switch to SP_EL0 */ 713 msr spsel, #0 714 mov sp, x1 715 716 /* 717 * Save registers on stack that can be corrupted by a call to 718 * a C function 719 */ 720 /* Make room for struct elx_itr_rec */ 721 sub sp, sp, #ELX_ITR_REC_SIZE 722 /* Store x4..x18 */ 723 store_xregs sp, ELX_ITR_REC_X_OFFSET(4), 4, 18 724 /* Store lr and original sp_el0 */ 725 stp x30, x2, [sp, #ELX_ITR_REC_LR_OFFSET] 726 727 bl thread_check_canaries 728 adr x16, thread_fiq_handler_ptr 729 ldr x16, [x16] 730 blr x16 731 732 /* 733 * Restore registers 734 */ 735 /* Restore x4..x18 */ 736 load_xregs sp, ELX_ITR_REC_X_OFFSET(4), 4, 18 737 /* Load lr and original sp_el0 */ 738 ldp x30, x2, [sp, #ELX_ITR_REC_LR_OFFSET] 739 /* Restore sp_el0 */ 740 mov sp, x2 741 /* Switch back to sp_el1 */ 742 msr spsel, #1 743 /* Restore x0..x3 */ 744 load_xregs sp, THREAD_CORE_LOCAL_X_OFFSET(0), 0, 3 745 746 /* Return from exception */ 747 eret 748END_FUNC elx_fiq 749