1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <arm32_macros.S> 31#include <arm.h> 32#include <asm.S> 33#include <generated/asm-defines.h> 34#include <keep.h> 35#include <kernel/abort.h> 36#include <kernel/thread_defs.h> 37#include <kernel/unwind.h> 38#include <mm/core_mmu.h> 39#include <sm/optee_smc.h> 40#include <sm/teesmc_opteed.h> 41#include <sm/teesmc_opteed_macros.h> 42 43#include "thread_private.h" 44 45 .macro cmp_spsr_user_mode reg:req 46 /* 47 * We're only testing the lower 4 bits as bit 5 (0x10) 48 * always is set. 49 */ 50 tst \reg, #0x0f 51 .endm 52 53LOCAL_FUNC vector_std_smc_entry , : 54UNWIND( .fnstart) 55UNWIND( .cantunwind) 56 push {r0-r7} 57 mov r0, sp 58 bl thread_handle_std_smc 59 /* 60 * Normally thread_handle_std_smc() should return via 61 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 62 * hasn't switched stack (error detected) it will do a normal "C" 63 * return. 64 */ 65 pop {r1-r8} 66 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 67 smc #0 68 b . /* SMC should not return */ 69UNWIND( .fnend) 70END_FUNC vector_std_smc_entry 71 72LOCAL_FUNC vector_fast_smc_entry , : 73UNWIND( .fnstart) 74UNWIND( .cantunwind) 75 push {r0-r7} 76 mov r0, sp 77 bl thread_handle_fast_smc 78 pop {r1-r8} 79 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 80 smc #0 81 b . /* SMC should not return */ 82UNWIND( .fnend) 83END_FUNC vector_fast_smc_entry 84 85LOCAL_FUNC vector_fiq_entry , : 86UNWIND( .fnstart) 87UNWIND( .cantunwind) 88 /* Secure Monitor received a FIQ and passed control to us. */ 89 bl thread_check_canaries 90 ldr lr, =thread_nintr_handler_ptr 91 ldr lr, [lr] 92 blx lr 93 mov r1, r0 94 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 95 smc #0 96 b . /* SMC should not return */ 97UNWIND( .fnend) 98END_FUNC vector_fiq_entry 99 100LOCAL_FUNC vector_cpu_on_entry , : 101UNWIND( .fnstart) 102UNWIND( .cantunwind) 103 ldr lr, =thread_cpu_on_handler_ptr 104 ldr lr, [lr] 105 blx lr 106 mov r1, r0 107 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 108 smc #0 109 b . /* SMC should not return */ 110UNWIND( .fnend) 111END_FUNC vector_cpu_on_entry 112 113LOCAL_FUNC vector_cpu_off_entry , : 114UNWIND( .fnstart) 115UNWIND( .cantunwind) 116 ldr lr, =thread_cpu_off_handler_ptr 117 ldr lr, [lr] 118 blx lr 119 mov r1, r0 120 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 121 smc #0 122 b . /* SMC should not return */ 123UNWIND( .fnend) 124END_FUNC vector_cpu_off_entry 125 126LOCAL_FUNC vector_cpu_suspend_entry , : 127UNWIND( .fnstart) 128UNWIND( .cantunwind) 129 ldr lr, =thread_cpu_suspend_handler_ptr 130 ldr lr, [lr] 131 blx lr 132 mov r1, r0 133 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 134 smc #0 135 b . /* SMC should not return */ 136UNWIND( .fnend) 137END_FUNC vector_cpu_suspend_entry 138 139LOCAL_FUNC vector_cpu_resume_entry , : 140UNWIND( .fnstart) 141UNWIND( .cantunwind) 142 ldr lr, =thread_cpu_resume_handler_ptr 143 ldr lr, [lr] 144 blx lr 145 mov r1, r0 146 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 147 smc #0 148 b . /* SMC should not return */ 149UNWIND( .fnend) 150END_FUNC vector_cpu_resume_entry 151 152LOCAL_FUNC vector_system_off_entry , : 153UNWIND( .fnstart) 154UNWIND( .cantunwind) 155 ldr lr, =thread_system_off_handler_ptr 156 ldr lr, [lr] 157 blx lr 158 mov r1, r0 159 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 160 smc #0 161 b . /* SMC should not return */ 162UNWIND( .fnend) 163END_FUNC vector_system_off_entry 164 165LOCAL_FUNC vector_system_reset_entry , : 166UNWIND( .fnstart) 167UNWIND( .cantunwind) 168 ldr lr, =thread_system_reset_handler_ptr 169 ldr lr, [lr] 170 blx lr 171 mov r1, r0 172 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 173 smc #0 174 b . /* SMC should not return */ 175UNWIND( .fnend) 176END_FUNC vector_system_reset_entry 177 178/* 179 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 180 * initialization. Also used when compiled with the internal monitor, but 181 * the cpu_*_entry and system_*_entry are not used then. 182 * 183 * Note that ARM-TF depends on the layout of this vector table, any change 184 * in layout has to be synced with ARM-TF. 185 */ 186FUNC thread_vector_table , : 187UNWIND( .fnstart) 188UNWIND( .cantunwind) 189 b vector_std_smc_entry 190 b vector_fast_smc_entry 191 b vector_cpu_on_entry 192 b vector_cpu_off_entry 193 b vector_cpu_resume_entry 194 b vector_cpu_suspend_entry 195 b vector_fiq_entry 196 b vector_system_off_entry 197 b vector_system_reset_entry 198UNWIND( .fnend) 199END_FUNC thread_vector_table 200KEEP_PAGER thread_vector_table 201 202FUNC thread_set_abt_sp , : 203UNWIND( .fnstart) 204UNWIND( .cantunwind) 205 mrs r1, cpsr 206 cps #CPSR_MODE_ABT 207 mov sp, r0 208 msr cpsr, r1 209 bx lr 210UNWIND( .fnend) 211END_FUNC thread_set_abt_sp 212 213FUNC thread_set_und_sp , : 214UNWIND( .fnstart) 215UNWIND( .cantunwind) 216 mrs r1, cpsr 217 cps #CPSR_MODE_UND 218 mov sp, r0 219 msr cpsr, r1 220 bx lr 221UNWIND( .fnend) 222END_FUNC thread_set_und_sp 223 224FUNC thread_set_irq_sp , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 mrs r1, cpsr 228 cps #CPSR_MODE_IRQ 229 mov sp, r0 230 msr cpsr, r1 231 bx lr 232UNWIND( .fnend) 233END_FUNC thread_set_irq_sp 234 235FUNC thread_set_fiq_sp , : 236UNWIND( .fnstart) 237UNWIND( .cantunwind) 238 mrs r1, cpsr 239 cps #CPSR_MODE_FIQ 240 mov sp, r0 241 msr cpsr, r1 242 bx lr 243UNWIND( .fnend) 244END_FUNC thread_set_fiq_sp 245 246/* void thread_resume(struct thread_ctx_regs *regs) */ 247FUNC thread_resume , : 248UNWIND( .fnstart) 249UNWIND( .cantunwind) 250 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 251 252 cps #CPSR_MODE_SYS 253 ldm r12!, {sp, lr} 254 255 cps #CPSR_MODE_SVC 256 ldm r12!, {r1, sp, lr} 257 msr spsr_fsxc, r1 258 259 ldm r12, {r1, r2} 260 261 /* 262 * Switching to some other mode than SVC as we need to set spsr in 263 * order to return into the old state properly and it may be SVC 264 * mode we're returning to. 265 */ 266 cps #CPSR_MODE_ABT 267 cmp_spsr_user_mode r2 268 mov lr, r1 269 msr spsr_fsxc, r2 270 ldm r0, {r0-r12} 271 movnes pc, lr 272 b eret_to_user_mode 273UNWIND( .fnend) 274END_FUNC thread_resume 275 276/* 277 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 278 * the banked r8-r12 registers, returns original CPSR. 279 */ 280LOCAL_FUNC thread_save_state_fiq , : 281UNWIND( .fnstart) 282UNWIND( .cantunwind) 283 mov r9, lr 284 285 /* 286 * Uses stack for temporary storage, while storing needed 287 * context in the thread context struct. 288 */ 289 290 mrs r8, cpsr 291 292 cpsid aif /* Disable Async abort, IRQ and FIQ */ 293 294 push {r4-r7} 295 push {r0-r3} 296 297 mrs r6, cpsr /* Save current CPSR */ 298 299 bl thread_get_ctx_regs 300 301 pop {r1-r4} /* r0-r3 pushed above */ 302 stm r0!, {r1-r4} 303 pop {r1-r4} /* r4-r7 pushed above */ 304 stm r0!, {r1-r4} 305 306 cps #CPSR_MODE_SYS 307 stm r0!, {r8-r12} 308 stm r0!, {sp, lr} 309 310 cps #CPSR_MODE_SVC 311 mrs r1, spsr 312 stm r0!, {r1, sp, lr} 313 314 /* back to fiq mode */ 315 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 316 msr cpsr, r6 /* Restore mode */ 317 318 mov r0, r8 /* Return original CPSR */ 319 bx r9 320UNWIND( .fnend) 321END_FUNC thread_save_state_fiq 322 323/* 324 * Disables IRQ and FIQ and saves state of thread, returns original 325 * CPSR. 326 */ 327LOCAL_FUNC thread_save_state , : 328UNWIND( .fnstart) 329UNWIND( .cantunwind) 330 push {r12, lr} 331 /* 332 * Uses stack for temporary storage, while storing needed 333 * context in the thread context struct. 334 */ 335 336 mrs r12, cpsr 337 338 cpsid aif /* Disable Async abort, IRQ and FIQ */ 339 340 push {r4-r7} 341 push {r0-r3} 342 343 mov r5, r12 /* Save CPSR in a preserved register */ 344 mrs r6, cpsr /* Save current CPSR */ 345 346 bl thread_get_ctx_regs 347 348 pop {r1-r4} /* r0-r3 pushed above */ 349 stm r0!, {r1-r4} 350 pop {r1-r4} /* r4-r7 pushed above */ 351 stm r0!, {r1-r4} 352 stm r0!, {r8-r11} 353 354 pop {r12, lr} 355 stm r0!, {r12} 356 357 cps #CPSR_MODE_SYS 358 stm r0!, {sp, lr} 359 360 cps #CPSR_MODE_SVC 361 mrs r1, spsr 362 stm r0!, {r1, sp, lr} 363 364 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 365 msr cpsr, r6 /* Restore mode */ 366 367 mov r0, r5 /* Return original CPSR */ 368 bx lr 369UNWIND( .fnend) 370END_FUNC thread_save_state 371 372FUNC thread_std_smc_entry , : 373UNWIND( .fnstart) 374UNWIND( .cantunwind) 375 /* Pass r0-r7 in a struct thread_smc_args */ 376 push {r0-r7} 377 mov r0, sp 378 bl __thread_std_smc_entry 379 /* 380 * Load the returned r0-r3 into preserved registers and skip the 381 * "returned" r4-r7 since they will not be returned to normal 382 * world. 383 */ 384 pop {r4-r7} 385 add sp, #(4 * 4) 386 387 /* Disable interrupts before switching to temporary stack */ 388 cpsid aif 389 bl thread_get_tmp_sp 390 mov sp, r0 391 392 bl thread_state_free 393 394 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 395 mov r1, r4 396 mov r2, r5 397 mov r3, r6 398 mov r4, r7 399 smc #0 400 b . /* SMC should not return */ 401UNWIND( .fnend) 402END_FUNC thread_std_smc_entry 403 404 405/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 406FUNC thread_rpc , : 407/* 408 * r0-r2 are used to pass parameters to normal world 409 * r0-r5 are used to pass return vaule back from normal world 410 * 411 * note that r3 is used to pass "resume information", that is, which 412 * thread it is that should resume. 413 * 414 * Since the this function is following AAPCS we need to preserve r4-r5 415 * which are otherwise modified when returning back from normal world. 416 */ 417UNWIND( .fnstart) 418 push {r4-r5, lr} 419UNWIND( .save {r4-r5, lr}) 420 push {r0} 421UNWIND( .save {r0}) 422 423 bl thread_save_state 424 mov r4, r0 /* Save original CPSR */ 425 426 /* 427 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 428 */ 429 bl thread_get_tmp_sp 430 ldr r5, [sp] /* Get pointer to rv[] */ 431 cps #CPSR_MODE_SVC /* Change to SVC mode */ 432 mov sp, r0 /* Switch to tmp stack */ 433 434 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 435 mov r1, r4 /* CPSR to restore */ 436 ldr r2, =.thread_rpc_return 437 bl thread_state_suspend 438 mov r4, r0 /* Supply thread index */ 439 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 440 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 441 smc #0 442 b . /* SMC should not return */ 443 444.thread_rpc_return: 445 /* 446 * At this point has the stack pointer been restored to the value 447 * it had when thread_save_state() was called above. 448 * 449 * Jumps here from thread_resume above when RPC has returned. The 450 * IRQ and FIQ bits are restored to what they where when this 451 * function was originally entered. 452 */ 453 pop {r12} /* Get pointer to rv[] */ 454 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 455 pop {r4-r5, pc} 456UNWIND( .fnend) 457END_FUNC thread_rpc 458KEEP_PAGER thread_rpc 459 460FUNC thread_init_vbar , : 461UNWIND( .fnstart) 462 /* Set vector (VBAR) */ 463 write_vbar r0 464 bx lr 465UNWIND( .fnend) 466END_FUNC thread_init_vbar 467KEEP_PAGER thread_init_vbar 468 469/* 470 * Below are low level routines handling entry and return from user mode. 471 * 472 * thread_enter_user_mode() saves all that registers user mode can change 473 * so kernel mode can restore needed registers when resuming execution 474 * after the call to thread_enter_user_mode() has returned. 475 * thread_enter_user_mode() doesn't return directly since it enters user 476 * mode instead, it's thread_unwind_user_mode() that does the 477 * returning by restoring the registers saved by thread_enter_user_mode(). 478 * 479 * There's three ways for thread_enter_user_mode() to return to caller, 480 * user TA calls utee_return, user TA calls utee_panic or through an abort. 481 * 482 * Calls to utee_return or utee_panic are handled as: 483 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 484 * calls syscall_return() or syscall_panic(). 485 * 486 * These function calls returns normally except thread_svc_handler() which 487 * which is an exception handling routine so it reads return address and 488 * SPSR to restore from the stack. syscall_return() and syscall_panic() 489 * changes return address and SPSR used by thread_svc_handler() to instead of 490 * returning into user mode as with other syscalls it returns into 491 * thread_unwind_user_mode() in kernel mode instead. When 492 * thread_svc_handler() returns the stack pointer at the point where 493 * thread_enter_user_mode() left it so this is where 494 * thread_unwind_user_mode() can operate. 495 * 496 * Aborts are handled in a similar way but by thread_abort_handler() 497 * instead, when the pager sees that it's an abort from user mode that 498 * can't be handled it updates SPSR and return address used by 499 * thread_abort_handler() to return into thread_unwind_user_mode() 500 * instead. 501 */ 502 503/* 504 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 505 * unsigned long a2, unsigned long a3, unsigned long user_sp, 506 * unsigned long user_func, unsigned long spsr, 507 * uint32_t *exit_status0, uint32_t *exit_status1) 508 * 509 */ 510FUNC __thread_enter_user_mode , : 511UNWIND( .fnstart) 512UNWIND( .cantunwind) 513 /* 514 * Save all registers to allow syscall_return() to resume execution 515 * as if this function would have returned. This is also used in 516 * syscall_panic(). 517 * 518 * If stack usage of this function is changed 519 * thread_unwind_user_mode() has to be updated. 520 */ 521 push {r4-r12,lr} 522 523 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 524 ldr r5, [sp, #(11 * 0x4)] /* user function */ 525 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 526 527 /* 528 * Save old user sp and set new user sp. 529 */ 530 cps #CPSR_MODE_SYS 531 mov r7, sp 532 mov sp, r4 533 cps #CPSR_MODE_SVC 534 push {r7,r8} 535 536 /* Prepare user mode entry via eret_to_user_mode */ 537 cpsid aif 538 msr spsr_fsxc, r6 539 mov lr, r5 540 541 b eret_to_user_mode 542UNWIND( .fnend) 543END_FUNC __thread_enter_user_mode 544 545/* 546 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 547 * uint32_t exit_status1); 548 * See description in thread.h 549 */ 550FUNC thread_unwind_user_mode , : 551UNWIND( .fnstart) 552UNWIND( .cantunwind) 553 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 554 str r1, [ip] 555 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 556 str r2, [ip] 557 558 /* Restore old user sp */ 559 pop {r4,r7} 560 cps #CPSR_MODE_SYS 561 mov sp, r4 562 cps #CPSR_MODE_SVC 563 564 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 565UNWIND( .fnend) 566END_FUNC thread_unwind_user_mode 567 568 .macro maybe_restore_mapping 569 /* 570 * This macro is a bit hard to read due to all the ifdefs, 571 * we're testing for two different configs which makes four 572 * different combinations. 573 * 574 * - With LPAE, and then some extra code if with 575 * CFG_CORE_UNMAP_CORE_AT_EL0 576 * - Without LPAE, and then some extra code if with 577 * CFG_CORE_UNMAP_CORE_AT_EL0 578 */ 579 580 /* 581 * At this point we can't rely on any memory being writable 582 * yet, so we're using TPIDRPRW to store r0, and if with 583 * LPAE TPIDRURO to store r1 too. 584 */ 585 write_tpidrprw r0 586#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 587 write_tpidruro r1 588#endif 589 590#ifdef CFG_WITH_LPAE 591 read_ttbr0_64bit r0, r1 592 tst r1, #BIT(TTBR_ASID_SHIFT - 32) 593 beq 11f 594 595#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 596 /* 597 * Update the mapping to use the full kernel mode mapping. 598 * Since the translation table could reside above 4GB we'll 599 * have to use 64-bit arithmetics. 600 */ 601 subs r0, r0, #CORE_MMU_L1_TBL_OFFSET 602 sbc r1, r1, #0 603#endif 604 bic r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 605 write_ttbr0_64bit r0, r1 606 isb 607 608#else /*!CFG_WITH_LPAE*/ 609 read_contextidr r0 610 tst r0, #1 611 beq 11f 612 613 /* Update the mapping to use the full kernel mode mapping. */ 614 bic r0, r0, #1 615 write_contextidr r0 616 isb 617#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 618 read_ttbr1 r0 619 sub r0, r0, #CORE_MMU_L1_TBL_OFFSET 620 write_ttbr1 r0 621 isb 622#endif 623 624#endif /*!CFG_WITH_LPAE*/ 625 626#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 627 ldr r0, =thread_user_kcode_offset 628 ldr r0, [r0] 629 read_vbar r1 630 add r1, r1, r0 631 write_vbar r1 632 isb 633 634 11: /* 635 * The PC is adjusted unconditionally to guard against the 636 * case there was an FIQ just before we did the "cpsid aif". 637 */ 638 ldr r0, =22f 639 bx r0 640 22: 641#else 642 11: 643#endif 644 read_tpidrprw r0 645#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 646 read_tpidruro r1 647#endif 648 .endm 649 650/* The handler of native interrupt. */ 651.macro native_intr_handler mode:req 652 cpsid aif 653 maybe_restore_mapping 654 655 /* 656 * FIQ and IRQ have a +4 offset for lr compared to preferred return 657 * address 658 */ 659 sub lr, lr, #4 660 661 /* 662 * We're always saving {r0-r3}. In IRQ mode we're saving r12 also. 663 * In FIQ mode we're saving the banked fiq registers {r8-r12} FIQ 664 * because the secure monitor doesn't save those. The treatment of 665 * the banked fiq registers is somewhat analogous to the lazy save 666 * of VFP registers. 667 */ 668 .ifc \mode\(),fiq 669 push {r0-r3, r8-r12, lr} 670 .else 671 push {r0-r3, r12, lr} 672 .endif 673 674 bl thread_check_canaries 675 ldr lr, =thread_nintr_handler_ptr 676 ldr lr, [lr] 677 blx lr 678 679 mrs r0, spsr 680 cmp_spsr_user_mode r0 681 682 .ifc \mode\(),fiq 683 pop {r0-r3, r8-r12, lr} 684 .else 685 pop {r0-r3, r12, lr} 686 .endif 687 688 movnes pc, lr 689 b eret_to_user_mode 690.endm 691 692/* The handler of foreign interrupt. */ 693.macro foreign_intr_handler mode:req 694 cpsid aif 695 maybe_restore_mapping 696 697 sub lr, lr, #4 698 push {lr} 699 push {r12} 700 701 .ifc \mode\(),fiq 702 bl thread_save_state_fiq 703 .else 704 bl thread_save_state 705 .endif 706 707 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 708 mrs r1, spsr 709 pop {r12} 710 pop {r2} 711 blx thread_state_suspend 712 mov r4, r0 /* Supply thread index */ 713 714 /* 715 * Switch to SVC mode and copy current stack pointer as it already 716 * is the tmp stack. 717 */ 718 mov r0, sp 719 cps #CPSR_MODE_SVC 720 mov sp, r0 721 722 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 723 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 724 mov r2, #0 725 mov r3, #0 726 /* r4 is already filled in above */ 727 smc #0 728 b . /* SMC should not return */ 729.endm 730 731 .section .text.thread_excp_vect 732 .align 5 733FUNC thread_excp_vect , : 734UNWIND( .fnstart) 735UNWIND( .cantunwind) 736 b . /* Reset */ 737 b thread_und_handler /* Undefined instruction */ 738 b thread_svc_handler /* System call */ 739 b thread_pabort_handler /* Prefetch abort */ 740 b thread_dabort_handler /* Data abort */ 741 b . /* Reserved */ 742 b thread_irq_handler /* IRQ */ 743 b thread_fiq_handler /* FIQ */ 744#ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 745 .macro vector_prologue_spectre 746 /* 747 * This depends on SP being 8 byte aligned, that is, the 748 * lowest three bits in SP are zero. 749 * 750 * To avoid unexpected speculation we need to invalidate 751 * the branch predictor before we do the first branch. It 752 * doesn't matter if it's a conditional or an unconditional 753 * branch speculation can still occur. 754 * 755 * The idea is to form a specific bit pattern in the lowest 756 * three bits of SP depending on which entry in the vector 757 * we enter via. This is done by adding 1 to SP in each 758 * entry but the last. 759 */ 760 add sp, sp, #1 /* 7:111 Reset */ 761 add sp, sp, #1 /* 6:110 Undefined instruction */ 762 add sp, sp, #1 /* 5:101 Secure monitor call */ 763 add sp, sp, #1 /* 4:100 Prefetch abort */ 764 add sp, sp, #1 /* 3:011 Data abort */ 765 add sp, sp, #1 /* 2:010 Reserved */ 766 add sp, sp, #1 /* 1:001 IRQ */ 767 write_tpidrprw r0 /* 0:000 FIQ */ 768 .endm 769 770 .align 5 771 .global thread_excp_vect_workaround_a15 772thread_excp_vect_workaround_a15: 773 vector_prologue_spectre 774 mrs r0, spsr 775 cmp_spsr_user_mode r0 776 bne 1f 777 /* 778 * Invalidate the branch predictor for the current processor. 779 * For Cortex-A8 ACTLR[6] has to be set to 1 for BPIALL to be 780 * effective. 781 * Note that the BPIALL instruction is not effective in 782 * invalidating the branch predictor on Cortex-A15. For that CPU, 783 * set ACTLR[0] to 1 during early processor initialisation, and 784 * invalidate the branch predictor by performing an ICIALLU 785 * instruction. See also: 786 * https://github.com/ARM-software/arm-trusted-firmware/wiki/Arm-Trusted-Firmware-Security-Advisory-TFV-6#variant-2-cve-2017-5715 787 */ 788 write_iciallu 789 isb 790 b 1f 791 792 .align 5 793 .global thread_excp_vect_workaround 794thread_excp_vect_workaround: 795 vector_prologue_spectre 796 mrs r0, spsr 797 cmp_spsr_user_mode r0 798 bne 1f 799 /* Invalidate the branch predictor for the current processor. */ 800 write_bpiall 801 isb 802 8031: and r0, sp, #(BIT(0) | BIT(1) | BIT(2)) 804 bic sp, sp, #(BIT(0) | BIT(1) | BIT(2)) 805 add pc, pc, r0, LSL #3 806 nop 807 808 read_tpidrprw r0 809 b thread_fiq_handler /* FIQ */ 810 read_tpidrprw r0 811 b thread_irq_handler /* IRQ */ 812 read_tpidrprw r0 813 b . /* Reserved */ 814 read_tpidrprw r0 815 b thread_dabort_handler /* Data abort */ 816 read_tpidrprw r0 817 b thread_pabort_handler /* Prefetch abort */ 818 read_tpidrprw r0 819 b thread_svc_handler /* System call */ 820 read_tpidrprw r0 821 b thread_und_handler /* Undefined instruction */ 822 read_tpidrprw r0 823 b . /* Reset */ 824#endif /*CFG_CORE_WORKAROUND_SPECTRE_BP_SEC*/ 825 826thread_und_handler: 827 cpsid aif 828 maybe_restore_mapping 829 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 830 mrs r1, spsr 831 tst r1, #CPSR_T 832 subne lr, lr, #2 833 subeq lr, lr, #4 834 mov r0, #ABORT_TYPE_UNDEF 835 b thread_abort_common 836 837thread_dabort_handler: 838 cpsid aif 839 maybe_restore_mapping 840 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 841 sub lr, lr, #8 842 mov r0, #ABORT_TYPE_DATA 843 b thread_abort_common 844 845thread_pabort_handler: 846 cpsid aif 847 maybe_restore_mapping 848 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 849 sub lr, lr, #4 850 mov r0, #ABORT_TYPE_PREFETCH 851 852thread_abort_common: 853 /* 854 * At this label: 855 * cpsr is in mode undef or abort 856 * sp is still pointing to struct thread_core_local belonging to 857 * this core. 858 * {r0, r1} are saved in struct thread_core_local pointed to by sp 859 * {r2-r11, ip} are untouched. 860 * r0 holds the first argument for abort_handler() 861 */ 862 863 /* 864 * Update core local flags. 865 * flags = (flags << THREAD_CLF_SAVED_SHIFT) | THREAD_CLF_ABORT; 866 */ 867 ldr r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 868 lsl r1, r1, #THREAD_CLF_SAVED_SHIFT 869 orr r1, r1, #THREAD_CLF_ABORT 870 871 /* 872 * Select stack and update flags accordingly 873 * 874 * Normal case: 875 * If the abort stack is unused select that. 876 * 877 * Fatal error handling: 878 * If we're already using the abort stack as noted by bit 879 * (THREAD_CLF_SAVED_SHIFT + THREAD_CLF_ABORT_SHIFT) in the flags 880 * field we're selecting the temporary stack instead to be able to 881 * make a stack trace of the abort in abort mode. 882 * 883 * r1 is initialized as a temporary stack pointer until we've 884 * switched to system mode. 885 */ 886 tst r1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 887 orrne r1, r1, #THREAD_CLF_TMP /* flags |= THREAD_CLF_TMP; */ 888 str r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 889 ldrne r1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 890 ldreq r1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 891 892 /* 893 * Store registers on stack fitting struct thread_abort_regs 894 * start from the end of the struct 895 * {r2-r11, ip} 896 * Load content of previously saved {r0-r1} and stores 897 * it up to the pad field. 898 * After this is only {usr_sp, usr_lr} missing in the struct 899 */ 900 stmdb r1!, {r2-r11, ip} /* Push on the selected stack */ 901 ldrd r2, r3, [sp, #THREAD_CORE_LOCAL_R0] 902 /* Push the original {r0-r1} on the selected stack */ 903 stmdb r1!, {r2-r3} 904 mrs r3, spsr 905 /* Push {pad, spsr, elr} on the selected stack */ 906 stmdb r1!, {r2, r3, lr} 907 908 cps #CPSR_MODE_SYS 909 str lr, [r1, #-4]! 910 str sp, [r1, #-4]! 911 mov sp, r1 912 913 bl abort_handler 914 915 mov ip, sp 916 ldr sp, [ip], #4 917 ldr lr, [ip], #4 918 919 /* 920 * Even if we entered via CPSR_MODE_UND, we are returning via 921 * CPSR_MODE_ABT. It doesn't matter as lr and spsr are assigned 922 * here. 923 */ 924 cps #CPSR_MODE_ABT 925 ldm ip!, {r0, r1, lr} /* r0 is pad */ 926 msr spsr_fsxc, r1 927 928 /* Update core local flags */ 929 ldr r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 930 lsr r0, r0, #THREAD_CLF_SAVED_SHIFT 931 str r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 932 933 cmp_spsr_user_mode r1 934 ldm ip, {r0-r11, ip} 935 movnes pc, lr 936 b eret_to_user_mode 937 /* end thread_abort_common */ 938 939thread_svc_handler: 940 cpsid aif 941 942 maybe_restore_mapping 943 944 push {r0-r7, lr} 945 mrs r0, spsr 946 push {r0} 947 mov r0, sp 948 bl tee_svc_handler 949 cpsid aif /* In case something was unmasked */ 950 pop {r0} 951 msr spsr_fsxc, r0 952 cmp_spsr_user_mode r0 953 pop {r0-r7, lr} 954 movnes pc, lr 955 b eret_to_user_mode 956 /* end thread_svc_handler */ 957 958thread_fiq_handler: 959#if defined(CFG_ARM_GICV3) 960 foreign_intr_handler fiq 961#else 962 native_intr_handler fiq 963#endif 964 /* end thread_fiq_handler */ 965 966thread_irq_handler: 967#if defined(CFG_ARM_GICV3) 968 native_intr_handler irq 969#else 970 foreign_intr_handler irq 971#endif 972 /* end thread_irq_handler */ 973 974 /* 975 * Returns to user mode. 976 * Expects to be jumped to with lr pointing to the user space 977 * address to jump to and spsr holding the desired cpsr. Async 978 * abort, irq and fiq should be masked. 979 */ 980eret_to_user_mode: 981 write_tpidrprw r0 982#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 983 write_tpidruro r1 984#endif 985 986#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 987 ldr r0, =thread_user_kcode_offset 988 ldr r0, [r0] 989 read_vbar r1 990 sub r1, r1, r0 991 write_vbar r1 992 isb 993 994 /* Jump into the reduced mapping before the full mapping is removed */ 995 ldr r1, =1f 996 sub r1, r1, r0 997 bx r1 9981: 999#endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 1000 1001#ifdef CFG_WITH_LPAE 1002 read_ttbr0_64bit r0, r1 1003#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1004 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 1005#endif 1006 /* switch to user ASID */ 1007 orr r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 1008 write_ttbr0_64bit r0, r1 1009 isb 1010#else /*!CFG_WITH_LPAE*/ 1011#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1012 read_ttbr1 r0 1013 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 1014 write_ttbr1 r0 1015 isb 1016#endif 1017 read_contextidr r0 1018 orr r0, r0, #BIT(0) 1019 write_contextidr r0 1020 isb 1021#endif /*!CFG_WITH_LPAE*/ 1022 1023 read_tpidrprw r0 1024#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 1025 read_tpidruro r1 1026#endif 1027 1028 movs pc, lr 1029UNWIND( .fnend) 1030END_FUNC thread_excp_vect 1031