1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <arm32_macros.S> 31#include <arm.h> 32#include <asm.S> 33#include <generated/asm-defines.h> 34#include <keep.h> 35#include <kernel/abort.h> 36#include <kernel/thread_defs.h> 37#include <kernel/unwind.h> 38#include <mm/core_mmu.h> 39#include <sm/optee_smc.h> 40#include <sm/teesmc_opteed.h> 41#include <sm/teesmc_opteed_macros.h> 42 43#include "thread_private.h" 44 45 .macro cmp_spsr_user_mode reg:req 46 /* 47 * We're only testing the lower 4 bits as bit 5 (0x10) 48 * always is set. 49 */ 50 tst \reg, #0x0f 51 .endm 52 53LOCAL_FUNC vector_std_smc_entry , : 54UNWIND( .fnstart) 55UNWIND( .cantunwind) 56 push {r0-r7} 57 mov r0, sp 58 bl thread_handle_std_smc 59 /* 60 * Normally thread_handle_std_smc() should return via 61 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 62 * hasn't switched stack (error detected) it will do a normal "C" 63 * return. 64 */ 65 pop {r1-r8} 66 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 67 smc #0 68 b . /* SMC should not return */ 69UNWIND( .fnend) 70END_FUNC vector_std_smc_entry 71 72LOCAL_FUNC vector_fast_smc_entry , : 73UNWIND( .fnstart) 74UNWIND( .cantunwind) 75 push {r0-r7} 76 mov r0, sp 77 bl thread_handle_fast_smc 78 pop {r1-r8} 79 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 80 smc #0 81 b . /* SMC should not return */ 82UNWIND( .fnend) 83END_FUNC vector_fast_smc_entry 84 85LOCAL_FUNC vector_fiq_entry , : 86UNWIND( .fnstart) 87UNWIND( .cantunwind) 88 /* Secure Monitor received a FIQ and passed control to us. */ 89 bl thread_check_canaries 90 ldr lr, =thread_nintr_handler_ptr 91 ldr lr, [lr] 92 blx lr 93 mov r1, r0 94 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 95 smc #0 96 b . /* SMC should not return */ 97UNWIND( .fnend) 98END_FUNC vector_fiq_entry 99 100LOCAL_FUNC vector_cpu_on_entry , : 101UNWIND( .fnstart) 102UNWIND( .cantunwind) 103 ldr lr, =thread_cpu_on_handler_ptr 104 ldr lr, [lr] 105 blx lr 106 mov r1, r0 107 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 108 smc #0 109 b . /* SMC should not return */ 110UNWIND( .fnend) 111END_FUNC vector_cpu_on_entry 112 113LOCAL_FUNC vector_cpu_off_entry , : 114UNWIND( .fnstart) 115UNWIND( .cantunwind) 116 ldr lr, =thread_cpu_off_handler_ptr 117 ldr lr, [lr] 118 blx lr 119 mov r1, r0 120 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 121 smc #0 122 b . /* SMC should not return */ 123UNWIND( .fnend) 124END_FUNC vector_cpu_off_entry 125 126LOCAL_FUNC vector_cpu_suspend_entry , : 127UNWIND( .fnstart) 128UNWIND( .cantunwind) 129 ldr lr, =thread_cpu_suspend_handler_ptr 130 ldr lr, [lr] 131 blx lr 132 mov r1, r0 133 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 134 smc #0 135 b . /* SMC should not return */ 136UNWIND( .fnend) 137END_FUNC vector_cpu_suspend_entry 138 139LOCAL_FUNC vector_cpu_resume_entry , : 140UNWIND( .fnstart) 141UNWIND( .cantunwind) 142 ldr lr, =thread_cpu_resume_handler_ptr 143 ldr lr, [lr] 144 blx lr 145 mov r1, r0 146 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 147 smc #0 148 b . /* SMC should not return */ 149UNWIND( .fnend) 150END_FUNC vector_cpu_resume_entry 151 152LOCAL_FUNC vector_system_off_entry , : 153UNWIND( .fnstart) 154UNWIND( .cantunwind) 155 ldr lr, =thread_system_off_handler_ptr 156 ldr lr, [lr] 157 blx lr 158 mov r1, r0 159 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 160 smc #0 161 b . /* SMC should not return */ 162UNWIND( .fnend) 163END_FUNC vector_system_off_entry 164 165LOCAL_FUNC vector_system_reset_entry , : 166UNWIND( .fnstart) 167UNWIND( .cantunwind) 168 ldr lr, =thread_system_reset_handler_ptr 169 ldr lr, [lr] 170 blx lr 171 mov r1, r0 172 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 173 smc #0 174 b . /* SMC should not return */ 175UNWIND( .fnend) 176END_FUNC vector_system_reset_entry 177 178/* 179 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 180 * initialization. Also used when compiled with the internal monitor, but 181 * the cpu_*_entry and system_*_entry are not used then. 182 * 183 * Note that ARM-TF depends on the layout of this vector table, any change 184 * in layout has to be synced with ARM-TF. 185 */ 186FUNC thread_vector_table , : 187UNWIND( .fnstart) 188UNWIND( .cantunwind) 189 b vector_std_smc_entry 190 b vector_fast_smc_entry 191 b vector_cpu_on_entry 192 b vector_cpu_off_entry 193 b vector_cpu_resume_entry 194 b vector_cpu_suspend_entry 195 b vector_fiq_entry 196 b vector_system_off_entry 197 b vector_system_reset_entry 198UNWIND( .fnend) 199END_FUNC thread_vector_table 200KEEP_PAGER thread_vector_table 201 202FUNC thread_set_abt_sp , : 203UNWIND( .fnstart) 204UNWIND( .cantunwind) 205 mrs r1, cpsr 206 cps #CPSR_MODE_ABT 207 mov sp, r0 208 msr cpsr, r1 209 bx lr 210UNWIND( .fnend) 211END_FUNC thread_set_abt_sp 212 213FUNC thread_set_und_sp , : 214UNWIND( .fnstart) 215UNWIND( .cantunwind) 216 mrs r1, cpsr 217 cps #CPSR_MODE_UND 218 mov sp, r0 219 msr cpsr, r1 220 bx lr 221UNWIND( .fnend) 222END_FUNC thread_set_und_sp 223 224FUNC thread_set_irq_sp , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 mrs r1, cpsr 228 cps #CPSR_MODE_IRQ 229 mov sp, r0 230 msr cpsr, r1 231 bx lr 232UNWIND( .fnend) 233END_FUNC thread_set_irq_sp 234 235FUNC thread_set_fiq_sp , : 236UNWIND( .fnstart) 237UNWIND( .cantunwind) 238 mrs r1, cpsr 239 cps #CPSR_MODE_FIQ 240 mov sp, r0 241 msr cpsr, r1 242 bx lr 243UNWIND( .fnend) 244END_FUNC thread_set_fiq_sp 245 246/* void thread_resume(struct thread_ctx_regs *regs) */ 247FUNC thread_resume , : 248UNWIND( .fnstart) 249UNWIND( .cantunwind) 250 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 251 252 cps #CPSR_MODE_SYS 253 ldm r12!, {sp, lr} 254 255 cps #CPSR_MODE_SVC 256 ldm r12!, {r1, sp, lr} 257 msr spsr_fsxc, r1 258 259 ldm r12, {r1, r2} 260 261 /* 262 * Switching to some other mode than SVC as we need to set spsr in 263 * order to return into the old state properly and it may be SVC 264 * mode we're returning to. 265 */ 266 cps #CPSR_MODE_ABT 267 cmp_spsr_user_mode r2 268 mov lr, r1 269 msr spsr_fsxc, r2 270 ldm r0, {r0-r12} 271 movnes pc, lr 272 b eret_to_user_mode 273UNWIND( .fnend) 274END_FUNC thread_resume 275 276/* 277 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 278 * the banked r8-r12 registers, returns original CPSR. 279 */ 280LOCAL_FUNC thread_save_state_fiq , : 281UNWIND( .fnstart) 282UNWIND( .cantunwind) 283 mov r9, lr 284 285 /* 286 * Uses stack for temporary storage, while storing needed 287 * context in the thread context struct. 288 */ 289 290 mrs r8, cpsr 291 292 cpsid aif /* Disable Async abort, IRQ and FIQ */ 293 294 push {r4-r7} 295 push {r0-r3} 296 297 mrs r6, cpsr /* Save current CPSR */ 298 299 bl thread_get_ctx_regs 300 301 pop {r1-r4} /* r0-r3 pushed above */ 302 stm r0!, {r1-r4} 303 pop {r1-r4} /* r4-r7 pushed above */ 304 stm r0!, {r1-r4} 305 306 cps #CPSR_MODE_SYS 307 stm r0!, {r8-r12} 308 stm r0!, {sp, lr} 309 310 cps #CPSR_MODE_SVC 311 mrs r1, spsr 312 stm r0!, {r1, sp, lr} 313 314 /* back to fiq mode */ 315 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 316 msr cpsr, r6 /* Restore mode */ 317 318 mov r0, r8 /* Return original CPSR */ 319 bx r9 320UNWIND( .fnend) 321END_FUNC thread_save_state_fiq 322 323/* 324 * Disables IRQ and FIQ and saves state of thread, returns original 325 * CPSR. 326 */ 327LOCAL_FUNC thread_save_state , : 328UNWIND( .fnstart) 329UNWIND( .cantunwind) 330 push {r12, lr} 331 /* 332 * Uses stack for temporary storage, while storing needed 333 * context in the thread context struct. 334 */ 335 336 mrs r12, cpsr 337 338 cpsid aif /* Disable Async abort, IRQ and FIQ */ 339 340 push {r4-r7} 341 push {r0-r3} 342 343 mov r5, r12 /* Save CPSR in a preserved register */ 344 mrs r6, cpsr /* Save current CPSR */ 345 346 bl thread_get_ctx_regs 347 348 pop {r1-r4} /* r0-r3 pushed above */ 349 stm r0!, {r1-r4} 350 pop {r1-r4} /* r4-r7 pushed above */ 351 stm r0!, {r1-r4} 352 stm r0!, {r8-r11} 353 354 pop {r12, lr} 355 stm r0!, {r12} 356 357 cps #CPSR_MODE_SYS 358 stm r0!, {sp, lr} 359 360 cps #CPSR_MODE_SVC 361 mrs r1, spsr 362 stm r0!, {r1, sp, lr} 363 364 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 365 msr cpsr, r6 /* Restore mode */ 366 367 mov r0, r5 /* Return original CPSR */ 368 bx lr 369UNWIND( .fnend) 370END_FUNC thread_save_state 371 372FUNC thread_std_smc_entry , : 373UNWIND( .fnstart) 374UNWIND( .cantunwind) 375 /* Pass r0-r7 in a struct thread_smc_args */ 376 push {r0-r7} 377 mov r0, sp 378 bl __thread_std_smc_entry 379 /* 380 * Load the returned r0-r3 into preserved registers and skip the 381 * "returned" r4-r7 since they will not be returned to normal 382 * world. 383 */ 384 pop {r4-r7} 385 add sp, #(4 * 4) 386 387 /* Disable interrupts before switching to temporary stack */ 388 cpsid aif 389 bl thread_get_tmp_sp 390 mov sp, r0 391 392 bl thread_state_free 393 394 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 395 mov r1, r4 396 mov r2, r5 397 mov r3, r6 398 mov r4, r7 399 smc #0 400 b . /* SMC should not return */ 401UNWIND( .fnend) 402END_FUNC thread_std_smc_entry 403 404 405/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 406FUNC thread_rpc , : 407/* 408 * r0-r2 are used to pass parameters to normal world 409 * r0-r5 are used to pass return vaule back from normal world 410 * 411 * note that r3 is used to pass "resume information", that is, which 412 * thread it is that should resume. 413 * 414 * Since the this function is following AAPCS we need to preserve r4-r5 415 * which are otherwise modified when returning back from normal world. 416 */ 417UNWIND( .fnstart) 418 push {r4-r5, lr} 419UNWIND( .save {r4-r5, lr}) 420 push {r0} 421UNWIND( .save {r0}) 422 423 bl thread_save_state 424 mov r4, r0 /* Save original CPSR */ 425 426 /* 427 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 428 */ 429 bl thread_get_tmp_sp 430 ldr r5, [sp] /* Get pointer to rv[] */ 431 cps #CPSR_MODE_SVC /* Change to SVC mode */ 432 mov sp, r0 /* Switch to tmp stack */ 433 434 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 435 mov r1, r4 /* CPSR to restore */ 436 ldr r2, =.thread_rpc_return 437 bl thread_state_suspend 438 mov r4, r0 /* Supply thread index */ 439 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 440 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 441 smc #0 442 b . /* SMC should not return */ 443 444.thread_rpc_return: 445 /* 446 * At this point has the stack pointer been restored to the value 447 * it had when thread_save_state() was called above. 448 * 449 * Jumps here from thread_resume above when RPC has returned. The 450 * IRQ and FIQ bits are restored to what they where when this 451 * function was originally entered. 452 */ 453 pop {r12} /* Get pointer to rv[] */ 454 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 455 pop {r4-r5, pc} 456UNWIND( .fnend) 457END_FUNC thread_rpc 458KEEP_PAGER thread_rpc 459 460/* 461 * unsigned long thread_smc(unsigned long func_id, unsigned long a1, 462 * unsigned long a2, unsigned long a3) 463 */ 464FUNC thread_smc , : 465UNWIND( .fnstart) 466 smc #0 467 bx lr 468UNWIND( .fnend) 469END_FUNC thread_smc 470 471FUNC thread_init_vbar , : 472UNWIND( .fnstart) 473 /* Set vector (VBAR) */ 474 write_vbar r0 475 bx lr 476UNWIND( .fnend) 477END_FUNC thread_init_vbar 478KEEP_PAGER thread_init_vbar 479 480/* 481 * Below are low level routines handling entry and return from user mode. 482 * 483 * thread_enter_user_mode() saves all that registers user mode can change 484 * so kernel mode can restore needed registers when resuming execution 485 * after the call to thread_enter_user_mode() has returned. 486 * thread_enter_user_mode() doesn't return directly since it enters user 487 * mode instead, it's thread_unwind_user_mode() that does the 488 * returning by restoring the registers saved by thread_enter_user_mode(). 489 * 490 * There's three ways for thread_enter_user_mode() to return to caller, 491 * user TA calls utee_return, user TA calls utee_panic or through an abort. 492 * 493 * Calls to utee_return or utee_panic are handled as: 494 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 495 * calls syscall_return() or syscall_panic(). 496 * 497 * These function calls returns normally except thread_svc_handler() which 498 * which is an exception handling routine so it reads return address and 499 * SPSR to restore from the stack. syscall_return() and syscall_panic() 500 * changes return address and SPSR used by thread_svc_handler() to instead of 501 * returning into user mode as with other syscalls it returns into 502 * thread_unwind_user_mode() in kernel mode instead. When 503 * thread_svc_handler() returns the stack pointer at the point where 504 * thread_enter_user_mode() left it so this is where 505 * thread_unwind_user_mode() can operate. 506 * 507 * Aborts are handled in a similar way but by thread_abort_handler() 508 * instead, when the pager sees that it's an abort from user mode that 509 * can't be handled it updates SPSR and return address used by 510 * thread_abort_handler() to return into thread_unwind_user_mode() 511 * instead. 512 */ 513 514/* 515 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 516 * unsigned long a2, unsigned long a3, unsigned long user_sp, 517 * unsigned long user_func, unsigned long spsr, 518 * uint32_t *exit_status0, uint32_t *exit_status1) 519 * 520 */ 521FUNC __thread_enter_user_mode , : 522UNWIND( .fnstart) 523UNWIND( .cantunwind) 524 /* 525 * Save all registers to allow syscall_return() to resume execution 526 * as if this function would have returned. This is also used in 527 * syscall_panic(). 528 * 529 * If stack usage of this function is changed 530 * thread_unwind_user_mode() has to be updated. 531 */ 532 push {r4-r12,lr} 533 534 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 535 ldr r5, [sp, #(11 * 0x4)] /* user function */ 536 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 537 538 /* 539 * Save old user sp and set new user sp. 540 */ 541 cps #CPSR_MODE_SYS 542 mov r7, sp 543 mov sp, r4 544 cps #CPSR_MODE_SVC 545 push {r7,r8} 546 547 /* Prepare user mode entry via eret_to_user_mode */ 548 cpsid aif 549 msr spsr_fsxc, r6 550 mov lr, r5 551 552 b eret_to_user_mode 553UNWIND( .fnend) 554END_FUNC __thread_enter_user_mode 555 556/* 557 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 558 * uint32_t exit_status1); 559 * See description in thread.h 560 */ 561FUNC thread_unwind_user_mode , : 562UNWIND( .fnstart) 563UNWIND( .cantunwind) 564 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 565 str r1, [ip] 566 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 567 str r2, [ip] 568 569 /* Restore old user sp */ 570 pop {r4,r7} 571 cps #CPSR_MODE_SYS 572 mov sp, r4 573 cps #CPSR_MODE_SVC 574 575 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 576UNWIND( .fnend) 577END_FUNC thread_unwind_user_mode 578 579 .macro maybe_restore_mapping 580 /* 581 * This macro is a bit hard to read due to all the ifdefs, 582 * we're testing for two different configs which makes four 583 * different combinations. 584 * 585 * - With LPAE, and then some extra code if with 586 * CFG_CORE_UNMAP_CORE_AT_EL0 587 * - Without LPAE, and then some extra code if with 588 * CFG_CORE_UNMAP_CORE_AT_EL0 589 */ 590 591 /* 592 * At this point we can't rely on any memory being writable 593 * yet, so we're using TPIDRPRW to store r0, and if with 594 * LPAE TPIDRURO to store r1 too. 595 */ 596 write_tpidrprw r0 597#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 598 write_tpidruro r1 599#endif 600 601#ifdef CFG_WITH_LPAE 602 read_ttbr0_64bit r0, r1 603 tst r1, #BIT(TTBR_ASID_SHIFT - 32) 604 beq 11f 605 606#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 607 /* 608 * Update the mapping to use the full kernel mode mapping. 609 * Since the translation table could reside above 4GB we'll 610 * have to use 64-bit arithmetics. 611 */ 612 subs r0, r0, #CORE_MMU_L1_TBL_OFFSET 613 sbc r1, r1, #0 614#endif 615 bic r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 616 write_ttbr0_64bit r0, r1 617 isb 618 619#else /*!CFG_WITH_LPAE*/ 620 read_contextidr r0 621 tst r0, #1 622 beq 11f 623 624 /* Update the mapping to use the full kernel mode mapping. */ 625 bic r0, r0, #1 626 write_contextidr r0 627 isb 628#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 629 read_ttbr1 r0 630 sub r0, r0, #CORE_MMU_L1_TBL_OFFSET 631 write_ttbr1 r0 632 isb 633#endif 634 635#endif /*!CFG_WITH_LPAE*/ 636 637#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 638 ldr r0, =thread_user_kcode_offset 639 ldr r0, [r0] 640 read_vbar r1 641 add r1, r1, r0 642 write_vbar r1 643 isb 644 645 11: /* 646 * The PC is adjusted unconditionally to guard against the 647 * case there was an FIQ just before we did the "cpsid aif". 648 */ 649 ldr r0, =22f 650 bx r0 651 22: 652#else 653 11: 654#endif 655 read_tpidrprw r0 656#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 657 read_tpidruro r1 658#endif 659 .endm 660 661/* The handler of native interrupt. */ 662.macro native_intr_handler mode:req 663 cpsid aif 664 maybe_restore_mapping 665 666 /* 667 * FIQ and IRQ have a +4 offset for lr compared to preferred return 668 * address 669 */ 670 sub lr, lr, #4 671 672 /* 673 * We're always saving {r0-r3}. In IRQ mode we're saving r12 also. 674 * In FIQ mode we're saving the banked fiq registers {r8-r12} FIQ 675 * because the secure monitor doesn't save those. The treatment of 676 * the banked fiq registers is somewhat analogous to the lazy save 677 * of VFP registers. 678 */ 679 .ifc \mode\(),fiq 680 push {r0-r3, r8-r12, lr} 681 .else 682 push {r0-r3, r12, lr} 683 .endif 684 685 bl thread_check_canaries 686 ldr lr, =thread_nintr_handler_ptr 687 ldr lr, [lr] 688 blx lr 689 690 mrs r0, spsr 691 cmp_spsr_user_mode r0 692 693 .ifc \mode\(),fiq 694 pop {r0-r3, r8-r12, lr} 695 .else 696 pop {r0-r3, r12, lr} 697 .endif 698 699 movnes pc, lr 700 b eret_to_user_mode 701.endm 702 703/* The handler of foreign interrupt. */ 704.macro foreign_intr_handler mode:req 705 cpsid aif 706 maybe_restore_mapping 707 708 sub lr, lr, #4 709 push {lr} 710 push {r12} 711 712 .ifc \mode\(),fiq 713 bl thread_save_state_fiq 714 .else 715 bl thread_save_state 716 .endif 717 718 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 719 mrs r1, spsr 720 pop {r12} 721 pop {r2} 722 blx thread_state_suspend 723 mov r4, r0 /* Supply thread index */ 724 725 /* 726 * Switch to SVC mode and copy current stack pointer as it already 727 * is the tmp stack. 728 */ 729 mov r0, sp 730 cps #CPSR_MODE_SVC 731 mov sp, r0 732 733 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 734 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 735 mov r2, #0 736 mov r3, #0 737 /* r4 is already filled in above */ 738 smc #0 739 b . /* SMC should not return */ 740.endm 741 742 .section .text.thread_excp_vect 743 .align 5 744FUNC thread_excp_vect , : 745UNWIND( .fnstart) 746UNWIND( .cantunwind) 747 b . /* Reset */ 748 b thread_und_handler /* Undefined instruction */ 749 b thread_svc_handler /* System call */ 750 b thread_pabort_handler /* Prefetch abort */ 751 b thread_dabort_handler /* Data abort */ 752 b . /* Reserved */ 753 b thread_irq_handler /* IRQ */ 754 b thread_fiq_handler /* FIQ */ 755#ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 756 .macro vector_prologue_spectre 757 /* 758 * This depends on SP being 8 byte aligned, that is, the 759 * lowest three bits in SP are zero. 760 * 761 * To avoid unexpected speculation we need to invalidate 762 * the branch predictor before we do the first branch. It 763 * doesn't matter if it's a conditional or an unconditional 764 * branch speculation can still occur. 765 * 766 * The idea is to form a specific bit pattern in the lowest 767 * three bits of SP depending on which entry in the vector 768 * we enter via. This is done by adding 1 to SP in each 769 * entry but the last. 770 */ 771 add sp, sp, #1 /* 7:111 Reset */ 772 add sp, sp, #1 /* 6:110 Undefined instruction */ 773 add sp, sp, #1 /* 5:101 Secure monitor call */ 774 add sp, sp, #1 /* 4:100 Prefetch abort */ 775 add sp, sp, #1 /* 3:011 Data abort */ 776 add sp, sp, #1 /* 2:010 Reserved */ 777 add sp, sp, #1 /* 1:001 IRQ */ 778 write_tpidrprw r0 /* 0:000 FIQ */ 779 .endm 780 781 .align 5 782 .global thread_excp_vect_workaround_a15 783thread_excp_vect_workaround_a15: 784 vector_prologue_spectre 785 mrs r0, spsr 786 cmp_spsr_user_mode r0 787 bne 1f 788 /* 789 * Invalidate the branch predictor for the current processor. 790 * For Cortex-A8 ACTLR[6] has to be set to 1 for BPIALL to be 791 * effective. 792 * Note that the BPIALL instruction is not effective in 793 * invalidating the branch predictor on Cortex-A15. For that CPU, 794 * set ACTLR[0] to 1 during early processor initialisation, and 795 * invalidate the branch predictor by performing an ICIALLU 796 * instruction. See also: 797 * https://github.com/ARM-software/arm-trusted-firmware/wiki/Arm-Trusted-Firmware-Security-Advisory-TFV-6#variant-2-cve-2017-5715 798 */ 799 write_iciallu 800 isb 801 b 1f 802 803 .align 5 804 .global thread_excp_vect_workaround 805thread_excp_vect_workaround: 806 vector_prologue_spectre 807 mrs r0, spsr 808 cmp_spsr_user_mode r0 809 bne 1f 810 /* Invalidate the branch predictor for the current processor. */ 811 write_bpiall 812 isb 813 8141: and r0, sp, #(BIT(0) | BIT(1) | BIT(2)) 815 bic sp, sp, #(BIT(0) | BIT(1) | BIT(2)) 816 add pc, pc, r0, LSL #3 817 nop 818 819 read_tpidrprw r0 820 b thread_fiq_handler /* FIQ */ 821 read_tpidrprw r0 822 b thread_irq_handler /* IRQ */ 823 read_tpidrprw r0 824 b . /* Reserved */ 825 read_tpidrprw r0 826 b thread_dabort_handler /* Data abort */ 827 read_tpidrprw r0 828 b thread_pabort_handler /* Prefetch abort */ 829 read_tpidrprw r0 830 b thread_svc_handler /* System call */ 831 read_tpidrprw r0 832 b thread_und_handler /* Undefined instruction */ 833 read_tpidrprw r0 834 b . /* Reset */ 835#endif /*CFG_CORE_WORKAROUND_SPECTRE_BP_SEC*/ 836 837thread_und_handler: 838 cpsid aif 839 maybe_restore_mapping 840 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 841 mrs r1, spsr 842 tst r1, #CPSR_T 843 subne lr, lr, #2 844 subeq lr, lr, #4 845 mov r0, #ABORT_TYPE_UNDEF 846 b thread_abort_common 847 848thread_dabort_handler: 849 cpsid aif 850 maybe_restore_mapping 851 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 852 sub lr, lr, #8 853 mov r0, #ABORT_TYPE_DATA 854 b thread_abort_common 855 856thread_pabort_handler: 857 cpsid aif 858 maybe_restore_mapping 859 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 860 sub lr, lr, #4 861 mov r0, #ABORT_TYPE_PREFETCH 862 863thread_abort_common: 864 /* 865 * At this label: 866 * cpsr is in mode undef or abort 867 * sp is still pointing to struct thread_core_local belonging to 868 * this core. 869 * {r0, r1} are saved in struct thread_core_local pointed to by sp 870 * {r2-r11, ip} are untouched. 871 * r0 holds the first argument for abort_handler() 872 */ 873 874 /* 875 * Update core local flags. 876 * flags = (flags << THREAD_CLF_SAVED_SHIFT) | THREAD_CLF_ABORT; 877 */ 878 ldr r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 879 lsl r1, r1, #THREAD_CLF_SAVED_SHIFT 880 orr r1, r1, #THREAD_CLF_ABORT 881 882 /* 883 * Select stack and update flags accordingly 884 * 885 * Normal case: 886 * If the abort stack is unused select that. 887 * 888 * Fatal error handling: 889 * If we're already using the abort stack as noted by bit 890 * (THREAD_CLF_SAVED_SHIFT + THREAD_CLF_ABORT_SHIFT) in the flags 891 * field we're selecting the temporary stack instead to be able to 892 * make a stack trace of the abort in abort mode. 893 * 894 * r1 is initialized as a temporary stack pointer until we've 895 * switched to system mode. 896 */ 897 tst r1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 898 orrne r1, r1, #THREAD_CLF_TMP /* flags |= THREAD_CLF_TMP; */ 899 str r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 900 ldrne r1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 901 ldreq r1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 902 903 /* 904 * Store registers on stack fitting struct thread_abort_regs 905 * start from the end of the struct 906 * {r2-r11, ip} 907 * Load content of previously saved {r0-r1} and stores 908 * it up to the pad field. 909 * After this is only {usr_sp, usr_lr} missing in the struct 910 */ 911 stmdb r1!, {r2-r11, ip} /* Push on the selected stack */ 912 ldrd r2, r3, [sp, #THREAD_CORE_LOCAL_R0] 913 /* Push the original {r0-r1} on the selected stack */ 914 stmdb r1!, {r2-r3} 915 mrs r3, spsr 916 /* Push {pad, spsr, elr} on the selected stack */ 917 stmdb r1!, {r2, r3, lr} 918 919 cps #CPSR_MODE_SYS 920 str lr, [r1, #-4]! 921 str sp, [r1, #-4]! 922 mov sp, r1 923 924 bl abort_handler 925 926 mov ip, sp 927 ldr sp, [ip], #4 928 ldr lr, [ip], #4 929 930 /* 931 * Even if we entered via CPSR_MODE_UND, we are returning via 932 * CPSR_MODE_ABT. It doesn't matter as lr and spsr are assigned 933 * here. 934 */ 935 cps #CPSR_MODE_ABT 936 ldm ip!, {r0, r1, lr} /* r0 is pad */ 937 msr spsr_fsxc, r1 938 939 /* Update core local flags */ 940 ldr r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 941 lsr r0, r0, #THREAD_CLF_SAVED_SHIFT 942 str r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 943 944 cmp_spsr_user_mode r1 945 ldm ip, {r0-r11, ip} 946 movnes pc, lr 947 b eret_to_user_mode 948 /* end thread_abort_common */ 949 950thread_svc_handler: 951 cpsid aif 952 953 maybe_restore_mapping 954 955 push {r0-r7, lr} 956 mrs r0, spsr 957 push {r0} 958 mov r0, sp 959 bl tee_svc_handler 960 cpsid aif /* In case something was unmasked */ 961 pop {r0} 962 msr spsr_fsxc, r0 963 cmp_spsr_user_mode r0 964 pop {r0-r7, lr} 965 movnes pc, lr 966 b eret_to_user_mode 967 /* end thread_svc_handler */ 968 969thread_fiq_handler: 970#if defined(CFG_ARM_GICV3) 971 foreign_intr_handler fiq 972#else 973 native_intr_handler fiq 974#endif 975 /* end thread_fiq_handler */ 976 977thread_irq_handler: 978#if defined(CFG_ARM_GICV3) 979 native_intr_handler irq 980#else 981 foreign_intr_handler irq 982#endif 983 /* end thread_irq_handler */ 984 985 /* 986 * Returns to user mode. 987 * Expects to be jumped to with lr pointing to the user space 988 * address to jump to and spsr holding the desired cpsr. Async 989 * abort, irq and fiq should be masked. 990 */ 991eret_to_user_mode: 992 write_tpidrprw r0 993#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 994 write_tpidruro r1 995#endif 996 997#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 998 ldr r0, =thread_user_kcode_offset 999 ldr r0, [r0] 1000 read_vbar r1 1001 sub r1, r1, r0 1002 write_vbar r1 1003 isb 1004 1005 /* Jump into the reduced mapping before the full mapping is removed */ 1006 ldr r1, =1f 1007 sub r1, r1, r0 1008 bx r1 10091: 1010#endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 1011 1012#ifdef CFG_WITH_LPAE 1013 read_ttbr0_64bit r0, r1 1014#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1015 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 1016#endif 1017 /* switch to user ASID */ 1018 orr r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 1019 write_ttbr0_64bit r0, r1 1020 isb 1021#else /*!CFG_WITH_LPAE*/ 1022#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1023 read_ttbr1 r0 1024 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 1025 write_ttbr1 r0 1026 isb 1027#endif 1028 read_contextidr r0 1029 orr r0, r0, #BIT(0) 1030 write_contextidr r0 1031 isb 1032#endif /*!CFG_WITH_LPAE*/ 1033 1034 read_tpidrprw r0 1035#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 1036 read_tpidruro r1 1037#endif 1038 1039 movs pc, lr 1040UNWIND( .fnend) 1041 .global thread_excp_vect_end 1042thread_excp_vect_end: 1043END_FUNC thread_excp_vect 1044