1/* 2 * Copyright (c) 2016-2017, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <arm32_macros.S> 30#include <arm.h> 31#include <asm.S> 32#include <keep.h> 33#include <kernel/abort.h> 34#include <kernel/thread_defs.h> 35#include <kernel/unwind.h> 36#include <sm/optee_smc.h> 37#include <sm/teesmc_opteed.h> 38#include <sm/teesmc_opteed_macros.h> 39 40 .section .text.thread_asm 41 42LOCAL_FUNC vector_std_smc_entry , : 43UNWIND( .fnstart) 44UNWIND( .cantunwind) 45 push {r0-r7} 46 mov r0, sp 47 bl thread_handle_std_smc 48 /* 49 * Normally thread_handle_std_smc() should return via 50 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 51 * hasn't switched stack (error detected) it will do a normal "C" 52 * return. 53 */ 54 pop {r1-r8} 55 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 56 smc #0 57 b . /* SMC should not return */ 58UNWIND( .fnend) 59END_FUNC vector_std_smc_entry 60 61LOCAL_FUNC vector_fast_smc_entry , : 62UNWIND( .fnstart) 63UNWIND( .cantunwind) 64 push {r0-r7} 65 mov r0, sp 66 bl thread_handle_fast_smc 67 pop {r1-r8} 68 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 69 smc #0 70 b . /* SMC should not return */ 71UNWIND( .fnend) 72END_FUNC vector_fast_smc_entry 73 74LOCAL_FUNC vector_fiq_entry , : 75UNWIND( .fnstart) 76UNWIND( .cantunwind) 77 /* Secure Monitor received a FIQ and passed control to us. */ 78 bl thread_check_canaries 79 ldr lr, =thread_nintr_handler_ptr 80 ldr lr, [lr] 81 blx lr 82 mov r1, r0 83 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 84 smc #0 85 b . /* SMC should not return */ 86UNWIND( .fnend) 87END_FUNC vector_fiq_entry 88 89LOCAL_FUNC vector_cpu_on_entry , : 90UNWIND( .fnstart) 91UNWIND( .cantunwind) 92 ldr lr, =thread_cpu_on_handler_ptr 93 ldr lr, [lr] 94 blx lr 95 mov r1, r0 96 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 97 smc #0 98 b . /* SMC should not return */ 99UNWIND( .fnend) 100END_FUNC vector_cpu_on_entry 101 102LOCAL_FUNC vector_cpu_off_entry , : 103UNWIND( .fnstart) 104UNWIND( .cantunwind) 105 ldr lr, =thread_cpu_off_handler_ptr 106 ldr lr, [lr] 107 blx lr 108 mov r1, r0 109 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 110 smc #0 111 b . /* SMC should not return */ 112UNWIND( .fnend) 113END_FUNC vector_cpu_off_entry 114 115LOCAL_FUNC vector_cpu_suspend_entry , : 116UNWIND( .fnstart) 117UNWIND( .cantunwind) 118 ldr lr, =thread_cpu_suspend_handler_ptr 119 ldr lr, [lr] 120 blx lr 121 mov r1, r0 122 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 123 smc #0 124 b . /* SMC should not return */ 125UNWIND( .fnend) 126END_FUNC vector_cpu_suspend_entry 127 128LOCAL_FUNC vector_cpu_resume_entry , : 129UNWIND( .fnstart) 130UNWIND( .cantunwind) 131 ldr lr, =thread_cpu_resume_handler_ptr 132 ldr lr, [lr] 133 blx lr 134 mov r1, r0 135 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 136 smc #0 137 b . /* SMC should not return */ 138UNWIND( .fnend) 139END_FUNC vector_cpu_resume_entry 140 141LOCAL_FUNC vector_system_off_entry , : 142UNWIND( .fnstart) 143UNWIND( .cantunwind) 144 ldr lr, =thread_system_off_handler_ptr 145 ldr lr, [lr] 146 blx lr 147 mov r1, r0 148 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 149 smc #0 150 b . /* SMC should not return */ 151UNWIND( .fnend) 152END_FUNC vector_system_off_entry 153 154LOCAL_FUNC vector_system_reset_entry , : 155UNWIND( .fnstart) 156UNWIND( .cantunwind) 157 ldr lr, =thread_system_reset_handler_ptr 158 ldr lr, [lr] 159 blx lr 160 mov r1, r0 161 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 162 smc #0 163 b . /* SMC should not return */ 164UNWIND( .fnend) 165END_FUNC vector_system_reset_entry 166 167/* 168 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 169 * initialization. Also used when compiled with the internal monitor, but 170 * the cpu_*_entry and system_*_entry are not used then. 171 * 172 * Note that ARM-TF depends on the layout of this vector table, any change 173 * in layout has to be synced with ARM-TF. 174 */ 175FUNC thread_vector_table , : 176UNWIND( .fnstart) 177UNWIND( .cantunwind) 178 b vector_std_smc_entry 179 b vector_fast_smc_entry 180 b vector_cpu_on_entry 181 b vector_cpu_off_entry 182 b vector_cpu_resume_entry 183 b vector_cpu_suspend_entry 184 b vector_fiq_entry 185 b vector_system_off_entry 186 b vector_system_reset_entry 187UNWIND( .fnend) 188END_FUNC thread_vector_table 189 190FUNC thread_set_abt_sp , : 191UNWIND( .fnstart) 192UNWIND( .cantunwind) 193 mrs r1, cpsr 194 cps #CPSR_MODE_ABT 195 mov sp, r0 196 msr cpsr, r1 197 bx lr 198UNWIND( .fnend) 199END_FUNC thread_set_abt_sp 200 201FUNC thread_set_irq_sp , : 202UNWIND( .fnstart) 203UNWIND( .cantunwind) 204 mrs r1, cpsr 205 cps #CPSR_MODE_IRQ 206 mov sp, r0 207 msr cpsr, r1 208 bx lr 209UNWIND( .fnend) 210END_FUNC thread_set_irq_sp 211 212FUNC thread_set_fiq_sp , : 213UNWIND( .fnstart) 214UNWIND( .cantunwind) 215 mrs r1, cpsr 216 cps #CPSR_MODE_FIQ 217 mov sp, r0 218 msr cpsr, r1 219 bx lr 220UNWIND( .fnend) 221END_FUNC thread_set_fiq_sp 222 223/* void thread_resume(struct thread_ctx_regs *regs) */ 224FUNC thread_resume , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 228 229 cps #CPSR_MODE_SYS 230 ldm r12!, {sp, lr} 231 232 cps #CPSR_MODE_SVC 233 ldm r12!, {r1, sp, lr} 234 msr spsr_fsxc, r1 235 236 cps #CPSR_MODE_SVC 237 ldm r12, {r1, r2} 238 push {r1, r2} 239 240 ldm r0, {r0-r12} 241 242 /* Restore CPSR and jump to the instruction to resume at */ 243 rfefd sp! 244UNWIND( .fnend) 245END_FUNC thread_resume 246 247/* 248 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 249 * the banked r8-r12 registers, returns original CPSR. 250 */ 251LOCAL_FUNC thread_save_state_fiq , : 252UNWIND( .fnstart) 253UNWIND( .cantunwind) 254 mov r9, lr 255 256 /* 257 * Uses stack for temporary storage, while storing needed 258 * context in the thread context struct. 259 */ 260 261 mrs r8, cpsr 262 263 cpsid aif /* Disable Async abort, IRQ and FIQ */ 264 265 push {r4-r7} 266 push {r0-r3} 267 268 mrs r6, cpsr /* Save current CPSR */ 269 270 bl thread_get_ctx_regs 271 272 pop {r1-r4} /* r0-r3 pushed above */ 273 stm r0!, {r1-r4} 274 pop {r1-r4} /* r4-r7 pushed above */ 275 stm r0!, {r1-r4} 276 277 cps #CPSR_MODE_SYS 278 stm r0!, {r8-r12} 279 stm r0!, {sp, lr} 280 281 cps #CPSR_MODE_SVC 282 mrs r1, spsr 283 stm r0!, {r1, sp, lr} 284 285 /* back to fiq mode */ 286 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 287 msr cpsr, r6 /* Restore mode */ 288 289 mov r0, r8 /* Return original CPSR */ 290 bx r9 291UNWIND( .fnend) 292END_FUNC thread_save_state_fiq 293 294/* 295 * Disables IRQ and FIQ and saves state of thread, returns original 296 * CPSR. 297 */ 298LOCAL_FUNC thread_save_state , : 299UNWIND( .fnstart) 300UNWIND( .cantunwind) 301 push {r12, lr} 302 /* 303 * Uses stack for temporary storage, while storing needed 304 * context in the thread context struct. 305 */ 306 307 mrs r12, cpsr 308 309 cpsid aif /* Disable Async abort, IRQ and FIQ */ 310 311 push {r4-r7} 312 push {r0-r3} 313 314 mov r5, r12 /* Save CPSR in a preserved register */ 315 mrs r6, cpsr /* Save current CPSR */ 316 317 bl thread_get_ctx_regs 318 319 pop {r1-r4} /* r0-r3 pushed above */ 320 stm r0!, {r1-r4} 321 pop {r1-r4} /* r4-r7 pushed above */ 322 stm r0!, {r1-r4} 323 stm r0!, {r8-r11} 324 325 pop {r12, lr} 326 stm r0!, {r12} 327 328 cps #CPSR_MODE_SYS 329 stm r0!, {sp, lr} 330 331 cps #CPSR_MODE_SVC 332 mrs r1, spsr 333 stm r0!, {r1, sp, lr} 334 335 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 336 msr cpsr, r6 /* Restore mode */ 337 338 mov r0, r5 /* Return original CPSR */ 339 bx lr 340UNWIND( .fnend) 341END_FUNC thread_save_state 342 343FUNC thread_std_smc_entry , : 344UNWIND( .fnstart) 345UNWIND( .cantunwind) 346 /* Pass r0-r7 in a struct thread_smc_args */ 347 push {r0-r7} 348 mov r0, sp 349 bl __thread_std_smc_entry 350 /* 351 * Load the returned r0-r3 into preserved registers and skip the 352 * "returned" r4-r7 since they will not be returned to normal 353 * world. 354 */ 355 pop {r4-r7} 356 add sp, #(4 * 4) 357 358 /* Disable interrupts before switching to temporary stack */ 359 cpsid aif 360 bl thread_get_tmp_sp 361 mov sp, r0 362 363 bl thread_state_free 364 365 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 366 mov r1, r4 367 mov r2, r5 368 mov r3, r6 369 mov r4, r7 370 smc #0 371 b . /* SMC should not return */ 372UNWIND( .fnend) 373END_FUNC thread_std_smc_entry 374 375 376/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 377FUNC thread_rpc , : 378/* 379 * r0-r2 are used to pass parameters to normal world 380 * r0-r5 are used to pass return vaule back from normal world 381 * 382 * note that r3 is used to pass "resume information", that is, which 383 * thread it is that should resume. 384 * 385 * Since the this function is following AAPCS we need to preserve r4-r5 386 * which are otherwise modified when returning back from normal world. 387 */ 388UNWIND( .fnstart) 389 push {r4-r5, lr} 390UNWIND( .save {r4-r5, lr}) 391 push {r0} 392UNWIND( .save {r0}) 393 394 bl thread_save_state 395 mov r4, r0 /* Save original CPSR */ 396 397 /* 398 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 399 */ 400 bl thread_get_tmp_sp 401 ldr r5, [sp] /* Get pointer to rv[] */ 402 cps #CPSR_MODE_SVC /* Change to SVC mode */ 403 mov sp, r0 /* Switch to tmp stack */ 404 405 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 406 mov r1, r4 /* CPSR to restore */ 407 ldr r2, =.thread_rpc_return 408 bl thread_state_suspend 409 mov r4, r0 /* Supply thread index */ 410 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 411 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 412 smc #0 413 b . /* SMC should not return */ 414 415.thread_rpc_return: 416 /* 417 * At this point has the stack pointer been restored to the value 418 * it had when thread_save_state() was called above. 419 * 420 * Jumps here from thread_resume above when RPC has returned. The 421 * IRQ and FIQ bits are restored to what they where when this 422 * function was originally entered. 423 */ 424 pop {r12} /* Get pointer to rv[] */ 425 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 426 pop {r4-r5, pc} 427UNWIND( .fnend) 428END_FUNC thread_rpc 429 430/* The handler of native interrupt. */ 431.macro native_intr_handler mode:req 432 /* 433 * FIQ and IRQ have a +4 offset for lr compared to preferred return 434 * address 435 */ 436 sub lr, lr, #4 437 438 /* 439 * We're saving {r0-r3}. The banked fiq registers {r8-r12} need to be 440 * saved if the native interrupt is sent as FIQ because the secure 441 * monitor doesn't save those. The treatment of the banked fiq 442 * registers is somewhat analogous to the lazy save of VFP registers. 443 */ 444 .ifc \mode\(),fiq 445 push {r0-r3, r8-r12, lr} 446 .else 447 push {r0-r3, lr} 448 .endif 449 bl thread_check_canaries 450 ldr lr, =thread_nintr_handler_ptr 451 ldr lr, [lr] 452 blx lr 453 .ifc \mode\(),fiq 454 pop {r0-r3, r8-r12, lr} 455 .else 456 pop {r0-r3, lr} 457 .endif 458 movs pc, lr 459.endm 460 461/* The handler of foreign interrupt. */ 462.macro foreign_intr_handler mode:req 463 .ifc \mode\(),irq 464 /* 465 * Disable FIQ if the foreign interrupt is sent as IRQ. 466 * IRQ mode is set up to use tmp stack so FIQ has to be 467 * disabled before touching the stack. We can also assign 468 * SVC sp from IRQ sp to get SVC mode into the state we 469 * need when doing the SMC below. 470 * If it is sent as FIQ, the IRQ has already been masked by hardware 471 */ 472 cpsid f 473 .endif 474 sub lr, lr, #4 475 push {lr} 476 push {r12} 477 478 .ifc \mode\(),fiq 479 bl thread_save_state_fiq 480 .else 481 bl thread_save_state 482 .endif 483 484 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 485 mrs r1, spsr 486 pop {r12} 487 pop {r2} 488 blx thread_state_suspend 489 mov r4, r0 /* Supply thread index */ 490 491 /* 492 * Switch to SVC mode and copy current stack pointer as it already 493 * is the tmp stack. 494 */ 495 mov r0, sp 496 cps #CPSR_MODE_SVC 497 mov sp, r0 498 499 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 500 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 501 mov r2, #0 502 mov r3, #0 503 /* r4 is already filled in above */ 504 smc #0 505 b . /* SMC should not return */ 506.endm 507 508LOCAL_FUNC thread_fiq_handler , : 509UNWIND( .fnstart) 510UNWIND( .cantunwind) 511#if defined(CFG_ARM_GICV3) 512 foreign_intr_handler fiq 513#else 514 native_intr_handler fiq 515#endif 516UNWIND( .fnend) 517END_FUNC thread_fiq_handler 518 519LOCAL_FUNC thread_irq_handler , : 520UNWIND( .fnstart) 521UNWIND( .cantunwind) 522#if defined(CFG_ARM_GICV3) 523 native_intr_handler irq 524#else 525 foreign_intr_handler irq 526#endif 527UNWIND( .fnend) 528END_FUNC thread_irq_handler 529 530FUNC thread_init_vbar , : 531UNWIND( .fnstart) 532 /* Set vector (VBAR) */ 533 ldr r0, =thread_vect_table 534 write_vbar r0 535 bx lr 536UNWIND( .fnend) 537END_FUNC thread_init_vbar 538KEEP_PAGER thread_init_vbar 539 540/* 541 * Below are low level routines handling entry and return from user mode. 542 * 543 * thread_enter_user_mode() saves all that registers user mode can change 544 * so kernel mode can restore needed registers when resuming execution 545 * after the call to thread_enter_user_mode() has returned. 546 * thread_enter_user_mode() doesn't return directly since it enters user 547 * mode instead, it's thread_unwind_user_mode() that does the 548 * returning by restoring the registers saved by thread_enter_user_mode(). 549 * 550 * There's three ways for thread_enter_user_mode() to return to caller, 551 * user TA calls utee_return, user TA calls utee_panic or through an abort. 552 * 553 * Calls to utee_return or utee_panic are handled as: 554 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 555 * calls syscall_return() or syscall_panic(). 556 * 557 * These function calls returns normally except thread_svc_handler() which 558 * which is an exception handling routine so it reads return address and 559 * SPSR to restore from the stack. syscall_return() and syscall_panic() 560 * changes return address and SPSR used by thread_svc_handler() to instead of 561 * returning into user mode as with other syscalls it returns into 562 * thread_unwind_user_mode() in kernel mode instead. When 563 * thread_svc_handler() returns the stack pointer at the point where 564 * thread_enter_user_mode() left it so this is where 565 * thread_unwind_user_mode() can operate. 566 * 567 * Aborts are handled in a similar way but by thread_abort_handler() 568 * instead, when the pager sees that it's an abort from user mode that 569 * can't be handled it updates SPSR and return address used by 570 * thread_abort_handler() to return into thread_unwind_user_mode() 571 * instead. 572 */ 573 574/* 575 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 576 * unsigned long a2, unsigned long a3, unsigned long user_sp, 577 * unsigned long user_func, unsigned long spsr, 578 * uint32_t *exit_status0, uint32_t *exit_status1) 579 * 580 */ 581FUNC __thread_enter_user_mode , : 582UNWIND( .fnstart) 583UNWIND( .cantunwind) 584 /* 585 * Save all registers to allow syscall_return() to resume execution 586 * as if this function would have returned. This is also used in 587 * syscall_panic(). 588 * 589 * If stack usage of this function is changed 590 * thread_unwind_user_mode() has to be updated. 591 */ 592 push {r4-r12,lr} 593 594 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 595 ldr r5, [sp, #(11 * 0x4)] /* user function */ 596 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 597 598 /* 599 * Set the saved Processors Status Register to user mode to allow 600 * entry of user mode through movs below. 601 */ 602 msr spsr_cxsf, r6 603 604 /* 605 * Save old user sp and set new user sp. 606 */ 607 cps #CPSR_MODE_SYS 608 mov r6, sp 609 mov sp, r4 610 cps #CPSR_MODE_SVC 611 push {r6,r7} 612 613 /* 614 * Don't allow return from this function, return is done through 615 * thread_unwind_user_mode() below. 616 */ 617 mov lr, #0 618 /* Call the user function with its arguments */ 619 movs pc, r5 620UNWIND( .fnend) 621END_FUNC __thread_enter_user_mode 622 623/* 624 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 625 * uint32_t exit_status1); 626 * See description in thread.h 627 */ 628FUNC thread_unwind_user_mode , : 629UNWIND( .fnstart) 630UNWIND( .cantunwind) 631 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 632 str r1, [ip] 633 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 634 str r2, [ip] 635 636 /* Restore old user sp */ 637 pop {r4,r7} 638 cps #CPSR_MODE_SYS 639 mov sp, r4 640 cps #CPSR_MODE_SVC 641 642 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 643UNWIND( .fnend) 644END_FUNC thread_unwind_user_mode 645 646LOCAL_FUNC thread_abort_handler , : 647thread_abort_handler: 648thread_und_handler: 649UNWIND( .fnstart) 650UNWIND( .cantunwind) 651 /* 652 * Switch to abort mode to use that stack instead. 653 */ 654 cps #CPSR_MODE_ABT 655 push {r0-r11, ip} 656 cps #CPSR_MODE_UND 657 mrs r0, spsr 658 tst r0, #CPSR_T 659 subne r1, lr, #2 660 subeq r1, lr, #4 661 cps #CPSR_MODE_ABT 662 push {r0, r1} 663 msr spsr_fsxc, r0 /* In case some code reads spsr directly */ 664 mov r0, #ABORT_TYPE_UNDEF 665 b .thread_abort_generic 666 667thread_dabort_handler: 668 push {r0-r11, ip} 669 sub r1, lr, #8 670 mrs r0, spsr 671 push {r0, r1} 672 mov r0, #ABORT_TYPE_DATA 673 b .thread_abort_generic 674 675thread_pabort_handler: 676 push {r0-r11, ip} 677 sub r1, lr, #4 678 mrs r0, spsr 679 push {r0, r1} 680 mov r0, #ABORT_TYPE_PREFETCH 681 b .thread_abort_generic 682 683.thread_abort_generic: 684 cps #CPSR_MODE_SYS 685 mov r1, sp 686 mov r2, lr 687 cps #CPSR_MODE_ABT 688 push {r1-r3} 689 mov r1, sp 690 bl abort_handler 691 pop {r1-r3} 692 cps #CPSR_MODE_SYS 693 mov sp, r1 694 mov lr, r2 695 cps #CPSR_MODE_ABT 696 pop {r0, r1} 697 mov lr, r1 698 msr spsr_fsxc, r0 699 pop {r0-r11, ip} 700 movs pc, lr 701UNWIND( .fnend) 702END_FUNC thread_abort_handler 703 704LOCAL_FUNC thread_svc_handler , : 705UNWIND( .fnstart) 706UNWIND( .cantunwind) 707 push {r0-r7, lr} 708 mrs r0, spsr 709 push {r0} 710 mov r0, sp 711 bl tee_svc_handler 712 pop {r0} 713 msr spsr_fsxc, r0 714 pop {r0-r7, lr} 715 movs pc, lr 716UNWIND( .fnend) 717END_FUNC thread_svc_handler 718 719 .align 5 720LOCAL_FUNC thread_vect_table , : 721UNWIND( .fnstart) 722UNWIND( .cantunwind) 723 b . /* Reset */ 724 b thread_und_handler /* Undefined instruction */ 725 b thread_svc_handler /* System call */ 726 b thread_pabort_handler /* Prefetch abort */ 727 b thread_dabort_handler /* Data abort */ 728 b . /* Reserved */ 729 b thread_irq_handler /* IRQ */ 730 b thread_fiq_handler /* FIQ */ 731UNWIND( .fnend) 732END_FUNC thread_vect_table 733