1/* 2 * Copyright (c) 2016-2017, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <arm32_macros.S> 30#include <arm.h> 31#include <asm-defines.h> 32#include <asm.S> 33#include <keep.h> 34#include <kernel/abort.h> 35#include <kernel/thread_defs.h> 36#include <kernel/unwind.h> 37#include <sm/optee_smc.h> 38#include <sm/teesmc_opteed.h> 39#include <sm/teesmc_opteed_macros.h> 40 41#include "thread_private.h" 42 43 .section .text.thread_asm 44 45LOCAL_FUNC vector_std_smc_entry , : 46UNWIND( .fnstart) 47UNWIND( .cantunwind) 48 push {r0-r7} 49 mov r0, sp 50 bl thread_handle_std_smc 51 /* 52 * Normally thread_handle_std_smc() should return via 53 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 54 * hasn't switched stack (error detected) it will do a normal "C" 55 * return. 56 */ 57 pop {r1-r8} 58 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 59 smc #0 60 b . /* SMC should not return */ 61UNWIND( .fnend) 62END_FUNC vector_std_smc_entry 63 64LOCAL_FUNC vector_fast_smc_entry , : 65UNWIND( .fnstart) 66UNWIND( .cantunwind) 67 push {r0-r7} 68 mov r0, sp 69 bl thread_handle_fast_smc 70 pop {r1-r8} 71 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 72 smc #0 73 b . /* SMC should not return */ 74UNWIND( .fnend) 75END_FUNC vector_fast_smc_entry 76 77LOCAL_FUNC vector_fiq_entry , : 78UNWIND( .fnstart) 79UNWIND( .cantunwind) 80 /* Secure Monitor received a FIQ and passed control to us. */ 81 bl thread_check_canaries 82 ldr lr, =thread_nintr_handler_ptr 83 ldr lr, [lr] 84 blx lr 85 mov r1, r0 86 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 87 smc #0 88 b . /* SMC should not return */ 89UNWIND( .fnend) 90END_FUNC vector_fiq_entry 91 92LOCAL_FUNC vector_cpu_on_entry , : 93UNWIND( .fnstart) 94UNWIND( .cantunwind) 95 ldr lr, =thread_cpu_on_handler_ptr 96 ldr lr, [lr] 97 blx lr 98 mov r1, r0 99 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 100 smc #0 101 b . /* SMC should not return */ 102UNWIND( .fnend) 103END_FUNC vector_cpu_on_entry 104 105LOCAL_FUNC vector_cpu_off_entry , : 106UNWIND( .fnstart) 107UNWIND( .cantunwind) 108 ldr lr, =thread_cpu_off_handler_ptr 109 ldr lr, [lr] 110 blx lr 111 mov r1, r0 112 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 113 smc #0 114 b . /* SMC should not return */ 115UNWIND( .fnend) 116END_FUNC vector_cpu_off_entry 117 118LOCAL_FUNC vector_cpu_suspend_entry , : 119UNWIND( .fnstart) 120UNWIND( .cantunwind) 121 ldr lr, =thread_cpu_suspend_handler_ptr 122 ldr lr, [lr] 123 blx lr 124 mov r1, r0 125 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 126 smc #0 127 b . /* SMC should not return */ 128UNWIND( .fnend) 129END_FUNC vector_cpu_suspend_entry 130 131LOCAL_FUNC vector_cpu_resume_entry , : 132UNWIND( .fnstart) 133UNWIND( .cantunwind) 134 ldr lr, =thread_cpu_resume_handler_ptr 135 ldr lr, [lr] 136 blx lr 137 mov r1, r0 138 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 139 smc #0 140 b . /* SMC should not return */ 141UNWIND( .fnend) 142END_FUNC vector_cpu_resume_entry 143 144LOCAL_FUNC vector_system_off_entry , : 145UNWIND( .fnstart) 146UNWIND( .cantunwind) 147 ldr lr, =thread_system_off_handler_ptr 148 ldr lr, [lr] 149 blx lr 150 mov r1, r0 151 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 152 smc #0 153 b . /* SMC should not return */ 154UNWIND( .fnend) 155END_FUNC vector_system_off_entry 156 157LOCAL_FUNC vector_system_reset_entry , : 158UNWIND( .fnstart) 159UNWIND( .cantunwind) 160 ldr lr, =thread_system_reset_handler_ptr 161 ldr lr, [lr] 162 blx lr 163 mov r1, r0 164 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 165 smc #0 166 b . /* SMC should not return */ 167UNWIND( .fnend) 168END_FUNC vector_system_reset_entry 169 170/* 171 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 172 * initialization. Also used when compiled with the internal monitor, but 173 * the cpu_*_entry and system_*_entry are not used then. 174 * 175 * Note that ARM-TF depends on the layout of this vector table, any change 176 * in layout has to be synced with ARM-TF. 177 */ 178FUNC thread_vector_table , : 179UNWIND( .fnstart) 180UNWIND( .cantunwind) 181 b vector_std_smc_entry 182 b vector_fast_smc_entry 183 b vector_cpu_on_entry 184 b vector_cpu_off_entry 185 b vector_cpu_resume_entry 186 b vector_cpu_suspend_entry 187 b vector_fiq_entry 188 b vector_system_off_entry 189 b vector_system_reset_entry 190UNWIND( .fnend) 191END_FUNC thread_vector_table 192 193FUNC thread_set_abt_sp , : 194UNWIND( .fnstart) 195UNWIND( .cantunwind) 196 mrs r1, cpsr 197 cps #CPSR_MODE_ABT 198 mov sp, r0 199 msr cpsr, r1 200 bx lr 201UNWIND( .fnend) 202END_FUNC thread_set_abt_sp 203 204FUNC thread_set_und_sp , : 205UNWIND( .fnstart) 206UNWIND( .cantunwind) 207 mrs r1, cpsr 208 cps #CPSR_MODE_UND 209 mov sp, r0 210 msr cpsr, r1 211 bx lr 212UNWIND( .fnend) 213END_FUNC thread_set_abt_sp 214 215FUNC thread_set_irq_sp , : 216UNWIND( .fnstart) 217UNWIND( .cantunwind) 218 mrs r1, cpsr 219 cps #CPSR_MODE_IRQ 220 mov sp, r0 221 msr cpsr, r1 222 bx lr 223UNWIND( .fnend) 224END_FUNC thread_set_irq_sp 225 226FUNC thread_set_fiq_sp , : 227UNWIND( .fnstart) 228UNWIND( .cantunwind) 229 mrs r1, cpsr 230 cps #CPSR_MODE_FIQ 231 mov sp, r0 232 msr cpsr, r1 233 bx lr 234UNWIND( .fnend) 235END_FUNC thread_set_fiq_sp 236 237/* void thread_resume(struct thread_ctx_regs *regs) */ 238FUNC thread_resume , : 239UNWIND( .fnstart) 240UNWIND( .cantunwind) 241 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 242 243 cps #CPSR_MODE_SYS 244 ldm r12!, {sp, lr} 245 246 cps #CPSR_MODE_SVC 247 ldm r12!, {r1, sp, lr} 248 msr spsr_fsxc, r1 249 250 cps #CPSR_MODE_SVC 251 ldm r12, {r1, r2} 252 push {r1, r2} 253 254 ldm r0, {r0-r12} 255 256 /* Restore CPSR and jump to the instruction to resume at */ 257 rfefd sp! 258UNWIND( .fnend) 259END_FUNC thread_resume 260 261/* 262 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 263 * the banked r8-r12 registers, returns original CPSR. 264 */ 265LOCAL_FUNC thread_save_state_fiq , : 266UNWIND( .fnstart) 267UNWIND( .cantunwind) 268 mov r9, lr 269 270 /* 271 * Uses stack for temporary storage, while storing needed 272 * context in the thread context struct. 273 */ 274 275 mrs r8, cpsr 276 277 cpsid aif /* Disable Async abort, IRQ and FIQ */ 278 279 push {r4-r7} 280 push {r0-r3} 281 282 mrs r6, cpsr /* Save current CPSR */ 283 284 bl thread_get_ctx_regs 285 286 pop {r1-r4} /* r0-r3 pushed above */ 287 stm r0!, {r1-r4} 288 pop {r1-r4} /* r4-r7 pushed above */ 289 stm r0!, {r1-r4} 290 291 cps #CPSR_MODE_SYS 292 stm r0!, {r8-r12} 293 stm r0!, {sp, lr} 294 295 cps #CPSR_MODE_SVC 296 mrs r1, spsr 297 stm r0!, {r1, sp, lr} 298 299 /* back to fiq mode */ 300 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 301 msr cpsr, r6 /* Restore mode */ 302 303 mov r0, r8 /* Return original CPSR */ 304 bx r9 305UNWIND( .fnend) 306END_FUNC thread_save_state_fiq 307 308/* 309 * Disables IRQ and FIQ and saves state of thread, returns original 310 * CPSR. 311 */ 312LOCAL_FUNC thread_save_state , : 313UNWIND( .fnstart) 314UNWIND( .cantunwind) 315 push {r12, lr} 316 /* 317 * Uses stack for temporary storage, while storing needed 318 * context in the thread context struct. 319 */ 320 321 mrs r12, cpsr 322 323 cpsid aif /* Disable Async abort, IRQ and FIQ */ 324 325 push {r4-r7} 326 push {r0-r3} 327 328 mov r5, r12 /* Save CPSR in a preserved register */ 329 mrs r6, cpsr /* Save current CPSR */ 330 331 bl thread_get_ctx_regs 332 333 pop {r1-r4} /* r0-r3 pushed above */ 334 stm r0!, {r1-r4} 335 pop {r1-r4} /* r4-r7 pushed above */ 336 stm r0!, {r1-r4} 337 stm r0!, {r8-r11} 338 339 pop {r12, lr} 340 stm r0!, {r12} 341 342 cps #CPSR_MODE_SYS 343 stm r0!, {sp, lr} 344 345 cps #CPSR_MODE_SVC 346 mrs r1, spsr 347 stm r0!, {r1, sp, lr} 348 349 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 350 msr cpsr, r6 /* Restore mode */ 351 352 mov r0, r5 /* Return original CPSR */ 353 bx lr 354UNWIND( .fnend) 355END_FUNC thread_save_state 356 357FUNC thread_std_smc_entry , : 358UNWIND( .fnstart) 359UNWIND( .cantunwind) 360 /* Pass r0-r7 in a struct thread_smc_args */ 361 push {r0-r7} 362 mov r0, sp 363 bl __thread_std_smc_entry 364 /* 365 * Load the returned r0-r3 into preserved registers and skip the 366 * "returned" r4-r7 since they will not be returned to normal 367 * world. 368 */ 369 pop {r4-r7} 370 add sp, #(4 * 4) 371 372 /* Disable interrupts before switching to temporary stack */ 373 cpsid aif 374 bl thread_get_tmp_sp 375 mov sp, r0 376 377 bl thread_state_free 378 379 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 380 mov r1, r4 381 mov r2, r5 382 mov r3, r6 383 mov r4, r7 384 smc #0 385 b . /* SMC should not return */ 386UNWIND( .fnend) 387END_FUNC thread_std_smc_entry 388 389 390/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 391FUNC thread_rpc , : 392/* 393 * r0-r2 are used to pass parameters to normal world 394 * r0-r5 are used to pass return vaule back from normal world 395 * 396 * note that r3 is used to pass "resume information", that is, which 397 * thread it is that should resume. 398 * 399 * Since the this function is following AAPCS we need to preserve r4-r5 400 * which are otherwise modified when returning back from normal world. 401 */ 402UNWIND( .fnstart) 403 push {r4-r5, lr} 404UNWIND( .save {r4-r5, lr}) 405 push {r0} 406UNWIND( .save {r0}) 407 408 bl thread_save_state 409 mov r4, r0 /* Save original CPSR */ 410 411 /* 412 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 413 */ 414 bl thread_get_tmp_sp 415 ldr r5, [sp] /* Get pointer to rv[] */ 416 cps #CPSR_MODE_SVC /* Change to SVC mode */ 417 mov sp, r0 /* Switch to tmp stack */ 418 419 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 420 mov r1, r4 /* CPSR to restore */ 421 ldr r2, =.thread_rpc_return 422 bl thread_state_suspend 423 mov r4, r0 /* Supply thread index */ 424 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 425 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 426 smc #0 427 b . /* SMC should not return */ 428 429.thread_rpc_return: 430 /* 431 * At this point has the stack pointer been restored to the value 432 * it had when thread_save_state() was called above. 433 * 434 * Jumps here from thread_resume above when RPC has returned. The 435 * IRQ and FIQ bits are restored to what they where when this 436 * function was originally entered. 437 */ 438 pop {r12} /* Get pointer to rv[] */ 439 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 440 pop {r4-r5, pc} 441UNWIND( .fnend) 442END_FUNC thread_rpc 443 444/* The handler of native interrupt. */ 445.macro native_intr_handler mode:req 446 .ifc \mode\(),irq 447 /* 448 * Foreign interrupts should be masked. 449 * For GICv2, IRQ is for foreign interrupt and already masked by 450 * hardware in FIQ mode which is used for native interrupt. 451 * For GICv3, FIQ is for foreign interrupt. It's not masked by hardware 452 * in IRQ mode which is used for natvie interrupt. 453 */ 454 cpsid f 455 .endif 456 /* 457 * FIQ and IRQ have a +4 offset for lr compared to preferred return 458 * address 459 */ 460 sub lr, lr, #4 461 462 /* 463 * We're always saving {r0-r3}. In IRQ mode we're saving r12 also. 464 * In FIQ mode we're saving the banked fiq registers {r8-r12} FIQ 465 * because the secure monitor doesn't save those. The treatment of 466 * the banked fiq registers is somewhat analogous to the lazy save 467 * of VFP registers. 468 */ 469 .ifc \mode\(),fiq 470 push {r0-r3, r8-r12, lr} 471 .else 472 push {r0-r3, r12, lr} 473 .endif 474 bl thread_check_canaries 475 ldr lr, =thread_nintr_handler_ptr 476 ldr lr, [lr] 477 blx lr 478 .ifc \mode\(),fiq 479 pop {r0-r3, r8-r12, lr} 480 .else 481 pop {r0-r3, r12, lr} 482 .endif 483 movs pc, lr 484.endm 485 486/* The handler of foreign interrupt. */ 487.macro foreign_intr_handler mode:req 488 .ifc \mode\(),irq 489 /* 490 * Disable FIQ if the foreign interrupt is sent as IRQ. 491 * IRQ mode is set up to use tmp stack so FIQ has to be 492 * disabled before touching the stack. We can also assign 493 * SVC sp from IRQ sp to get SVC mode into the state we 494 * need when doing the SMC below. 495 * If it is sent as FIQ, the IRQ has already been masked by hardware 496 */ 497 cpsid f 498 .endif 499 sub lr, lr, #4 500 push {lr} 501 push {r12} 502 503 .ifc \mode\(),fiq 504 bl thread_save_state_fiq 505 .else 506 bl thread_save_state 507 .endif 508 509 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 510 mrs r1, spsr 511 pop {r12} 512 pop {r2} 513 blx thread_state_suspend 514 mov r4, r0 /* Supply thread index */ 515 516 /* 517 * Switch to SVC mode and copy current stack pointer as it already 518 * is the tmp stack. 519 */ 520 mov r0, sp 521 cps #CPSR_MODE_SVC 522 mov sp, r0 523 524 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 525 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 526 mov r2, #0 527 mov r3, #0 528 /* r4 is already filled in above */ 529 smc #0 530 b . /* SMC should not return */ 531.endm 532 533LOCAL_FUNC thread_fiq_handler , : 534UNWIND( .fnstart) 535UNWIND( .cantunwind) 536#if defined(CFG_ARM_GICV3) 537 foreign_intr_handler fiq 538#else 539 native_intr_handler fiq 540#endif 541UNWIND( .fnend) 542END_FUNC thread_fiq_handler 543 544LOCAL_FUNC thread_irq_handler , : 545UNWIND( .fnstart) 546UNWIND( .cantunwind) 547#if defined(CFG_ARM_GICV3) 548 native_intr_handler irq 549#else 550 foreign_intr_handler irq 551#endif 552UNWIND( .fnend) 553END_FUNC thread_irq_handler 554 555FUNC thread_init_vbar , : 556UNWIND( .fnstart) 557 /* Set vector (VBAR) */ 558 ldr r0, =thread_vect_table 559 write_vbar r0 560 bx lr 561UNWIND( .fnend) 562END_FUNC thread_init_vbar 563KEEP_PAGER thread_init_vbar 564 565/* 566 * Below are low level routines handling entry and return from user mode. 567 * 568 * thread_enter_user_mode() saves all that registers user mode can change 569 * so kernel mode can restore needed registers when resuming execution 570 * after the call to thread_enter_user_mode() has returned. 571 * thread_enter_user_mode() doesn't return directly since it enters user 572 * mode instead, it's thread_unwind_user_mode() that does the 573 * returning by restoring the registers saved by thread_enter_user_mode(). 574 * 575 * There's three ways for thread_enter_user_mode() to return to caller, 576 * user TA calls utee_return, user TA calls utee_panic or through an abort. 577 * 578 * Calls to utee_return or utee_panic are handled as: 579 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 580 * calls syscall_return() or syscall_panic(). 581 * 582 * These function calls returns normally except thread_svc_handler() which 583 * which is an exception handling routine so it reads return address and 584 * SPSR to restore from the stack. syscall_return() and syscall_panic() 585 * changes return address and SPSR used by thread_svc_handler() to instead of 586 * returning into user mode as with other syscalls it returns into 587 * thread_unwind_user_mode() in kernel mode instead. When 588 * thread_svc_handler() returns the stack pointer at the point where 589 * thread_enter_user_mode() left it so this is where 590 * thread_unwind_user_mode() can operate. 591 * 592 * Aborts are handled in a similar way but by thread_abort_handler() 593 * instead, when the pager sees that it's an abort from user mode that 594 * can't be handled it updates SPSR and return address used by 595 * thread_abort_handler() to return into thread_unwind_user_mode() 596 * instead. 597 */ 598 599/* 600 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 601 * unsigned long a2, unsigned long a3, unsigned long user_sp, 602 * unsigned long user_func, unsigned long spsr, 603 * uint32_t *exit_status0, uint32_t *exit_status1) 604 * 605 */ 606FUNC __thread_enter_user_mode , : 607UNWIND( .fnstart) 608UNWIND( .cantunwind) 609 /* 610 * Save all registers to allow syscall_return() to resume execution 611 * as if this function would have returned. This is also used in 612 * syscall_panic(). 613 * 614 * If stack usage of this function is changed 615 * thread_unwind_user_mode() has to be updated. 616 */ 617 push {r4-r12,lr} 618 619 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 620 ldr r5, [sp, #(11 * 0x4)] /* user function */ 621 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 622 623 /* 624 * Set the saved Processors Status Register to user mode to allow 625 * entry of user mode through movs below. 626 */ 627 msr spsr_cxsf, r6 628 629 /* 630 * Save old user sp and set new user sp. 631 */ 632 cps #CPSR_MODE_SYS 633 mov r6, sp 634 mov sp, r4 635 cps #CPSR_MODE_SVC 636 push {r6,r7} 637 638 /* 639 * Don't allow return from this function, return is done through 640 * thread_unwind_user_mode() below. 641 */ 642 mov lr, #0 643 /* Call the user function with its arguments */ 644 movs pc, r5 645UNWIND( .fnend) 646END_FUNC __thread_enter_user_mode 647 648/* 649 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 650 * uint32_t exit_status1); 651 * See description in thread.h 652 */ 653FUNC thread_unwind_user_mode , : 654UNWIND( .fnstart) 655UNWIND( .cantunwind) 656 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 657 str r1, [ip] 658 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 659 str r2, [ip] 660 661 /* Restore old user sp */ 662 pop {r4,r7} 663 cps #CPSR_MODE_SYS 664 mov sp, r4 665 cps #CPSR_MODE_SVC 666 667 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 668UNWIND( .fnend) 669END_FUNC thread_unwind_user_mode 670 671LOCAL_FUNC thread_abort_handler , : 672thread_und_handler: 673UNWIND( .fnstart) 674UNWIND( .cantunwind) 675 /* 676 * Disable both foreign and native interrupts in the thread handlers. 677 * The tee handlers can decide when the native interrupts should 678 * be enabled. 679 */ 680 cpsid f /* IRQ is already masked by the hardware */ 681 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 682 mrs r1, spsr 683 tst r1, #CPSR_T 684 subne lr, lr, #2 685 subeq lr, lr, #4 686 mov r0, #ABORT_TYPE_UNDEF 687 b .thread_abort_generic 688 689thread_dabort_handler: 690 /* 691 * Disable both foreign and native interrupts in the thread handlers. 692 * The tee handlers can decide when the native interrupts should 693 * be enabled. 694 */ 695 cpsid f /* IRQ is already masked by the hardware */ 696 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 697 sub lr, lr, #8 698 mov r0, #ABORT_TYPE_DATA 699 b .thread_abort_generic 700 701thread_pabort_handler: 702 /* 703 * Disable both foreign and native interrupts in the thread handlers. 704 * The tee handlers can decide when the native interrupts should 705 * be enabled. 706 */ 707 cpsid f /* IRQ is already masked by the hardware */ 708 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 709 sub lr, lr, #4 710 mov r0, #ABORT_TYPE_PREFETCH 711 712.thread_abort_generic: 713 /* 714 * At this label: 715 * cpsr is in mode undef or abort 716 * sp is still pointing to struct thread_core_local belonging to 717 * this core. 718 * {r0, r1} are saved in struct thread_core_local pointed to by sp 719 * {r2-r11, ip} are untouched. 720 * r0 holds the first argument for abort_handler() 721 */ 722 723 /* 724 * Update core local flags. 725 * flags = (flags << THREAD_CLF_SAVED_SHIFT) | THREAD_CLF_ABORT; 726 */ 727 ldr r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 728 lsl r1, r1, #THREAD_CLF_SAVED_SHIFT 729 orr r1, r1, #THREAD_CLF_ABORT 730 731 /* 732 * Select stack and update flags accordingly 733 * 734 * Normal case: 735 * If the abort stack is unused select that. 736 * 737 * Fatal error handling: 738 * If we're already using the abort stack as noted by bit 739 * (THREAD_CLF_SAVED_SHIFT + THREAD_CLF_ABORT_SHIFT) in the flags 740 * field we're selecting the temporary stack instead to be able to 741 * make a stack trace of the abort in abort mode. 742 * 743 * r1 is initialized as a temporary stack pointer until we've 744 * switched to system mode. 745 */ 746 tst r1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 747 orrne r1, r1, #THREAD_CLF_TMP /* flags |= THREAD_CLF_TMP; */ 748 str r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 749 ldrne r1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 750 ldreq r1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 751 752 /* 753 * Store registers on stack fitting struct thread_abort_regs 754 * start from the end of the struct 755 * {r2-r11, ip} 756 * Load content of previously saved {r0-r1} and stores 757 * it up to the pad field. 758 * After this is only {usr_sp, usr_lr} missing in the struct 759 */ 760 stmdb r1!, {r2-r11, ip} /* Push on the selected stack */ 761 ldrd r2, r3, [sp, #THREAD_CORE_LOCAL_R0] 762 /* Push the original {r0-r1} on the selected stack */ 763 stmdb r1!, {r2-r3} 764 mrs r3, spsr 765 /* Push {pad, spsr, elr} on the selected stack */ 766 stmdb r1!, {r2, r3, lr} 767 768 cps #CPSR_MODE_SYS 769 str lr, [r1, #-4]! 770 str sp, [r1, #-4]! 771 mov sp, r1 772 773 bl abort_handler 774 775 mov ip, sp 776 ldr sp, [ip], #4 777 ldr lr, [ip], #4 778 779 /* 780 * Even if we entered via CPSR_MODE_UND, we are returning via 781 * CPSR_MODE_ABT. It doesn't matter as lr and spsr are assigned 782 * here. 783 */ 784 cps #CPSR_MODE_ABT 785 ldm ip!, {r0, r1, lr} /* r0 is pad */ 786 msr spsr_fsxc, r1 787 788 /* Update core local flags */ 789 ldr r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 790 lsr r0, r0, #THREAD_CLF_SAVED_SHIFT 791 str r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 792 793 ldm ip, {r0-r11, ip} 794 795 movs pc, lr 796UNWIND( .fnend) 797END_FUNC thread_abort_handler 798 799LOCAL_FUNC thread_svc_handler , : 800UNWIND( .fnstart) 801UNWIND( .cantunwind) 802 /* 803 * Disable both foreign and native interrupts in the thread handlers. 804 * The tee handlers can decide when the native interrupts should 805 * be enabled. 806 */ 807 cpsid f /* IRQ is already masked by the hardware */ 808 push {r0-r7, lr} 809 mrs r0, spsr 810 push {r0} 811 mov r0, sp 812 bl tee_svc_handler 813 pop {r0} 814 msr spsr_fsxc, r0 815 pop {r0-r7, lr} 816 movs pc, lr 817UNWIND( .fnend) 818END_FUNC thread_svc_handler 819 820 .align 5 821LOCAL_FUNC thread_vect_table , : 822UNWIND( .fnstart) 823UNWIND( .cantunwind) 824 b . /* Reset */ 825 b thread_und_handler /* Undefined instruction */ 826 b thread_svc_handler /* System call */ 827 b thread_pabort_handler /* Prefetch abort */ 828 b thread_dabort_handler /* Data abort */ 829 b . /* Reserved */ 830 b thread_irq_handler /* IRQ */ 831 b thread_fiq_handler /* FIQ */ 832UNWIND( .fnend) 833END_FUNC thread_vect_table 834