1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2022, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * Copyright (c) 2020-2021, Arm Limited 6 */ 7 8 #include <platform_config.h> 9 10 #include <arm.h> 11 #include <assert.h> 12 #include <config.h> 13 #include <io.h> 14 #include <keep.h> 15 #include <kernel/asan.h> 16 #include <kernel/boot.h> 17 #include <kernel/linker.h> 18 #include <kernel/lockdep.h> 19 #include <kernel/misc.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <kernel/spmc_sp_handler.h> 23 #include <kernel/tee_ta_manager.h> 24 #include <kernel/thread.h> 25 #include <kernel/thread_private.h> 26 #include <kernel/user_mode_ctx_struct.h> 27 #include <kernel/virtualization.h> 28 #include <mm/core_memprot.h> 29 #include <mm/mobj.h> 30 #include <mm/tee_mm.h> 31 #include <mm/tee_pager.h> 32 #include <mm/vm.h> 33 #include <smccc.h> 34 #include <sm/sm.h> 35 #include <trace.h> 36 #include <util.h> 37 38 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 39 static vaddr_t thread_user_kcode_va __nex_bss; 40 long thread_user_kcode_offset __nex_bss; 41 static size_t thread_user_kcode_size __nex_bss; 42 #endif 43 44 #if defined(CFG_CORE_UNMAP_CORE_AT_EL0) && \ 45 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 46 long thread_user_kdata_sp_offset __nex_bss; 47 static uint8_t thread_user_kdata_page[ 48 ROUNDUP(sizeof(struct thread_core_local) * CFG_TEE_CORE_NB_CORE, 49 SMALL_PAGE_SIZE)] 50 __aligned(SMALL_PAGE_SIZE) 51 #ifndef CFG_VIRTUALIZATION 52 __section(".nozi.kdata_page"); 53 #else 54 __section(".nex_nozi.kdata_page"); 55 #endif 56 #endif 57 58 #ifdef ARM32 59 uint32_t __nostackcheck thread_get_exceptions(void) 60 { 61 uint32_t cpsr = read_cpsr(); 62 63 return (cpsr >> CPSR_F_SHIFT) & THREAD_EXCP_ALL; 64 } 65 66 void __nostackcheck thread_set_exceptions(uint32_t exceptions) 67 { 68 uint32_t cpsr = read_cpsr(); 69 70 /* Foreign interrupts must not be unmasked while holding a spinlock */ 71 if (!(exceptions & THREAD_EXCP_FOREIGN_INTR)) 72 assert_have_no_spinlock(); 73 74 cpsr &= ~(THREAD_EXCP_ALL << CPSR_F_SHIFT); 75 cpsr |= ((exceptions & THREAD_EXCP_ALL) << CPSR_F_SHIFT); 76 77 barrier(); 78 write_cpsr(cpsr); 79 barrier(); 80 } 81 #endif /*ARM32*/ 82 83 #ifdef ARM64 84 uint32_t __nostackcheck thread_get_exceptions(void) 85 { 86 uint32_t daif = read_daif(); 87 88 return (daif >> DAIF_F_SHIFT) & THREAD_EXCP_ALL; 89 } 90 91 void __nostackcheck thread_set_exceptions(uint32_t exceptions) 92 { 93 uint32_t daif = read_daif(); 94 95 /* Foreign interrupts must not be unmasked while holding a spinlock */ 96 if (!(exceptions & THREAD_EXCP_FOREIGN_INTR)) 97 assert_have_no_spinlock(); 98 99 daif &= ~(THREAD_EXCP_ALL << DAIF_F_SHIFT); 100 daif |= ((exceptions & THREAD_EXCP_ALL) << DAIF_F_SHIFT); 101 102 barrier(); 103 write_daif(daif); 104 barrier(); 105 } 106 #endif /*ARM64*/ 107 108 uint32_t __nostackcheck thread_mask_exceptions(uint32_t exceptions) 109 { 110 uint32_t state = thread_get_exceptions(); 111 112 thread_set_exceptions(state | (exceptions & THREAD_EXCP_ALL)); 113 return state; 114 } 115 116 void __nostackcheck thread_unmask_exceptions(uint32_t state) 117 { 118 thread_set_exceptions(state & THREAD_EXCP_ALL); 119 } 120 121 static void thread_lazy_save_ns_vfp(void) 122 { 123 #ifdef CFG_WITH_VFP 124 struct thread_ctx *thr = threads + thread_get_id(); 125 126 thr->vfp_state.ns_saved = false; 127 vfp_lazy_save_state_init(&thr->vfp_state.ns); 128 #endif /*CFG_WITH_VFP*/ 129 } 130 131 static void thread_lazy_restore_ns_vfp(void) 132 { 133 #ifdef CFG_WITH_VFP 134 struct thread_ctx *thr = threads + thread_get_id(); 135 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 136 137 assert(!thr->vfp_state.sec_lazy_saved && !thr->vfp_state.sec_saved); 138 139 if (tuv && tuv->lazy_saved && !tuv->saved) { 140 vfp_lazy_save_state_final(&tuv->vfp, false /*!force_save*/); 141 tuv->saved = true; 142 } 143 144 vfp_lazy_restore_state(&thr->vfp_state.ns, thr->vfp_state.ns_saved); 145 thr->vfp_state.ns_saved = false; 146 #endif /*CFG_WITH_VFP*/ 147 } 148 149 #ifdef ARM32 150 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, 151 uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, 152 uint32_t a6, uint32_t a7, void *pc) 153 { 154 thread->regs.pc = (uint32_t)pc; 155 156 /* 157 * Stdcalls starts in SVC mode with masked foreign interrupts, masked 158 * Asynchronous abort and unmasked native interrupts. 159 */ 160 thread->regs.cpsr = read_cpsr() & ARM32_CPSR_E; 161 thread->regs.cpsr |= CPSR_MODE_SVC | CPSR_A | 162 (THREAD_EXCP_FOREIGN_INTR << ARM32_CPSR_F_SHIFT); 163 /* Enable thumb mode if it's a thumb instruction */ 164 if (thread->regs.pc & 1) 165 thread->regs.cpsr |= CPSR_T; 166 /* Reinitialize stack pointer */ 167 thread->regs.svc_sp = thread->stack_va_end; 168 169 /* 170 * Copy arguments into context. This will make the 171 * arguments appear in r0-r7 when thread is started. 172 */ 173 thread->regs.r0 = a0; 174 thread->regs.r1 = a1; 175 thread->regs.r2 = a2; 176 thread->regs.r3 = a3; 177 thread->regs.r4 = a4; 178 thread->regs.r5 = a5; 179 thread->regs.r6 = a6; 180 thread->regs.r7 = a7; 181 } 182 #endif /*ARM32*/ 183 184 #ifdef ARM64 185 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, 186 uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, 187 uint32_t a6, uint32_t a7, void *pc) 188 { 189 thread->regs.pc = (uint64_t)pc; 190 191 /* 192 * Stdcalls starts in SVC mode with masked foreign interrupts, masked 193 * Asynchronous abort and unmasked native interrupts. 194 */ 195 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 196 THREAD_EXCP_FOREIGN_INTR | DAIFBIT_ABT); 197 /* Reinitialize stack pointer */ 198 thread->regs.sp = thread->stack_va_end; 199 200 /* 201 * Copy arguments into context. This will make the 202 * arguments appear in x0-x7 when thread is started. 203 */ 204 thread->regs.x[0] = a0; 205 thread->regs.x[1] = a1; 206 thread->regs.x[2] = a2; 207 thread->regs.x[3] = a3; 208 thread->regs.x[4] = a4; 209 thread->regs.x[5] = a5; 210 thread->regs.x[6] = a6; 211 thread->regs.x[7] = a7; 212 213 /* Set up frame pointer as per the Aarch64 AAPCS */ 214 thread->regs.x[29] = 0; 215 } 216 #endif /*ARM64*/ 217 218 static void __thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, 219 uint32_t a3, uint32_t a4, uint32_t a5, 220 uint32_t a6, uint32_t a7, 221 void *pc) 222 { 223 struct thread_core_local *l = thread_get_core_local(); 224 bool found_thread = false; 225 size_t n = 0; 226 227 assert(l->curr_thread == THREAD_ID_INVALID); 228 229 thread_lock_global(); 230 231 for (n = 0; n < CFG_NUM_THREADS; n++) { 232 if (threads[n].state == THREAD_STATE_FREE) { 233 threads[n].state = THREAD_STATE_ACTIVE; 234 found_thread = true; 235 break; 236 } 237 } 238 239 thread_unlock_global(); 240 241 if (!found_thread) 242 return; 243 244 l->curr_thread = n; 245 246 threads[n].flags = 0; 247 init_regs(threads + n, a0, a1, a2, a3, a4, a5, a6, a7, pc); 248 #ifdef CFG_CORE_PAUTH 249 /* 250 * Copy the APIA key into the registers to be restored with 251 * thread_resume(). 252 */ 253 threads[n].regs.apiakey_hi = threads[n].keys.apia_hi; 254 threads[n].regs.apiakey_lo = threads[n].keys.apia_lo; 255 #endif 256 257 thread_lazy_save_ns_vfp(); 258 259 l->flags &= ~THREAD_CLF_TMP; 260 thread_resume(&threads[n].regs); 261 /*NOTREACHED*/ 262 panic(); 263 } 264 265 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, 266 uint32_t a4, uint32_t a5) 267 { 268 __thread_alloc_and_run(a0, a1, a2, a3, a4, a5, 0, 0, 269 thread_std_smc_entry); 270 } 271 272 #ifdef CFG_SECURE_PARTITION 273 void thread_sp_alloc_and_run(struct thread_smc_args *args __maybe_unused) 274 { 275 __thread_alloc_and_run(args->a0, args->a1, args->a2, args->a3, args->a4, 276 args->a5, args->a6, args->a7, 277 spmc_sp_thread_entry); 278 } 279 #endif 280 281 #ifdef ARM32 282 static void copy_a0_to_a3(struct thread_ctx_regs *regs, uint32_t a0, 283 uint32_t a1, uint32_t a2, uint32_t a3) 284 { 285 /* 286 * Update returned values from RPC, values will appear in 287 * r0-r3 when thread is resumed. 288 */ 289 regs->r0 = a0; 290 regs->r1 = a1; 291 regs->r2 = a2; 292 regs->r3 = a3; 293 } 294 #endif /*ARM32*/ 295 296 #ifdef ARM64 297 static void copy_a0_to_a3(struct thread_ctx_regs *regs, uint32_t a0, 298 uint32_t a1, uint32_t a2, uint32_t a3) 299 { 300 /* 301 * Update returned values from RPC, values will appear in 302 * x0-x3 when thread is resumed. 303 */ 304 regs->x[0] = a0; 305 regs->x[1] = a1; 306 regs->x[2] = a2; 307 regs->x[3] = a3; 308 } 309 #endif /*ARM64*/ 310 311 #ifdef ARM32 312 static bool is_from_user(uint32_t cpsr) 313 { 314 return (cpsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 315 } 316 #endif 317 318 #ifdef ARM64 319 static bool is_from_user(uint32_t cpsr) 320 { 321 if (cpsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 322 return true; 323 if (((cpsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 324 SPSR_64_MODE_EL0) 325 return true; 326 return false; 327 } 328 #endif 329 330 #ifdef CFG_SYSCALL_FTRACE 331 static void __noprof ftrace_suspend(void) 332 { 333 struct ts_session *s = TAILQ_FIRST(&thread_get_tsd()->sess_stack); 334 335 if (s && s->fbuf) 336 s->fbuf->syscall_trace_suspended = true; 337 } 338 339 static void __noprof ftrace_resume(void) 340 { 341 struct ts_session *s = TAILQ_FIRST(&thread_get_tsd()->sess_stack); 342 343 if (s && s->fbuf) 344 s->fbuf->syscall_trace_suspended = false; 345 } 346 #else 347 static void __noprof ftrace_suspend(void) 348 { 349 } 350 351 static void __noprof ftrace_resume(void) 352 { 353 } 354 #endif 355 356 static bool is_user_mode(struct thread_ctx_regs *regs) 357 { 358 return is_from_user((uint32_t)regs->cpsr); 359 } 360 361 void thread_resume_from_rpc(uint32_t thread_id, uint32_t a0, uint32_t a1, 362 uint32_t a2, uint32_t a3) 363 { 364 size_t n = thread_id; 365 struct thread_core_local *l = thread_get_core_local(); 366 bool found_thread = false; 367 368 assert(l->curr_thread == THREAD_ID_INVALID); 369 370 thread_lock_global(); 371 372 if (n < CFG_NUM_THREADS && threads[n].state == THREAD_STATE_SUSPENDED) { 373 threads[n].state = THREAD_STATE_ACTIVE; 374 found_thread = true; 375 } 376 377 thread_unlock_global(); 378 379 if (!found_thread) 380 return; 381 382 l->curr_thread = n; 383 384 if (threads[n].have_user_map) { 385 core_mmu_set_user_map(&threads[n].user_map); 386 if (threads[n].flags & THREAD_FLAGS_EXIT_ON_FOREIGN_INTR) 387 tee_ta_ftrace_update_times_resume(); 388 } 389 390 if (is_user_mode(&threads[n].regs)) 391 tee_ta_update_session_utime_resume(); 392 393 /* 394 * Return from RPC to request service of a foreign interrupt must not 395 * get parameters from non-secure world. 396 */ 397 if (threads[n].flags & THREAD_FLAGS_COPY_ARGS_ON_RETURN) { 398 copy_a0_to_a3(&threads[n].regs, a0, a1, a2, a3); 399 threads[n].flags &= ~THREAD_FLAGS_COPY_ARGS_ON_RETURN; 400 } 401 402 thread_lazy_save_ns_vfp(); 403 404 if (threads[n].have_user_map) 405 ftrace_resume(); 406 407 l->flags &= ~THREAD_CLF_TMP; 408 thread_resume(&threads[n].regs); 409 /*NOTREACHED*/ 410 panic(); 411 } 412 413 #ifdef ARM64 414 vaddr_t thread_get_saved_thread_sp(void) 415 { 416 struct thread_core_local *l = thread_get_core_local(); 417 int ct = l->curr_thread; 418 419 assert(ct != THREAD_ID_INVALID); 420 return threads[ct].kern_sp; 421 } 422 #endif /*ARM64*/ 423 424 #ifdef ARM32 425 bool thread_is_in_normal_mode(void) 426 { 427 return (read_cpsr() & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_SVC; 428 } 429 #endif 430 431 void thread_state_free(void) 432 { 433 struct thread_core_local *l = thread_get_core_local(); 434 int ct = l->curr_thread; 435 436 assert(ct != THREAD_ID_INVALID); 437 438 thread_lazy_restore_ns_vfp(); 439 tee_pager_release_phys( 440 (void *)(threads[ct].stack_va_end - STACK_THREAD_SIZE), 441 STACK_THREAD_SIZE); 442 443 thread_lock_global(); 444 445 assert(threads[ct].state == THREAD_STATE_ACTIVE); 446 threads[ct].state = THREAD_STATE_FREE; 447 threads[ct].flags = 0; 448 l->curr_thread = THREAD_ID_INVALID; 449 450 if (IS_ENABLED(CFG_VIRTUALIZATION)) 451 virt_unset_guest(); 452 thread_unlock_global(); 453 } 454 455 #ifdef CFG_WITH_PAGER 456 static void release_unused_kernel_stack(struct thread_ctx *thr, 457 uint32_t cpsr __maybe_unused) 458 { 459 #ifdef ARM64 460 /* 461 * If we're from user mode then thr->regs.sp is the saved user 462 * stack pointer and thr->kern_sp holds the last kernel stack 463 * pointer. But if we're from kernel mode then thr->kern_sp isn't 464 * up to date so we need to read from thr->regs.sp instead. 465 */ 466 vaddr_t sp = is_from_user(cpsr) ? thr->kern_sp : thr->regs.sp; 467 #else 468 vaddr_t sp = thr->regs.svc_sp; 469 #endif 470 vaddr_t base = thr->stack_va_end - STACK_THREAD_SIZE; 471 size_t len = sp - base; 472 473 tee_pager_release_phys((void *)base, len); 474 } 475 #else 476 static void release_unused_kernel_stack(struct thread_ctx *thr __unused, 477 uint32_t cpsr __unused) 478 { 479 } 480 #endif 481 482 int thread_state_suspend(uint32_t flags, uint32_t cpsr, vaddr_t pc) 483 { 484 struct thread_core_local *l = thread_get_core_local(); 485 int ct = l->curr_thread; 486 487 assert(ct != THREAD_ID_INVALID); 488 489 if (core_mmu_user_mapping_is_active()) 490 ftrace_suspend(); 491 492 thread_check_canaries(); 493 494 release_unused_kernel_stack(threads + ct, cpsr); 495 496 if (is_from_user(cpsr)) { 497 thread_user_save_vfp(); 498 tee_ta_update_session_utime_suspend(); 499 tee_ta_gprof_sample_pc(pc); 500 } 501 thread_lazy_restore_ns_vfp(); 502 503 thread_lock_global(); 504 505 assert(threads[ct].state == THREAD_STATE_ACTIVE); 506 threads[ct].flags |= flags; 507 threads[ct].regs.cpsr = cpsr; 508 threads[ct].regs.pc = pc; 509 threads[ct].state = THREAD_STATE_SUSPENDED; 510 511 threads[ct].have_user_map = core_mmu_user_mapping_is_active(); 512 if (threads[ct].have_user_map) { 513 if (threads[ct].flags & THREAD_FLAGS_EXIT_ON_FOREIGN_INTR) 514 tee_ta_ftrace_update_times_suspend(); 515 core_mmu_get_user_map(&threads[ct].user_map); 516 core_mmu_set_user_map(NULL); 517 } 518 519 l->curr_thread = THREAD_ID_INVALID; 520 521 if (IS_ENABLED(CFG_VIRTUALIZATION)) 522 virt_unset_guest(); 523 524 thread_unlock_global(); 525 526 return ct; 527 } 528 529 bool thread_init_stack(uint32_t thread_id, vaddr_t sp) 530 { 531 if (thread_id >= CFG_NUM_THREADS) 532 return false; 533 threads[thread_id].stack_va_end = sp; 534 return true; 535 } 536 537 static void __maybe_unused 538 set_core_local_kcode_offset(struct thread_core_local *cls, long offset) 539 { 540 size_t n = 0; 541 542 for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) 543 cls[n].kcode_offset = offset; 544 } 545 546 static void init_user_kcode(void) 547 { 548 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 549 vaddr_t v = (vaddr_t)thread_excp_vect; 550 vaddr_t ve = (vaddr_t)thread_excp_vect_end; 551 552 thread_user_kcode_va = ROUNDDOWN(v, CORE_MMU_USER_CODE_SIZE); 553 ve = ROUNDUP(ve, CORE_MMU_USER_CODE_SIZE); 554 thread_user_kcode_size = ve - thread_user_kcode_va; 555 556 core_mmu_get_user_va_range(&v, NULL); 557 thread_user_kcode_offset = thread_user_kcode_va - v; 558 559 set_core_local_kcode_offset(thread_core_local, 560 thread_user_kcode_offset); 561 #if defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 562 set_core_local_kcode_offset((void *)thread_user_kdata_page, 563 thread_user_kcode_offset); 564 /* 565 * When transitioning to EL0 subtract SP with this much to point to 566 * this special kdata page instead. SP is restored by add this much 567 * while transitioning back to EL1. 568 */ 569 v += thread_user_kcode_size; 570 thread_user_kdata_sp_offset = (vaddr_t)thread_core_local - v; 571 #endif 572 #endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 573 } 574 575 void thread_init_primary(void) 576 { 577 /* Initialize canaries around the stacks */ 578 thread_init_canaries(); 579 580 init_user_kcode(); 581 } 582 583 static uint32_t __maybe_unused get_midr_implementer(uint32_t midr) 584 { 585 return (midr >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK; 586 } 587 588 static uint32_t __maybe_unused get_midr_primary_part(uint32_t midr) 589 { 590 return (midr >> MIDR_PRIMARY_PART_NUM_SHIFT) & 591 MIDR_PRIMARY_PART_NUM_MASK; 592 } 593 594 static uint32_t __maybe_unused get_midr_variant(uint32_t midr) 595 { 596 return (midr >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK; 597 } 598 599 static uint32_t __maybe_unused get_midr_revision(uint32_t midr) 600 { 601 return (midr >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK; 602 } 603 604 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 605 #ifdef ARM64 606 static bool probe_workaround_available(uint32_t wa_id) 607 { 608 int32_t r; 609 610 r = thread_smc(SMCCC_VERSION, 0, 0, 0); 611 if (r < 0) 612 return false; 613 if (r < 0x10001) /* compare with version 1.1 */ 614 return false; 615 616 /* Version >= 1.1, so SMCCC_ARCH_FEATURES is available */ 617 r = thread_smc(SMCCC_ARCH_FEATURES, wa_id, 0, 0); 618 return r >= 0; 619 } 620 621 static vaddr_t __maybe_unused select_vector_wa_spectre_v2(void) 622 { 623 if (probe_workaround_available(SMCCC_ARCH_WORKAROUND_1)) { 624 DMSG("SMCCC_ARCH_WORKAROUND_1 (%#08" PRIx32 ") available", 625 SMCCC_ARCH_WORKAROUND_1); 626 DMSG("SMC Workaround for CVE-2017-5715 used"); 627 return (vaddr_t)thread_excp_vect_wa_spectre_v2; 628 } 629 630 DMSG("SMCCC_ARCH_WORKAROUND_1 (%#08" PRIx32 ") unavailable", 631 SMCCC_ARCH_WORKAROUND_1); 632 DMSG("SMC Workaround for CVE-2017-5715 not needed (if ARM-TF is up to date)"); 633 return (vaddr_t)thread_excp_vect; 634 } 635 #else 636 static vaddr_t __maybe_unused select_vector_wa_spectre_v2(void) 637 { 638 return (vaddr_t)thread_excp_vect_wa_spectre_v2; 639 } 640 #endif 641 #endif 642 643 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 644 static vaddr_t select_vector_wa_spectre_bhb(uint8_t loop_count __maybe_unused) 645 { 646 /* 647 * Spectre-BHB has only been analyzed for AArch64 so far. For 648 * AArch32 fall back to the Spectre-V2 workaround which is likely 649 * to work even if perhaps a bit more expensive than a more 650 * optimized workaround. 651 */ 652 #ifdef ARM64 653 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 654 struct thread_core_local *cl = (void *)thread_user_kdata_page; 655 656 cl[get_core_pos()].bhb_loop_count = loop_count; 657 #endif 658 thread_get_core_local()->bhb_loop_count = loop_count; 659 660 DMSG("Spectre-BHB CVE-2022-23960 workaround enabled with \"K\" = %u", 661 loop_count); 662 663 return (vaddr_t)thread_excp_vect_wa_spectre_bhb; 664 #else 665 return select_vector_wa_spectre_v2(); 666 #endif 667 } 668 #endif 669 670 static vaddr_t get_excp_vect(void) 671 { 672 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 673 uint32_t midr = read_midr(); 674 uint8_t vers = 0; 675 676 if (get_midr_implementer(midr) != MIDR_IMPLEMENTER_ARM) 677 return (vaddr_t)thread_excp_vect; 678 /* 679 * Variant rx, Revision py, for instance 680 * Variant 2 Revision 0 = r2p0 = 0x20 681 */ 682 vers = (get_midr_variant(midr) << 4) | get_midr_revision(midr); 683 684 /* 685 * Spectre-V2 (CVE-2017-5715) software workarounds covers what's 686 * needed for Spectre-BHB (CVE-2022-23960) too. The workaround for 687 * Spectre-V2 is more expensive than the one for Spectre-BHB so if 688 * possible select the workaround for Spectre-BHB. 689 */ 690 switch (get_midr_primary_part(midr)) { 691 #ifdef ARM32 692 /* Spectre-V2 */ 693 case CORTEX_A8_PART_NUM: 694 case CORTEX_A9_PART_NUM: 695 case CORTEX_A17_PART_NUM: 696 #endif 697 /* Spectre-V2 */ 698 case CORTEX_A57_PART_NUM: 699 case CORTEX_A73_PART_NUM: 700 case CORTEX_A75_PART_NUM: 701 return select_vector_wa_spectre_v2(); 702 #ifdef ARM32 703 /* Spectre-V2 */ 704 case CORTEX_A15_PART_NUM: 705 return (vaddr_t)thread_excp_vect_wa_a15_spectre_v2; 706 #endif 707 /* 708 * Spectre-V2 for vers < r1p0 709 * Spectre-BHB for vers >= r1p0 710 */ 711 case CORTEX_A72_PART_NUM: 712 if (vers < 0x10) 713 return select_vector_wa_spectre_v2(); 714 return select_vector_wa_spectre_bhb(8); 715 716 /* 717 * Doing the more safe but expensive Spectre-V2 workaround for CPUs 718 * still being researched on the best mitigation sequence. 719 */ 720 case CORTEX_A65_PART_NUM: 721 case CORTEX_A65AE_PART_NUM: 722 case NEOVERSE_E1_PART_NUM: 723 return select_vector_wa_spectre_v2(); 724 725 /* Spectre-BHB */ 726 case CORTEX_A76_PART_NUM: 727 case CORTEX_A76AE_PART_NUM: 728 case CORTEX_A77_PART_NUM: 729 return select_vector_wa_spectre_bhb(24); 730 case CORTEX_A78_PART_NUM: 731 case CORTEX_A78AE_PART_NUM: 732 case CORTEX_A78C_PART_NUM: 733 case CORTEX_A710_PART_NUM: 734 case CORTEX_X1_PART_NUM: 735 case CORTEX_X2_PART_NUM: 736 return select_vector_wa_spectre_bhb(32); 737 case NEOVERSE_N1_PART_NUM: 738 return select_vector_wa_spectre_bhb(24); 739 case NEOVERSE_N2_PART_NUM: 740 case NEOVERSE_V1_PART_NUM: 741 return select_vector_wa_spectre_bhb(32); 742 743 default: 744 return (vaddr_t)thread_excp_vect; 745 } 746 #endif /*CFG_CORE_WORKAROUND_SPECTRE_BP_SEC*/ 747 748 return (vaddr_t)thread_excp_vect; 749 } 750 751 void thread_init_per_cpu(void) 752 { 753 #ifdef ARM32 754 struct thread_core_local *l = thread_get_core_local(); 755 756 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 757 /* Initialize secure monitor */ 758 sm_init(l->tmp_stack_va_end + STACK_TMP_OFFS); 759 #endif 760 thread_set_irq_sp(l->tmp_stack_va_end); 761 thread_set_fiq_sp(l->tmp_stack_va_end); 762 thread_set_abt_sp((vaddr_t)l); 763 thread_set_und_sp((vaddr_t)l); 764 #endif 765 766 thread_init_vbar(get_excp_vect()); 767 768 #ifdef CFG_FTRACE_SUPPORT 769 /* 770 * Enable accesses to frequency register and physical counter 771 * register in EL0/PL0 required for timestamping during 772 * function tracing. 773 */ 774 write_cntkctl(read_cntkctl() | CNTKCTL_PL0PCTEN); 775 #endif 776 } 777 778 #ifdef CFG_WITH_VFP 779 uint32_t thread_kernel_enable_vfp(void) 780 { 781 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_FOREIGN_INTR); 782 struct thread_ctx *thr = threads + thread_get_id(); 783 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 784 785 assert(!vfp_is_enabled()); 786 787 if (!thr->vfp_state.ns_saved) { 788 vfp_lazy_save_state_final(&thr->vfp_state.ns, 789 true /*force_save*/); 790 thr->vfp_state.ns_saved = true; 791 } else if (thr->vfp_state.sec_lazy_saved && 792 !thr->vfp_state.sec_saved) { 793 /* 794 * This happens when we're handling an abort while the 795 * thread was using the VFP state. 796 */ 797 vfp_lazy_save_state_final(&thr->vfp_state.sec, 798 false /*!force_save*/); 799 thr->vfp_state.sec_saved = true; 800 } else if (tuv && tuv->lazy_saved && !tuv->saved) { 801 /* 802 * This can happen either during syscall or abort 803 * processing (while processing a syscall). 804 */ 805 vfp_lazy_save_state_final(&tuv->vfp, false /*!force_save*/); 806 tuv->saved = true; 807 } 808 809 vfp_enable(); 810 return exceptions; 811 } 812 813 void thread_kernel_disable_vfp(uint32_t state) 814 { 815 uint32_t exceptions; 816 817 assert(vfp_is_enabled()); 818 819 vfp_disable(); 820 exceptions = thread_get_exceptions(); 821 assert(exceptions & THREAD_EXCP_FOREIGN_INTR); 822 exceptions &= ~THREAD_EXCP_FOREIGN_INTR; 823 exceptions |= state & THREAD_EXCP_FOREIGN_INTR; 824 thread_set_exceptions(exceptions); 825 } 826 827 void thread_kernel_save_vfp(void) 828 { 829 struct thread_ctx *thr = threads + thread_get_id(); 830 831 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 832 if (vfp_is_enabled()) { 833 vfp_lazy_save_state_init(&thr->vfp_state.sec); 834 thr->vfp_state.sec_lazy_saved = true; 835 } 836 } 837 838 void thread_kernel_restore_vfp(void) 839 { 840 struct thread_ctx *thr = threads + thread_get_id(); 841 842 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 843 assert(!vfp_is_enabled()); 844 if (thr->vfp_state.sec_lazy_saved) { 845 vfp_lazy_restore_state(&thr->vfp_state.sec, 846 thr->vfp_state.sec_saved); 847 thr->vfp_state.sec_saved = false; 848 thr->vfp_state.sec_lazy_saved = false; 849 } 850 } 851 852 void thread_user_enable_vfp(struct thread_user_vfp_state *uvfp) 853 { 854 struct thread_ctx *thr = threads + thread_get_id(); 855 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 856 857 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 858 assert(!vfp_is_enabled()); 859 860 if (!thr->vfp_state.ns_saved) { 861 vfp_lazy_save_state_final(&thr->vfp_state.ns, 862 true /*force_save*/); 863 thr->vfp_state.ns_saved = true; 864 } else if (tuv && uvfp != tuv) { 865 if (tuv->lazy_saved && !tuv->saved) { 866 vfp_lazy_save_state_final(&tuv->vfp, 867 false /*!force_save*/); 868 tuv->saved = true; 869 } 870 } 871 872 if (uvfp->lazy_saved) 873 vfp_lazy_restore_state(&uvfp->vfp, uvfp->saved); 874 uvfp->lazy_saved = false; 875 uvfp->saved = false; 876 877 thr->vfp_state.uvfp = uvfp; 878 vfp_enable(); 879 } 880 881 void thread_user_save_vfp(void) 882 { 883 struct thread_ctx *thr = threads + thread_get_id(); 884 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 885 886 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 887 if (!vfp_is_enabled()) 888 return; 889 890 assert(tuv && !tuv->lazy_saved && !tuv->saved); 891 vfp_lazy_save_state_init(&tuv->vfp); 892 tuv->lazy_saved = true; 893 } 894 895 void thread_user_clear_vfp(struct user_mode_ctx *uctx) 896 { 897 struct thread_user_vfp_state *uvfp = &uctx->vfp; 898 struct thread_ctx *thr = threads + thread_get_id(); 899 900 if (uvfp == thr->vfp_state.uvfp) 901 thr->vfp_state.uvfp = NULL; 902 uvfp->lazy_saved = false; 903 uvfp->saved = false; 904 } 905 #endif /*CFG_WITH_VFP*/ 906 907 #ifdef ARM32 908 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 909 { 910 uint32_t s; 911 912 if (!is_32bit) 913 return false; 914 915 s = read_cpsr(); 916 s &= ~(CPSR_MODE_MASK | CPSR_T | CPSR_IT_MASK1 | CPSR_IT_MASK2); 917 s |= CPSR_MODE_USR; 918 if (entry_func & 1) 919 s |= CPSR_T; 920 *spsr = s; 921 return true; 922 } 923 #endif 924 925 #ifdef ARM64 926 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 927 { 928 uint32_t s; 929 930 if (is_32bit) { 931 s = read_daif() & (SPSR_32_AIF_MASK << SPSR_32_AIF_SHIFT); 932 s |= SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT; 933 s |= (entry_func & SPSR_32_T_MASK) << SPSR_32_T_SHIFT; 934 } else { 935 s = read_daif() & (SPSR_64_DAIF_MASK << SPSR_64_DAIF_SHIFT); 936 } 937 938 *spsr = s; 939 return true; 940 } 941 #endif 942 943 static void set_ctx_regs(struct thread_ctx_regs *regs, unsigned long a0, 944 unsigned long a1, unsigned long a2, unsigned long a3, 945 unsigned long user_sp, unsigned long entry_func, 946 uint32_t spsr, 947 struct thread_pauth_keys *keys __maybe_unused) 948 { 949 /* 950 * First clear all registers to avoid leaking information from 951 * other TAs or even the Core itself. 952 */ 953 *regs = (struct thread_ctx_regs){ }; 954 #ifdef ARM32 955 regs->r0 = a0; 956 regs->r1 = a1; 957 regs->r2 = a2; 958 regs->r3 = a3; 959 regs->usr_sp = user_sp; 960 regs->pc = entry_func; 961 regs->cpsr = spsr; 962 #endif 963 #ifdef ARM64 964 regs->x[0] = a0; 965 regs->x[1] = a1; 966 regs->x[2] = a2; 967 regs->x[3] = a3; 968 regs->sp = user_sp; 969 regs->pc = entry_func; 970 regs->cpsr = spsr; 971 regs->x[13] = user_sp; /* Used when running TA in Aarch32 */ 972 regs->sp = user_sp; /* Used when running TA in Aarch64 */ 973 #ifdef CFG_TA_PAUTH 974 assert(keys); 975 regs->apiakey_hi = keys->apia_hi; 976 regs->apiakey_lo = keys->apia_lo; 977 #endif 978 /* Set frame pointer (user stack can't be unwound past this point) */ 979 regs->x[29] = 0; 980 #endif 981 } 982 983 static struct thread_pauth_keys *thread_get_pauth_keys(void) 984 { 985 #if defined(CFG_TA_PAUTH) 986 struct ts_session *s = ts_get_current_session(); 987 /* Only user TA's support the PAUTH keys */ 988 struct user_ta_ctx *utc = to_user_ta_ctx(s->ctx); 989 990 return &utc->uctx.keys; 991 #else 992 return NULL; 993 #endif 994 } 995 996 uint32_t thread_enter_user_mode(unsigned long a0, unsigned long a1, 997 unsigned long a2, unsigned long a3, unsigned long user_sp, 998 unsigned long entry_func, bool is_32bit, 999 uint32_t *exit_status0, uint32_t *exit_status1) 1000 { 1001 uint32_t spsr = 0; 1002 uint32_t exceptions = 0; 1003 uint32_t rc = 0; 1004 struct thread_ctx_regs *regs = NULL; 1005 struct thread_pauth_keys *keys = NULL; 1006 1007 tee_ta_update_session_utime_resume(); 1008 1009 keys = thread_get_pauth_keys(); 1010 1011 /* Derive SPSR from current CPSR/PSTATE readout. */ 1012 if (!get_spsr(is_32bit, entry_func, &spsr)) { 1013 *exit_status0 = 1; /* panic */ 1014 *exit_status1 = 0xbadbadba; 1015 return 0; 1016 } 1017 1018 exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); 1019 /* 1020 * We're using the per thread location of saved context registers 1021 * for temporary storage. Now that exceptions are masked they will 1022 * not be used for any thing else until they are eventually 1023 * unmasked when user mode has been entered. 1024 */ 1025 regs = thread_get_ctx_regs(); 1026 set_ctx_regs(regs, a0, a1, a2, a3, user_sp, entry_func, spsr, keys); 1027 rc = __thread_enter_user_mode(regs, exit_status0, exit_status1); 1028 thread_unmask_exceptions(exceptions); 1029 return rc; 1030 } 1031 1032 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1033 void thread_get_user_kcode(struct mobj **mobj, size_t *offset, 1034 vaddr_t *va, size_t *sz) 1035 { 1036 core_mmu_get_user_va_range(va, NULL); 1037 *mobj = mobj_tee_ram_rx; 1038 *sz = thread_user_kcode_size; 1039 *offset = thread_user_kcode_va - (vaddr_t)mobj_get_va(*mobj, 0, *sz); 1040 } 1041 #endif 1042 1043 #if defined(CFG_CORE_UNMAP_CORE_AT_EL0) && \ 1044 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 1045 void thread_get_user_kdata(struct mobj **mobj, size_t *offset, 1046 vaddr_t *va, size_t *sz) 1047 { 1048 vaddr_t v; 1049 1050 core_mmu_get_user_va_range(&v, NULL); 1051 *va = v + thread_user_kcode_size; 1052 *mobj = mobj_tee_ram_rw; 1053 *sz = sizeof(thread_user_kdata_page); 1054 *offset = (vaddr_t)thread_user_kdata_page - 1055 (vaddr_t)mobj_get_va(*mobj, 0, *sz); 1056 } 1057 #endif 1058 1059 static void setup_unwind_user_mode(struct thread_svc_regs *regs) 1060 { 1061 #ifdef ARM32 1062 regs->lr = (uintptr_t)thread_unwind_user_mode; 1063 regs->spsr = read_cpsr(); 1064 #endif 1065 #ifdef ARM64 1066 regs->elr = (uintptr_t)thread_unwind_user_mode; 1067 regs->spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 0); 1068 regs->spsr |= read_daif(); 1069 /* 1070 * Regs is the value of stack pointer before calling the SVC 1071 * handler. By the addition matches for the reserved space at the 1072 * beginning of el0_sync_svc(). This prepares the stack when 1073 * returning to thread_unwind_user_mode instead of a normal 1074 * exception return. 1075 */ 1076 regs->sp_el0 = (uint64_t)(regs + 1); 1077 #endif 1078 } 1079 1080 static void gprof_set_status(struct ts_session *s __maybe_unused, 1081 enum ts_gprof_status status __maybe_unused) 1082 { 1083 #ifdef CFG_TA_GPROF_SUPPORT 1084 if (s->ctx->ops->gprof_set_status) 1085 s->ctx->ops->gprof_set_status(status); 1086 #endif 1087 } 1088 1089 /* 1090 * Note: this function is weak just to make it possible to exclude it from 1091 * the unpaged area. 1092 */ 1093 void __weak thread_svc_handler(struct thread_svc_regs *regs) 1094 { 1095 struct ts_session *sess = NULL; 1096 uint32_t state = 0; 1097 1098 /* Enable native interrupts */ 1099 state = thread_get_exceptions(); 1100 thread_unmask_exceptions(state & ~THREAD_EXCP_NATIVE_INTR); 1101 1102 thread_user_save_vfp(); 1103 1104 sess = ts_get_current_session(); 1105 /* 1106 * User mode service has just entered kernel mode, suspend gprof 1107 * collection until we're about to switch back again. 1108 */ 1109 gprof_set_status(sess, TS_GPROF_SUSPEND); 1110 1111 /* Restore foreign interrupts which are disabled on exception entry */ 1112 thread_restore_foreign_intr(); 1113 1114 assert(sess && sess->handle_svc); 1115 if (sess->handle_svc(regs)) { 1116 /* We're about to switch back to user mode */ 1117 gprof_set_status(sess, TS_GPROF_RESUME); 1118 } else { 1119 /* We're returning from __thread_enter_user_mode() */ 1120 setup_unwind_user_mode(regs); 1121 } 1122 } 1123 1124 #ifdef CFG_WITH_ARM_TRUSTED_FW 1125 /* 1126 * These five functions are __weak to allow platforms to override them if 1127 * needed. 1128 */ 1129 unsigned long __weak thread_cpu_off_handler(unsigned long a0 __unused, 1130 unsigned long a1 __unused) 1131 { 1132 return 0; 1133 } 1134 DECLARE_KEEP_PAGER(thread_cpu_off_handler); 1135 1136 unsigned long __weak thread_cpu_suspend_handler(unsigned long a0 __unused, 1137 unsigned long a1 __unused) 1138 { 1139 return 0; 1140 } 1141 DECLARE_KEEP_PAGER(thread_cpu_suspend_handler); 1142 1143 unsigned long __weak thread_cpu_resume_handler(unsigned long a0 __unused, 1144 unsigned long a1 __unused) 1145 { 1146 return 0; 1147 } 1148 DECLARE_KEEP_PAGER(thread_cpu_resume_handler); 1149 1150 unsigned long __weak thread_system_off_handler(unsigned long a0 __unused, 1151 unsigned long a1 __unused) 1152 { 1153 return 0; 1154 } 1155 DECLARE_KEEP_PAGER(thread_system_off_handler); 1156 1157 unsigned long __weak thread_system_reset_handler(unsigned long a0 __unused, 1158 unsigned long a1 __unused) 1159 { 1160 return 0; 1161 } 1162 DECLARE_KEEP_PAGER(thread_system_reset_handler); 1163 #endif /*CFG_WITH_ARM_TRUSTED_FW*/ 1164 1165 #ifdef CFG_CORE_WORKAROUND_ARM_NMFI 1166 void __noreturn itr_core_handler(void) 1167 { 1168 /* 1169 * Note: overrides the default implementation of this function so that 1170 * if there would be another handler defined there would be duplicate 1171 * symbol error during linking. 1172 */ 1173 panic("Secure interrupt received but it is not supported"); 1174 } 1175 #endif 1176