1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <platform_config.h> 28 #include <kernel/panic.h> 29 #include <kernel/thread.h> 30 #include <kernel/thread_defs.h> 31 #include "thread_private.h" 32 #include <sm/sm_defs.h> 33 #include <sm/sm.h> 34 #include <sm/teesmc.h> 35 #include <sm/teesmc_optee.h> 36 #include <arm.h> 37 #include <kernel/tz_proc_def.h> 38 #include <kernel/tz_proc.h> 39 #include <kernel/misc.h> 40 #include <mm/tee_mmu.h> 41 #include <mm/tee_mmu_defs.h> 42 #include <mm/tee_mm.h> 43 #include <mm/tee_pager.h> 44 #include <kernel/tee_ta_manager.h> 45 #include <util.h> 46 #include <trace.h> 47 #include <assert.h> 48 49 #ifdef ARM32 50 #define STACK_TMP_SIZE 1024 51 #define STACK_THREAD_SIZE 8192 52 53 #if TRACE_LEVEL > 0 54 #define STACK_ABT_SIZE 2048 55 #else 56 #define STACK_ABT_SIZE 1024 57 #endif 58 59 #endif /*ARM32*/ 60 61 #ifdef ARM64 62 #define STACK_TMP_SIZE 2048 63 #define STACK_THREAD_SIZE 8192 64 65 #if TRACE_LEVEL > 0 66 #define STACK_ABT_SIZE 3072 67 #else 68 #define STACK_ABT_SIZE 1024 69 #endif 70 #endif /*ARM64*/ 71 72 #define RPC_MAX_PARAMS 2 73 74 struct thread_ctx threads[CFG_NUM_THREADS]; 75 76 static struct thread_core_local thread_core_local[CFG_TEE_CORE_NB_CORE]; 77 78 #ifdef CFG_WITH_STACK_CANARIES 79 #ifdef ARM32 80 #define STACK_CANARY_SIZE (4 * sizeof(uint32_t)) 81 #endif 82 #ifdef ARM64 83 #define STACK_CANARY_SIZE (8 * sizeof(uint32_t)) 84 #endif 85 #define START_CANARY_VALUE 0xdededede 86 #define END_CANARY_VALUE 0xabababab 87 #define GET_START_CANARY(name, stack_num) name[stack_num][0] 88 #define GET_END_CANARY(name, stack_num) \ 89 name[stack_num][sizeof(name[stack_num]) / sizeof(uint32_t) - 1] 90 #else 91 #define STACK_CANARY_SIZE 0 92 #endif 93 94 #define DECLARE_STACK(name, num_stacks, stack_size) \ 95 static uint32_t name[num_stacks][ \ 96 ROUNDUP(stack_size + STACK_CANARY_SIZE, STACK_ALIGNMENT) / \ 97 sizeof(uint32_t)] \ 98 __attribute__((section(".nozi.stack"), \ 99 aligned(STACK_ALIGNMENT))) 100 101 #define GET_STACK(stack) \ 102 ((vaddr_t)(stack) + sizeof(stack) - STACK_CANARY_SIZE / 2) 103 104 DECLARE_STACK(stack_tmp, CFG_TEE_CORE_NB_CORE, STACK_TMP_SIZE); 105 DECLARE_STACK(stack_abt, CFG_TEE_CORE_NB_CORE, STACK_ABT_SIZE); 106 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 107 DECLARE_STACK(stack_sm, CFG_TEE_CORE_NB_CORE, SM_STACK_SIZE); 108 #endif 109 #ifndef CFG_WITH_PAGER 110 DECLARE_STACK(stack_thread, CFG_NUM_THREADS, STACK_THREAD_SIZE); 111 #endif 112 113 const vaddr_t stack_tmp_top[CFG_TEE_CORE_NB_CORE] = { 114 GET_STACK(stack_tmp[0]), 115 #if CFG_TEE_CORE_NB_CORE > 1 116 GET_STACK(stack_tmp[1]), 117 #endif 118 #if CFG_TEE_CORE_NB_CORE > 2 119 GET_STACK(stack_tmp[2]), 120 #endif 121 #if CFG_TEE_CORE_NB_CORE > 3 122 GET_STACK(stack_tmp[3]), 123 #endif 124 #if CFG_TEE_CORE_NB_CORE > 4 125 GET_STACK(stack_tmp[4]), 126 #endif 127 #if CFG_TEE_CORE_NB_CORE > 5 128 GET_STACK(stack_tmp[5]), 129 #endif 130 #if CFG_TEE_CORE_NB_CORE > 6 131 GET_STACK(stack_tmp[6]), 132 #endif 133 #if CFG_TEE_CORE_NB_CORE > 7 134 GET_STACK(stack_tmp[7]), 135 #endif 136 #if CFG_TEE_CORE_NB_CORE > 8 137 #error "Top of tmp stacks aren't defined for more than 8 CPUS" 138 #endif 139 }; 140 141 thread_smc_handler_t thread_std_smc_handler_ptr; 142 static thread_smc_handler_t thread_fast_smc_handler_ptr; 143 thread_fiq_handler_t thread_fiq_handler_ptr; 144 thread_svc_handler_t thread_svc_handler_ptr; 145 static thread_abort_handler_t thread_abort_handler_ptr; 146 thread_pm_handler_t thread_cpu_on_handler_ptr; 147 thread_pm_handler_t thread_cpu_off_handler_ptr; 148 thread_pm_handler_t thread_cpu_suspend_handler_ptr; 149 thread_pm_handler_t thread_cpu_resume_handler_ptr; 150 thread_pm_handler_t thread_system_off_handler_ptr; 151 thread_pm_handler_t thread_system_reset_handler_ptr; 152 153 154 static unsigned int thread_global_lock = SPINLOCK_UNLOCK; 155 156 static void init_canaries(void) 157 { 158 #ifdef CFG_WITH_STACK_CANARIES 159 size_t n; 160 #define INIT_CANARY(name) \ 161 for (n = 0; n < ARRAY_SIZE(name); n++) { \ 162 uint32_t *start_canary = &GET_START_CANARY(name, n); \ 163 uint32_t *end_canary = &GET_END_CANARY(name, n); \ 164 \ 165 *start_canary = START_CANARY_VALUE; \ 166 *end_canary = END_CANARY_VALUE; \ 167 DMSG("#Stack canaries for %s[%zu] with top at %p\n", \ 168 #name, n, (void *)(end_canary - 1)); \ 169 DMSG("watch *%p\n", (void *)end_canary); \ 170 } 171 172 INIT_CANARY(stack_tmp); 173 INIT_CANARY(stack_abt); 174 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 175 INIT_CANARY(stack_sm); 176 #endif 177 #ifndef CFG_WITH_PAGER 178 INIT_CANARY(stack_thread); 179 #endif 180 #endif/*CFG_WITH_STACK_CANARIES*/ 181 } 182 183 void thread_check_canaries(void) 184 { 185 #ifdef CFG_WITH_STACK_CANARIES 186 size_t n; 187 188 for (n = 0; n < ARRAY_SIZE(stack_tmp); n++) { 189 assert(GET_START_CANARY(stack_tmp, n) == START_CANARY_VALUE); 190 assert(GET_END_CANARY(stack_tmp, n) == END_CANARY_VALUE); 191 } 192 193 for (n = 0; n < ARRAY_SIZE(stack_abt); n++) { 194 assert(GET_START_CANARY(stack_abt, n) == START_CANARY_VALUE); 195 assert(GET_END_CANARY(stack_abt, n) == END_CANARY_VALUE); 196 } 197 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 198 for (n = 0; n < ARRAY_SIZE(stack_sm); n++) { 199 assert(GET_START_CANARY(stack_sm, n) == START_CANARY_VALUE); 200 assert(GET_END_CANARY(stack_sm, n) == END_CANARY_VALUE); 201 } 202 #endif 203 #ifndef CFG_WITH_PAGER 204 for (n = 0; n < ARRAY_SIZE(stack_thread); n++) { 205 assert(GET_START_CANARY(stack_thread, n) == START_CANARY_VALUE); 206 assert(GET_END_CANARY(stack_thread, n) == END_CANARY_VALUE); 207 } 208 #endif 209 #endif/*CFG_WITH_STACK_CANARIES*/ 210 } 211 212 static void lock_global(void) 213 { 214 cpu_spin_lock(&thread_global_lock); 215 } 216 217 static void unlock_global(void) 218 { 219 cpu_spin_unlock(&thread_global_lock); 220 } 221 222 #ifdef ARM32 223 uint32_t thread_get_exceptions(void) 224 { 225 uint32_t cpsr = read_cpsr(); 226 227 return (cpsr >> CPSR_F_SHIFT) & THREAD_EXCP_ALL; 228 } 229 230 void thread_set_exceptions(uint32_t exceptions) 231 { 232 uint32_t cpsr = read_cpsr(); 233 234 cpsr &= ~(THREAD_EXCP_ALL << CPSR_F_SHIFT); 235 cpsr |= ((exceptions & THREAD_EXCP_ALL) << CPSR_F_SHIFT); 236 write_cpsr(cpsr); 237 } 238 #endif /*ARM32*/ 239 240 #ifdef ARM64 241 uint32_t thread_get_exceptions(void) 242 { 243 uint32_t daif = read_daif(); 244 245 return (daif >> DAIF_F_SHIFT) & THREAD_EXCP_ALL; 246 } 247 248 void thread_set_exceptions(uint32_t exceptions) 249 { 250 uint32_t daif = read_daif(); 251 252 daif &= ~(THREAD_EXCP_ALL << DAIF_F_SHIFT); 253 daif |= ((exceptions & THREAD_EXCP_ALL) << DAIF_F_SHIFT); 254 write_daif(daif); 255 } 256 #endif /*ARM64*/ 257 258 uint32_t thread_mask_exceptions(uint32_t exceptions) 259 { 260 uint32_t state = thread_get_exceptions(); 261 262 thread_set_exceptions(state | (exceptions & THREAD_EXCP_ALL)); 263 return state; 264 } 265 266 void thread_unmask_exceptions(uint32_t state) 267 { 268 thread_set_exceptions(state & THREAD_EXCP_ALL); 269 } 270 271 272 struct thread_core_local *thread_get_core_local(void) 273 { 274 uint32_t cpu_id = get_core_pos(); 275 276 /* 277 * IRQs must be disabled before playing with core_local since 278 * we otherwise may be rescheduled to a different core in the 279 * middle of this function. 280 */ 281 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 282 283 assert(cpu_id < CFG_TEE_CORE_NB_CORE); 284 return &thread_core_local[cpu_id]; 285 } 286 287 static void thread_lazy_save_ns_vfp(void) 288 { 289 #ifdef CFG_WITH_VFP 290 struct thread_ctx *thr = threads + thread_get_id(); 291 292 thr->vfp_state.ns_saved = false; 293 #if defined(ARM64) && defined(CFG_WITH_ARM_TRUSTED_FW) 294 /* 295 * ARM TF saves and restores CPACR_EL1, so we must assume NS world 296 * uses VFP and always preserve the register file when secure world 297 * is about to use it 298 */ 299 thr->vfp_state.ns.force_save = true; 300 #endif 301 vfp_lazy_save_state_init(&thr->vfp_state.ns); 302 #endif /*CFG_WITH_VFP*/ 303 } 304 305 static void thread_lazy_restore_ns_vfp(void) 306 { 307 #ifdef CFG_WITH_VFP 308 struct thread_ctx *thr = threads + thread_get_id(); 309 310 assert(!thr->vfp_state.sec_lazy_saved && !thr->vfp_state.sec_saved); 311 vfp_lazy_restore_state(&thr->vfp_state.ns, thr->vfp_state.ns_saved); 312 thr->vfp_state.ns_saved = false; 313 #endif /*CFG_WITH_VFP*/ 314 } 315 316 #ifdef ARM32 317 static void init_regs(struct thread_ctx *thread, 318 struct thread_smc_args *args) 319 { 320 thread->regs.pc = (uint32_t)thread_std_smc_entry; 321 322 /* 323 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 324 * abort and unmasked FIQ. 325 */ 326 thread->regs.cpsr = read_cpsr() & ARM32_CPSR_E; 327 thread->regs.cpsr |= CPSR_MODE_SVC | CPSR_I | CPSR_A; 328 /* Enable thumb mode if it's a thumb instruction */ 329 if (thread->regs.pc & 1) 330 thread->regs.cpsr |= CPSR_T; 331 /* Reinitialize stack pointer */ 332 thread->regs.svc_sp = thread->stack_va_end; 333 334 /* 335 * Copy arguments into context. This will make the 336 * arguments appear in r0-r7 when thread is started. 337 */ 338 thread->regs.r0 = args->a0; 339 thread->regs.r1 = args->a1; 340 thread->regs.r2 = args->a2; 341 thread->regs.r3 = args->a3; 342 thread->regs.r4 = args->a4; 343 thread->regs.r5 = args->a5; 344 thread->regs.r6 = args->a6; 345 thread->regs.r7 = args->a7; 346 } 347 #endif /*ARM32*/ 348 349 #ifdef ARM64 350 static void init_regs(struct thread_ctx *thread, 351 struct thread_smc_args *args) 352 { 353 thread->regs.pc = (uint64_t)thread_std_smc_entry; 354 355 /* 356 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 357 * abort and unmasked FIQ. 358 */ 359 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 360 DAIFBIT_IRQ | DAIFBIT_ABT); 361 /* Reinitialize stack pointer */ 362 thread->regs.sp = thread->stack_va_end; 363 364 /* 365 * Copy arguments into context. This will make the 366 * arguments appear in x0-x7 when thread is started. 367 */ 368 thread->regs.x[0] = args->a0; 369 thread->regs.x[1] = args->a1; 370 thread->regs.x[2] = args->a2; 371 thread->regs.x[3] = args->a3; 372 thread->regs.x[4] = args->a4; 373 thread->regs.x[5] = args->a5; 374 thread->regs.x[6] = args->a6; 375 thread->regs.x[7] = args->a7; 376 } 377 #endif /*ARM64*/ 378 379 void thread_init_boot_thread(void) 380 { 381 struct thread_core_local *l = thread_get_core_local(); 382 size_t n; 383 384 for (n = 0; n < CFG_NUM_THREADS; n++) 385 TAILQ_INIT(&threads[n].mutexes); 386 387 for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) 388 thread_core_local[n].curr_thread = -1; 389 390 l->curr_thread = 0; 391 threads[0].state = THREAD_STATE_ACTIVE; 392 } 393 394 void thread_clr_boot_thread(void) 395 { 396 struct thread_core_local *l = thread_get_core_local(); 397 398 assert(l->curr_thread >= 0 && l->curr_thread < CFG_NUM_THREADS); 399 assert(threads[l->curr_thread].state == THREAD_STATE_ACTIVE); 400 assert(TAILQ_EMPTY(&threads[l->curr_thread].mutexes)); 401 threads[l->curr_thread].state = THREAD_STATE_FREE; 402 l->curr_thread = -1; 403 } 404 405 static void thread_alloc_and_run(struct thread_smc_args *args) 406 { 407 size_t n; 408 struct thread_core_local *l = thread_get_core_local(); 409 bool found_thread = false; 410 411 assert(l->curr_thread == -1); 412 413 lock_global(); 414 415 for (n = 0; n < CFG_NUM_THREADS; n++) { 416 if (threads[n].state == THREAD_STATE_FREE) { 417 threads[n].state = THREAD_STATE_ACTIVE; 418 found_thread = true; 419 break; 420 } 421 } 422 423 unlock_global(); 424 425 if (!found_thread) { 426 args->a0 = TEESMC_RETURN_ETHREAD_LIMIT; 427 return; 428 } 429 430 l->curr_thread = n; 431 432 threads[n].flags = 0; 433 init_regs(threads + n, args); 434 435 /* Save Hypervisor Client ID */ 436 threads[n].hyp_clnt_id = args->a7; 437 438 thread_lazy_save_ns_vfp(); 439 thread_resume(&threads[n].regs); 440 } 441 442 #ifdef ARM32 443 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 444 struct thread_smc_args *args) 445 { 446 /* 447 * Update returned values from RPC, values will appear in 448 * r0-r3 when thread is resumed. 449 */ 450 regs->r0 = args->a0; 451 regs->r1 = args->a1; 452 regs->r2 = args->a2; 453 regs->r3 = args->a3; 454 } 455 #endif /*ARM32*/ 456 457 #ifdef ARM64 458 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 459 struct thread_smc_args *args) 460 { 461 /* 462 * Update returned values from RPC, values will appear in 463 * x0-x3 when thread is resumed. 464 */ 465 regs->x[0] = args->a0; 466 regs->x[1] = args->a1; 467 regs->x[2] = args->a2; 468 regs->x[3] = args->a3; 469 } 470 #endif /*ARM64*/ 471 472 static void thread_resume_from_rpc(struct thread_smc_args *args) 473 { 474 size_t n = args->a3; /* thread id */ 475 struct thread_core_local *l = thread_get_core_local(); 476 uint32_t rv = 0; 477 478 assert(l->curr_thread == -1); 479 480 lock_global(); 481 482 if (n < CFG_NUM_THREADS && 483 threads[n].state == THREAD_STATE_SUSPENDED && 484 args->a7 == threads[n].hyp_clnt_id) 485 threads[n].state = THREAD_STATE_ACTIVE; 486 else 487 rv = TEESMC_RETURN_ERESUME; 488 489 unlock_global(); 490 491 if (rv) { 492 args->a0 = rv; 493 return; 494 } 495 496 l->curr_thread = n; 497 498 if (threads[n].have_user_map) 499 core_mmu_set_user_map(&threads[n].user_map); 500 501 /* 502 * Return from RPC to request service of an IRQ must not 503 * get parameters from non-secure world. 504 */ 505 if (threads[n].flags & THREAD_FLAGS_COPY_ARGS_ON_RETURN) { 506 copy_a0_to_a3(&threads[n].regs, args); 507 threads[n].flags &= ~THREAD_FLAGS_COPY_ARGS_ON_RETURN; 508 } 509 510 thread_lazy_save_ns_vfp(); 511 thread_resume(&threads[n].regs); 512 } 513 514 void thread_handle_fast_smc(struct thread_smc_args *args) 515 { 516 thread_check_canaries(); 517 thread_fast_smc_handler_ptr(args); 518 /* Fast handlers must not unmask any exceptions */ 519 assert(thread_get_exceptions() == THREAD_EXCP_ALL); 520 } 521 522 void thread_handle_std_smc(struct thread_smc_args *args) 523 { 524 thread_check_canaries(); 525 526 if (args->a0 == TEESMC32_CALL_RETURN_FROM_RPC) 527 thread_resume_from_rpc(args); 528 else 529 thread_alloc_and_run(args); 530 } 531 532 /* Helper routine for the assembly function thread_std_smc_entry() */ 533 void __thread_std_smc_entry(struct thread_smc_args *args) 534 { 535 struct thread_ctx *thr = threads + thread_get_id(); 536 537 if (!thr->rpc_arg) { 538 paddr_t parg; 539 void *arg; 540 541 parg = thread_rpc_alloc_arg( 542 TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 543 if (!parg || !ALIGNMENT_IS_OK(parg, struct teesmc32_arg) || 544 core_pa2va(parg, &arg)) { 545 thread_rpc_free_arg(parg); 546 args->a0 = TEESMC_RETURN_ENOMEM; 547 return; 548 } 549 550 thr->rpc_arg = arg; 551 thr->rpc_parg = parg; 552 } 553 554 thread_std_smc_handler_ptr(args); 555 } 556 557 void thread_handle_abort(uint32_t abort_type, struct thread_abort_regs *regs) 558 { 559 #ifdef CFG_WITH_VFP 560 struct thread_ctx *thr = threads + thread_get_id(); 561 562 if (vfp_is_enabled()) { 563 vfp_lazy_save_state_init(&thr->vfp_state.sec); 564 thr->vfp_state.sec_lazy_saved = true; 565 } 566 #endif 567 568 thread_abort_handler_ptr(abort_type, regs); 569 570 #ifdef CFG_WITH_VFP 571 assert(!vfp_is_enabled()); 572 if (thr->vfp_state.sec_lazy_saved) { 573 vfp_lazy_restore_state(&thr->vfp_state.sec, 574 thr->vfp_state.sec_saved); 575 thr->vfp_state.sec_saved = false; 576 thr->vfp_state.sec_lazy_saved = false; 577 } 578 #endif 579 } 580 581 void *thread_get_tmp_sp(void) 582 { 583 struct thread_core_local *l = thread_get_core_local(); 584 585 return (void *)l->tmp_stack_va_end; 586 } 587 588 #ifdef ARM64 589 vaddr_t thread_get_saved_thread_sp(void) 590 { 591 struct thread_core_local *l = thread_get_core_local(); 592 int ct = l->curr_thread; 593 594 assert(ct != -1); 595 return threads[ct].kern_sp; 596 } 597 #endif /*ARM64*/ 598 599 void thread_state_free(void) 600 { 601 struct thread_core_local *l = thread_get_core_local(); 602 int ct = l->curr_thread; 603 604 assert(ct != -1); 605 assert(TAILQ_EMPTY(&threads[ct].mutexes)); 606 607 thread_lazy_restore_ns_vfp(); 608 609 lock_global(); 610 611 assert(threads[ct].state == THREAD_STATE_ACTIVE); 612 threads[ct].state = THREAD_STATE_FREE; 613 threads[ct].flags = 0; 614 l->curr_thread = -1; 615 616 unlock_global(); 617 } 618 619 int thread_state_suspend(uint32_t flags, uint32_t cpsr, vaddr_t pc) 620 { 621 struct thread_core_local *l = thread_get_core_local(); 622 int ct = l->curr_thread; 623 624 assert(ct != -1); 625 626 thread_check_canaries(); 627 628 thread_lazy_restore_ns_vfp(); 629 630 lock_global(); 631 632 assert(threads[ct].state == THREAD_STATE_ACTIVE); 633 threads[ct].flags |= flags; 634 threads[ct].regs.cpsr = cpsr; 635 threads[ct].regs.pc = pc; 636 threads[ct].state = THREAD_STATE_SUSPENDED; 637 638 threads[ct].have_user_map = core_mmu_user_mapping_is_active(); 639 if (threads[ct].have_user_map) { 640 core_mmu_get_user_map(&threads[ct].user_map); 641 core_mmu_set_user_map(NULL); 642 } 643 644 645 l->curr_thread = -1; 646 647 unlock_global(); 648 649 return ct; 650 } 651 652 #ifdef ARM32 653 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 654 { 655 l->tmp_stack_va_end = sp; 656 thread_set_irq_sp(sp); 657 thread_set_fiq_sp(sp); 658 } 659 660 static void set_abt_stack(struct thread_core_local *l __unused, vaddr_t sp) 661 { 662 thread_set_abt_sp(sp); 663 } 664 #endif /*ARM32*/ 665 666 #ifdef ARM64 667 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 668 { 669 /* 670 * We're already using the tmp stack when this function is called 671 * so there's no need to assign it to any stack pointer. However, 672 * we'll need to restore it at different times so store it here. 673 */ 674 l->tmp_stack_va_end = sp; 675 } 676 677 static void set_abt_stack(struct thread_core_local *l, vaddr_t sp) 678 { 679 l->abt_stack_va_end = sp; 680 } 681 #endif /*ARM64*/ 682 683 bool thread_init_stack(uint32_t thread_id, vaddr_t sp) 684 { 685 if (thread_id >= CFG_NUM_THREADS) 686 return false; 687 threads[thread_id].stack_va_end = sp; 688 return true; 689 } 690 691 int thread_get_id(void) 692 { 693 /* thread_get_core_local() requires IRQs to be disabled */ 694 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 695 struct thread_core_local *l; 696 int ct; 697 698 l = thread_get_core_local(); 699 ct = l->curr_thread; 700 assert((ct >= 0) && (ct < CFG_NUM_THREADS)); 701 702 thread_unmask_exceptions(exceptions); 703 return ct; 704 } 705 706 static void init_handlers(const struct thread_handlers *handlers) 707 { 708 thread_std_smc_handler_ptr = handlers->std_smc; 709 thread_fast_smc_handler_ptr = handlers->fast_smc; 710 thread_fiq_handler_ptr = handlers->fiq; 711 thread_svc_handler_ptr = handlers->svc; 712 thread_abort_handler_ptr = handlers->abort; 713 thread_cpu_on_handler_ptr = handlers->cpu_on; 714 thread_cpu_off_handler_ptr = handlers->cpu_off; 715 thread_cpu_suspend_handler_ptr = handlers->cpu_suspend; 716 thread_cpu_resume_handler_ptr = handlers->cpu_resume; 717 thread_system_off_handler_ptr = handlers->system_off; 718 thread_system_reset_handler_ptr = handlers->system_reset; 719 } 720 721 722 #ifdef CFG_WITH_PAGER 723 static void init_thread_stacks(void) 724 { 725 size_t n; 726 727 /* 728 * Allocate virtual memory for thread stacks. 729 */ 730 for (n = 0; n < CFG_NUM_THREADS; n++) { 731 tee_mm_entry_t *mm; 732 vaddr_t sp; 733 734 /* Find vmem for thread stack and its protection gap */ 735 mm = tee_mm_alloc(&tee_mm_vcore, 736 SMALL_PAGE_SIZE + STACK_THREAD_SIZE); 737 TEE_ASSERT(mm); 738 739 /* Claim eventual physical page */ 740 tee_pager_add_pages(tee_mm_get_smem(mm), tee_mm_get_size(mm), 741 true); 742 743 /* Realloc both protection vmem and stack vmem separately */ 744 sp = tee_mm_get_smem(mm); 745 tee_mm_free(mm); 746 mm = tee_mm_alloc2(&tee_mm_vcore, sp, SMALL_PAGE_SIZE); 747 TEE_ASSERT(mm); 748 mm = tee_mm_alloc2(&tee_mm_vcore, sp + SMALL_PAGE_SIZE, 749 STACK_THREAD_SIZE); 750 TEE_ASSERT(mm); 751 752 /* init effective stack */ 753 sp = tee_mm_get_smem(mm) + tee_mm_get_bytes(mm); 754 if (!thread_init_stack(n, sp)) 755 panic(); 756 757 /* Add the area to the pager */ 758 tee_pager_add_area(mm, TEE_PAGER_AREA_RW, NULL, NULL); 759 } 760 } 761 #else 762 static void init_thread_stacks(void) 763 { 764 size_t n; 765 766 /* Assign the thread stacks */ 767 for (n = 0; n < CFG_NUM_THREADS; n++) { 768 if (!thread_init_stack(n, GET_STACK(stack_thread[n]))) 769 panic(); 770 } 771 } 772 #endif /*CFG_WITH_PAGER*/ 773 774 void thread_init_primary(const struct thread_handlers *handlers) 775 { 776 /* 777 * The COMPILE_TIME_ASSERT only works in function context. These 778 * checks verifies that the offsets used in assembly code matches 779 * what's used in C code. 780 */ 781 #ifdef ARM32 782 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r0) == 783 THREAD_SVC_REG_R0_OFFS); 784 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r1) == 785 THREAD_SVC_REG_R1_OFFS); 786 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r2) == 787 THREAD_SVC_REG_R2_OFFS); 788 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r3) == 789 THREAD_SVC_REG_R3_OFFS); 790 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r4) == 791 THREAD_SVC_REG_R4_OFFS); 792 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r5) == 793 THREAD_SVC_REG_R5_OFFS); 794 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r6) == 795 THREAD_SVC_REG_R6_OFFS); 796 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r7) == 797 THREAD_SVC_REG_R7_OFFS); 798 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, lr) == 799 THREAD_SVC_REG_LR_OFFS); 800 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, spsr) == 801 THREAD_SVC_REG_SPSR_OFFS); 802 #endif /*ARM32*/ 803 #ifdef ARM64 804 /* struct thread_abort_regs */ 805 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, x22) == 806 THREAD_ABT_REG_X_OFFS(22)); 807 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, elr) == 808 THREAD_ABT_REG_ELR_OFFS); 809 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, spsr) == 810 THREAD_ABT_REG_SPSR_OFFS); 811 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, sp_el0) == 812 THREAD_ABT_REG_SP_EL0_OFFS); 813 COMPILE_TIME_ASSERT(sizeof(struct thread_abort_regs) == 814 THREAD_ABT_REGS_SIZE); 815 816 /* struct thread_ctx */ 817 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx, kern_sp) == 818 THREAD_CTX_KERN_SP_OFFSET); 819 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx) == THREAD_CTX_SIZE); 820 821 /* struct thread_ctx_regs */ 822 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, sp) == 823 THREAD_CTX_REGS_SP_OFFSET); 824 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, pc) == 825 THREAD_CTX_REGS_PC_OFFSET); 826 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, cpsr) == 827 THREAD_CTX_REGS_SPSR_OFFSET); 828 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, x[23]) == 829 THREAD_CTX_REGS_X_OFFSET(23)); 830 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx_regs) == 831 THREAD_CTX_REGS_SIZE); 832 833 /* struct thread_user_mode_rec */ 834 COMPILE_TIME_ASSERT( 835 offsetof(struct thread_user_mode_rec, exit_status0_ptr) == 836 THREAD_USER_MODE_REC_EXIT_STATUS0_PTR_OFFSET); 837 COMPILE_TIME_ASSERT( 838 offsetof(struct thread_user_mode_rec, exit_status1_ptr) == 839 THREAD_USER_MODE_REC_EXIT_STATUS1_PTR_OFFSET); 840 COMPILE_TIME_ASSERT( 841 offsetof(struct thread_user_mode_rec, x[1]) == 842 THREAD_USER_MODE_REC_X_OFFSET(20)); 843 COMPILE_TIME_ASSERT(sizeof(struct thread_user_mode_rec) == 844 THREAD_USER_MODE_REC_SIZE); 845 846 /* struct thread_core_local */ 847 COMPILE_TIME_ASSERT( 848 offsetof(struct thread_core_local, tmp_stack_va_end) == 849 THREAD_CORE_LOCAL_TMP_STACK_VA_END_OFFSET); 850 COMPILE_TIME_ASSERT( 851 offsetof(struct thread_core_local, curr_thread) == 852 THREAD_CORE_LOCAL_CURR_THREAD_OFFSET); 853 COMPILE_TIME_ASSERT( 854 offsetof(struct thread_core_local, flags) == 855 THREAD_CORE_LOCAL_FLAGS_OFFSET); 856 COMPILE_TIME_ASSERT( 857 offsetof(struct thread_core_local, abt_stack_va_end) == 858 THREAD_CORE_LOCAL_ABT_STACK_VA_END_OFFSET); 859 COMPILE_TIME_ASSERT( 860 offsetof(struct thread_core_local, x[3]) == 861 THREAD_CORE_LOCAL_X_OFFSET(3)); 862 COMPILE_TIME_ASSERT(sizeof(struct thread_core_local) == 863 THREAD_CORE_LOCAL_SIZE); 864 865 #endif /*ARM64*/ 866 867 init_handlers(handlers); 868 869 /* Initialize canaries around the stacks */ 870 init_canaries(); 871 872 init_thread_stacks(); 873 } 874 875 static void init_sec_mon(size_t __unused pos) 876 { 877 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 878 /* Initialize secure monitor */ 879 sm_init(GET_STACK(stack_sm[pos])); 880 sm_set_entry_vector(thread_vector_table); 881 #endif 882 } 883 884 void thread_init_per_cpu(void) 885 { 886 size_t pos = get_core_pos(); 887 struct thread_core_local *l = thread_get_core_local(); 888 889 init_sec_mon(pos); 890 891 set_tmp_stack(l, GET_STACK(stack_tmp[pos])); 892 set_abt_stack(l, GET_STACK(stack_abt[pos])); 893 894 thread_init_vbar(); 895 } 896 897 void thread_set_tsd(void *tsd) 898 { 899 /* thread_get_core_local() requires IRQs to be disabled */ 900 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 901 struct thread_core_local *l; 902 int ct; 903 904 l = thread_get_core_local(); 905 ct = l->curr_thread; 906 907 assert(ct != -1); 908 assert(threads[ct].state == THREAD_STATE_ACTIVE); 909 threads[ct].tsd = tsd; 910 911 thread_unmask_exceptions(exceptions); 912 } 913 914 void *thread_get_tsd(void) 915 { 916 /* thread_get_core_local() requires IRQs to be disabled */ 917 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 918 struct thread_core_local *l; 919 int ct; 920 void *tsd; 921 922 l = thread_get_core_local(); 923 ct = l->curr_thread; 924 925 if (ct == -1 || threads[ct].state != THREAD_STATE_ACTIVE) 926 tsd = NULL; 927 else 928 tsd = threads[ct].tsd; 929 930 thread_unmask_exceptions(exceptions); 931 return tsd; 932 } 933 934 struct thread_ctx_regs *thread_get_ctx_regs(void) 935 { 936 struct thread_core_local *l = thread_get_core_local(); 937 938 assert(l->curr_thread != -1); 939 return &threads[l->curr_thread].regs; 940 } 941 942 void thread_set_irq(bool enable) 943 { 944 /* thread_get_core_local() requires IRQs to be disabled */ 945 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 946 struct thread_core_local *l; 947 948 l = thread_get_core_local(); 949 950 assert(l->curr_thread != -1); 951 952 if (enable) { 953 threads[l->curr_thread].flags |= THREAD_FLAGS_IRQ_ENABLE; 954 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 955 } else { 956 /* 957 * No need to disable IRQ here since it's already disabled 958 * above. 959 */ 960 threads[l->curr_thread].flags &= ~THREAD_FLAGS_IRQ_ENABLE; 961 } 962 } 963 964 void thread_restore_irq(void) 965 { 966 /* thread_get_core_local() requires IRQs to be disabled */ 967 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 968 struct thread_core_local *l; 969 970 l = thread_get_core_local(); 971 972 assert(l->curr_thread != -1); 973 974 if (threads[l->curr_thread].flags & THREAD_FLAGS_IRQ_ENABLE) 975 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 976 } 977 978 #ifdef CFG_WITH_VFP 979 uint32_t thread_kernel_enable_vfp(void) 980 { 981 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 982 struct thread_ctx *thr = threads + thread_get_id(); 983 984 assert(!vfp_is_enabled()); 985 986 if (!thr->vfp_state.ns_saved) { 987 vfp_lazy_save_state_final(&thr->vfp_state.ns); 988 thr->vfp_state.ns_saved = true; 989 } else if (thr->vfp_state.sec_lazy_saved && 990 !thr->vfp_state.sec_saved) { 991 /* 992 * This happens when we're handling an abort while the 993 * thread was using the VFP state. 994 */ 995 vfp_lazy_save_state_final(&thr->vfp_state.sec); 996 thr->vfp_state.sec_saved = true; 997 } 998 999 vfp_enable(); 1000 return exceptions; 1001 } 1002 1003 void thread_kernel_disable_vfp(uint32_t state) 1004 { 1005 uint32_t exceptions; 1006 1007 assert(vfp_is_enabled()); 1008 1009 vfp_disable(); 1010 exceptions = thread_get_exceptions(); 1011 assert(exceptions & THREAD_EXCP_IRQ); 1012 exceptions &= ~THREAD_EXCP_IRQ; 1013 exceptions |= state & THREAD_EXCP_IRQ; 1014 thread_set_exceptions(exceptions); 1015 } 1016 #endif /*CFG_WITH_VFP*/ 1017 1018 #ifdef ARM32 1019 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1020 { 1021 uint32_t s; 1022 1023 if (!is_32bit) 1024 return false; 1025 1026 s = read_spsr(); 1027 s &= ~(CPSR_MODE_MASK | CPSR_T | CPSR_IT_MASK1 | CPSR_IT_MASK2); 1028 s |= CPSR_MODE_USR; 1029 if (entry_func & 1) 1030 s |= CPSR_T; 1031 *spsr = s; 1032 return true; 1033 } 1034 #endif 1035 1036 #ifdef ARM64 1037 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1038 { 1039 uint32_t s; 1040 1041 if (is_32bit) { 1042 s = read_daif() & (SPSR_32_AIF_MASK << SPSR_32_AIF_SHIFT); 1043 s |= SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT; 1044 s |= (entry_func & SPSR_32_T_MASK) << SPSR_32_T_SHIFT; 1045 } else { 1046 s = read_daif() & (SPSR_64_DAIF_MASK << SPSR_64_DAIF_SHIFT); 1047 } 1048 1049 *spsr = s; 1050 return true; 1051 } 1052 #endif 1053 1054 uint32_t thread_enter_user_mode(unsigned long a0, unsigned long a1, 1055 unsigned long a2, unsigned long a3, unsigned long user_sp, 1056 unsigned long entry_func, bool is_32bit, 1057 uint32_t *exit_status0, uint32_t *exit_status1) 1058 { 1059 uint32_t spsr; 1060 1061 if (!get_spsr(is_32bit, entry_func, &spsr)) { 1062 *exit_status0 = 1; /* panic */ 1063 *exit_status1 = 0xbadbadba; 1064 return 0; 1065 } 1066 return __thread_enter_user_mode(a0, a1, a2, a3, user_sp, entry_func, 1067 spsr, exit_status0, exit_status1); 1068 } 1069 1070 void thread_add_mutex(struct mutex *m) 1071 { 1072 struct thread_core_local *l = thread_get_core_local(); 1073 int ct = l->curr_thread; 1074 1075 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1076 assert(m->owner_id == -1); 1077 m->owner_id = ct; 1078 TAILQ_INSERT_TAIL(&threads[ct].mutexes, m, link); 1079 } 1080 1081 void thread_rem_mutex(struct mutex *m) 1082 { 1083 struct thread_core_local *l = thread_get_core_local(); 1084 int ct = l->curr_thread; 1085 1086 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1087 assert(m->owner_id == ct); 1088 m->owner_id = -1; 1089 TAILQ_REMOVE(&threads[ct].mutexes, m, link); 1090 } 1091 1092 paddr_t thread_rpc_alloc_arg(size_t size) 1093 { 1094 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1095 TEESMC_RETURN_RPC_ALLOC_ARG, size}; 1096 1097 thread_rpc(rpc_args); 1098 return rpc_args[1]; 1099 } 1100 1101 paddr_t thread_rpc_alloc_payload(size_t size) 1102 { 1103 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1104 TEESMC_RETURN_RPC_ALLOC_PAYLOAD, size}; 1105 1106 thread_rpc(rpc_args); 1107 return rpc_args[1]; 1108 } 1109 1110 void thread_rpc_free_arg(paddr_t arg) 1111 { 1112 if (arg) { 1113 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1114 TEESMC_RETURN_RPC_FREE_ARG, arg}; 1115 1116 thread_rpc(rpc_args); 1117 } 1118 } 1119 void thread_rpc_free_payload(paddr_t payload) 1120 { 1121 if (payload) { 1122 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1123 TEESMC_RETURN_RPC_FREE_PAYLOAD, payload}; 1124 1125 thread_rpc(rpc_args); 1126 } 1127 } 1128 1129 static uint32_t rpc_cmd_nolock(uint32_t cmd, size_t num_params, 1130 struct teesmc32_param *params) 1131 { 1132 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 0 }; 1133 struct thread_ctx *thr = threads + thread_get_id(); 1134 struct teesmc32_arg *arg = thr->rpc_arg; 1135 paddr_t parg = thr->rpc_parg; 1136 const size_t params_size = sizeof(struct teesmc32_param) * num_params; 1137 size_t n; 1138 1139 TEE_ASSERT(arg && parg && num_params <= RPC_MAX_PARAMS); 1140 1141 memset(arg, 0, TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 1142 arg->cmd = cmd; 1143 arg->ret = TEE_ERROR_GENERIC; /* in case value isn't updated */ 1144 arg->num_params = num_params; 1145 memcpy(TEESMC32_GET_PARAMS(arg), params, params_size); 1146 1147 rpc_args[0] = TEESMC_RETURN_RPC_CMD; 1148 rpc_args[1] = parg; 1149 thread_rpc(rpc_args); 1150 1151 for (n = 0; n < num_params; n++) { 1152 switch (params[n].attr & TEESMC_ATTR_TYPE_MASK) { 1153 case TEESMC_ATTR_TYPE_VALUE_OUTPUT: 1154 case TEESMC_ATTR_TYPE_VALUE_INOUT: 1155 case TEESMC_ATTR_TYPE_MEMREF_OUTPUT: 1156 case TEESMC_ATTR_TYPE_MEMREF_INOUT: 1157 memcpy(params + n, TEESMC32_GET_PARAMS(arg) + n, 1158 sizeof(struct teesmc32_param)); 1159 break; 1160 default: 1161 break; 1162 } 1163 } 1164 1165 return arg->ret; 1166 } 1167 1168 uint32_t thread_rpc_cmd(uint32_t cmd, size_t num_params, 1169 struct teesmc32_param *params) 1170 { 1171 uint32_t ret; 1172 1173 ret = rpc_cmd_nolock(cmd, num_params, params); 1174 1175 return ret; 1176 } 1177 1178 void thread_optee_rpc_alloc_payload(size_t size, paddr_t *payload, 1179 paddr_t *cookie) 1180 { 1181 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1182 TEESMC_RETURN_OPTEE_RPC_ALLOC_PAYLOAD, size}; 1183 1184 thread_rpc(rpc_args); 1185 if (payload) 1186 *payload = rpc_args[1]; 1187 if (cookie) 1188 *cookie = rpc_args[2]; 1189 } 1190 1191 void thread_optee_rpc_free_payload(paddr_t cookie) 1192 { 1193 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] ={ 1194 TEESMC_RETURN_OPTEE_RPC_FREE_PAYLOAD, cookie}; 1195 1196 thread_rpc(rpc_args); 1197 } 1198