1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <platform_config.h> 28 #include <kernel/panic.h> 29 #include <kernel/thread.h> 30 #include <kernel/thread_defs.h> 31 #include "thread_private.h" 32 #include <sm/sm_defs.h> 33 #include <sm/sm.h> 34 #include <sm/teesmc.h> 35 #include <sm/teesmc_optee.h> 36 #include <arm.h> 37 #include <kernel/tz_proc_def.h> 38 #include <kernel/tz_proc.h> 39 #include <kernel/misc.h> 40 #include <mm/tee_mmu.h> 41 #include <mm/tee_mmu_defs.h> 42 #include <mm/tee_mm.h> 43 #include <mm/tee_pager.h> 44 #include <kernel/tee_ta_manager.h> 45 #include <util.h> 46 #include <trace.h> 47 #include <assert.h> 48 49 #ifdef ARM32 50 #define STACK_TMP_SIZE 1024 51 #define STACK_THREAD_SIZE 8192 52 53 #if TRACE_LEVEL > 0 54 #define STACK_ABT_SIZE 2048 55 #else 56 #define STACK_ABT_SIZE 1024 57 #endif 58 59 #endif /*ARM32*/ 60 61 #ifdef ARM64 62 #define STACK_TMP_SIZE 2048 63 #define STACK_THREAD_SIZE 8192 64 65 #if TRACE_LEVEL > 0 66 #define STACK_ABT_SIZE 3072 67 #else 68 #define STACK_ABT_SIZE 1024 69 #endif 70 #endif /*ARM64*/ 71 72 #define RPC_MAX_PARAMS 2 73 74 struct thread_ctx threads[CFG_NUM_THREADS]; 75 76 static struct thread_core_local thread_core_local[CFG_TEE_CORE_NB_CORE]; 77 78 #ifdef CFG_WITH_STACK_CANARIES 79 #ifdef ARM32 80 #define STACK_CANARY_SIZE (4 * sizeof(uint32_t)) 81 #endif 82 #ifdef ARM64 83 #define STACK_CANARY_SIZE (8 * sizeof(uint32_t)) 84 #endif 85 #define START_CANARY_VALUE 0xdededede 86 #define END_CANARY_VALUE 0xabababab 87 #define GET_START_CANARY(name, stack_num) name[stack_num][0] 88 #define GET_END_CANARY(name, stack_num) \ 89 name[stack_num][sizeof(name[stack_num]) / sizeof(uint32_t) - 1] 90 #else 91 #define STACK_CANARY_SIZE 0 92 #endif 93 94 #define DECLARE_STACK(name, num_stacks, stack_size) \ 95 static uint32_t name[num_stacks][ \ 96 ROUNDUP(stack_size + STACK_CANARY_SIZE, STACK_ALIGNMENT) / \ 97 sizeof(uint32_t)] \ 98 __attribute__((section(".nozi.stack"), \ 99 aligned(STACK_ALIGNMENT))) 100 101 #define GET_STACK(stack) \ 102 ((vaddr_t)(stack) + sizeof(stack) - STACK_CANARY_SIZE / 2) 103 104 DECLARE_STACK(stack_tmp, CFG_TEE_CORE_NB_CORE, STACK_TMP_SIZE); 105 DECLARE_STACK(stack_abt, CFG_TEE_CORE_NB_CORE, STACK_ABT_SIZE); 106 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 107 DECLARE_STACK(stack_sm, CFG_TEE_CORE_NB_CORE, SM_STACK_SIZE); 108 #endif 109 #ifndef CFG_WITH_PAGER 110 DECLARE_STACK(stack_thread, CFG_NUM_THREADS, STACK_THREAD_SIZE); 111 #endif 112 113 const vaddr_t stack_tmp_top[CFG_TEE_CORE_NB_CORE] = { 114 GET_STACK(stack_tmp[0]), 115 #if CFG_TEE_CORE_NB_CORE > 1 116 GET_STACK(stack_tmp[1]), 117 #endif 118 #if CFG_TEE_CORE_NB_CORE > 2 119 GET_STACK(stack_tmp[2]), 120 #endif 121 #if CFG_TEE_CORE_NB_CORE > 3 122 GET_STACK(stack_tmp[3]), 123 #endif 124 #if CFG_TEE_CORE_NB_CORE > 4 125 GET_STACK(stack_tmp[4]), 126 #endif 127 #if CFG_TEE_CORE_NB_CORE > 5 128 GET_STACK(stack_tmp[5]), 129 #endif 130 #if CFG_TEE_CORE_NB_CORE > 6 131 GET_STACK(stack_tmp[6]), 132 #endif 133 #if CFG_TEE_CORE_NB_CORE > 7 134 GET_STACK(stack_tmp[7]), 135 #endif 136 #if CFG_TEE_CORE_NB_CORE > 8 137 #error "Top of tmp stacks aren't defined for more than 8 CPUS" 138 #endif 139 }; 140 141 thread_smc_handler_t thread_std_smc_handler_ptr; 142 static thread_smc_handler_t thread_fast_smc_handler_ptr; 143 thread_fiq_handler_t thread_fiq_handler_ptr; 144 thread_svc_handler_t thread_svc_handler_ptr; 145 static thread_abort_handler_t thread_abort_handler_ptr; 146 thread_pm_handler_t thread_cpu_on_handler_ptr; 147 thread_pm_handler_t thread_cpu_off_handler_ptr; 148 thread_pm_handler_t thread_cpu_suspend_handler_ptr; 149 thread_pm_handler_t thread_cpu_resume_handler_ptr; 150 thread_pm_handler_t thread_system_off_handler_ptr; 151 thread_pm_handler_t thread_system_reset_handler_ptr; 152 153 154 static unsigned int thread_global_lock = SPINLOCK_UNLOCK; 155 156 static void init_canaries(void) 157 { 158 #ifdef CFG_WITH_STACK_CANARIES 159 size_t n; 160 #define INIT_CANARY(name) \ 161 for (n = 0; n < ARRAY_SIZE(name); n++) { \ 162 uint32_t *start_canary = &GET_START_CANARY(name, n); \ 163 uint32_t *end_canary = &GET_END_CANARY(name, n); \ 164 \ 165 *start_canary = START_CANARY_VALUE; \ 166 *end_canary = END_CANARY_VALUE; \ 167 DMSG("#Stack canaries for %s[%zu] with top at %p\n", \ 168 #name, n, (void *)(end_canary - 1)); \ 169 DMSG("watch *%p\n", (void *)end_canary); \ 170 } 171 172 INIT_CANARY(stack_tmp); 173 INIT_CANARY(stack_abt); 174 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 175 INIT_CANARY(stack_sm); 176 #endif 177 #ifndef CFG_WITH_PAGER 178 INIT_CANARY(stack_thread); 179 #endif 180 #endif/*CFG_WITH_STACK_CANARIES*/ 181 } 182 183 void thread_check_canaries(void) 184 { 185 #ifdef CFG_WITH_STACK_CANARIES 186 size_t n; 187 188 for (n = 0; n < ARRAY_SIZE(stack_tmp); n++) { 189 assert(GET_START_CANARY(stack_tmp, n) == START_CANARY_VALUE); 190 assert(GET_END_CANARY(stack_tmp, n) == END_CANARY_VALUE); 191 } 192 193 for (n = 0; n < ARRAY_SIZE(stack_abt); n++) { 194 assert(GET_START_CANARY(stack_abt, n) == START_CANARY_VALUE); 195 assert(GET_END_CANARY(stack_abt, n) == END_CANARY_VALUE); 196 } 197 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 198 for (n = 0; n < ARRAY_SIZE(stack_sm); n++) { 199 assert(GET_START_CANARY(stack_sm, n) == START_CANARY_VALUE); 200 assert(GET_END_CANARY(stack_sm, n) == END_CANARY_VALUE); 201 } 202 #endif 203 #ifndef CFG_WITH_PAGER 204 for (n = 0; n < ARRAY_SIZE(stack_thread); n++) { 205 assert(GET_START_CANARY(stack_thread, n) == START_CANARY_VALUE); 206 assert(GET_END_CANARY(stack_thread, n) == END_CANARY_VALUE); 207 } 208 #endif 209 #endif/*CFG_WITH_STACK_CANARIES*/ 210 } 211 212 static void lock_global(void) 213 { 214 cpu_spin_lock(&thread_global_lock); 215 } 216 217 static void unlock_global(void) 218 { 219 cpu_spin_unlock(&thread_global_lock); 220 } 221 222 #ifdef ARM32 223 uint32_t thread_get_exceptions(void) 224 { 225 uint32_t cpsr = read_cpsr(); 226 227 return (cpsr >> CPSR_F_SHIFT) & THREAD_EXCP_ALL; 228 } 229 230 void thread_set_exceptions(uint32_t exceptions) 231 { 232 uint32_t cpsr = read_cpsr(); 233 234 cpsr &= ~(THREAD_EXCP_ALL << CPSR_F_SHIFT); 235 cpsr |= ((exceptions & THREAD_EXCP_ALL) << CPSR_F_SHIFT); 236 write_cpsr(cpsr); 237 } 238 #endif /*ARM32*/ 239 240 #ifdef ARM64 241 uint32_t thread_get_exceptions(void) 242 { 243 uint32_t daif = read_daif(); 244 245 return (daif >> DAIF_F_SHIFT) & THREAD_EXCP_ALL; 246 } 247 248 void thread_set_exceptions(uint32_t exceptions) 249 { 250 uint32_t daif = read_daif(); 251 252 daif &= ~(THREAD_EXCP_ALL << DAIF_F_SHIFT); 253 daif |= ((exceptions & THREAD_EXCP_ALL) << DAIF_F_SHIFT); 254 write_daif(daif); 255 } 256 #endif /*ARM64*/ 257 258 uint32_t thread_mask_exceptions(uint32_t exceptions) 259 { 260 uint32_t state = thread_get_exceptions(); 261 262 thread_set_exceptions(state | (exceptions & THREAD_EXCP_ALL)); 263 return state; 264 } 265 266 void thread_unmask_exceptions(uint32_t state) 267 { 268 thread_set_exceptions(state & THREAD_EXCP_ALL); 269 } 270 271 272 struct thread_core_local *thread_get_core_local(void) 273 { 274 uint32_t cpu_id = get_core_pos(); 275 276 /* 277 * IRQs must be disabled before playing with core_local since 278 * we otherwise may be rescheduled to a different core in the 279 * middle of this function. 280 */ 281 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 282 283 assert(cpu_id < CFG_TEE_CORE_NB_CORE); 284 return &thread_core_local[cpu_id]; 285 } 286 287 static void thread_lazy_save_ns_vfp(void) 288 { 289 #ifdef CFG_WITH_VFP 290 struct thread_ctx *thr = threads + thread_get_id(); 291 292 thr->vfp_state.ns_saved = false; 293 #if defined(ARM64) && defined(CFG_WITH_ARM_TRUSTED_FW) 294 /* 295 * ARM TF saves and restores CPACR_EL1, so we must assume NS world 296 * uses VFP and always preserve the register file when secure world 297 * is about to use it 298 */ 299 thr->vfp_state.ns.force_save = true; 300 #endif 301 vfp_lazy_save_state_init(&thr->vfp_state.ns); 302 #endif /*CFG_WITH_VFP*/ 303 } 304 305 static void thread_lazy_restore_ns_vfp(void) 306 { 307 #ifdef CFG_WITH_VFP 308 struct thread_ctx *thr = threads + thread_get_id(); 309 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 310 311 assert(!thr->vfp_state.sec_lazy_saved && !thr->vfp_state.sec_saved); 312 313 if (tuv && tuv->lazy_saved && !tuv->saved) { 314 vfp_lazy_save_state_final(&tuv->vfp); 315 tuv->saved = true; 316 } 317 318 vfp_lazy_restore_state(&thr->vfp_state.ns, thr->vfp_state.ns_saved); 319 thr->vfp_state.ns_saved = false; 320 #endif /*CFG_WITH_VFP*/ 321 } 322 323 #ifdef ARM32 324 static void init_regs(struct thread_ctx *thread, 325 struct thread_smc_args *args) 326 { 327 thread->regs.pc = (uint32_t)thread_std_smc_entry; 328 329 /* 330 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 331 * abort and unmasked FIQ. 332 */ 333 thread->regs.cpsr = read_cpsr() & ARM32_CPSR_E; 334 thread->regs.cpsr |= CPSR_MODE_SVC | CPSR_I | CPSR_A; 335 /* Enable thumb mode if it's a thumb instruction */ 336 if (thread->regs.pc & 1) 337 thread->regs.cpsr |= CPSR_T; 338 /* Reinitialize stack pointer */ 339 thread->regs.svc_sp = thread->stack_va_end; 340 341 /* 342 * Copy arguments into context. This will make the 343 * arguments appear in r0-r7 when thread is started. 344 */ 345 thread->regs.r0 = args->a0; 346 thread->regs.r1 = args->a1; 347 thread->regs.r2 = args->a2; 348 thread->regs.r3 = args->a3; 349 thread->regs.r4 = args->a4; 350 thread->regs.r5 = args->a5; 351 thread->regs.r6 = args->a6; 352 thread->regs.r7 = args->a7; 353 } 354 #endif /*ARM32*/ 355 356 #ifdef ARM64 357 static void init_regs(struct thread_ctx *thread, 358 struct thread_smc_args *args) 359 { 360 thread->regs.pc = (uint64_t)thread_std_smc_entry; 361 362 /* 363 * Stdcalls starts in SVC mode with masked IRQ, masked Asynchronous 364 * abort and unmasked FIQ. 365 */ 366 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 367 DAIFBIT_IRQ | DAIFBIT_ABT); 368 /* Reinitialize stack pointer */ 369 thread->regs.sp = thread->stack_va_end; 370 371 /* 372 * Copy arguments into context. This will make the 373 * arguments appear in x0-x7 when thread is started. 374 */ 375 thread->regs.x[0] = args->a0; 376 thread->regs.x[1] = args->a1; 377 thread->regs.x[2] = args->a2; 378 thread->regs.x[3] = args->a3; 379 thread->regs.x[4] = args->a4; 380 thread->regs.x[5] = args->a5; 381 thread->regs.x[6] = args->a6; 382 thread->regs.x[7] = args->a7; 383 } 384 #endif /*ARM64*/ 385 386 void thread_init_boot_thread(void) 387 { 388 struct thread_core_local *l = thread_get_core_local(); 389 size_t n; 390 391 for (n = 0; n < CFG_NUM_THREADS; n++) 392 TAILQ_INIT(&threads[n].mutexes); 393 394 for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) 395 thread_core_local[n].curr_thread = -1; 396 397 l->curr_thread = 0; 398 threads[0].state = THREAD_STATE_ACTIVE; 399 } 400 401 void thread_clr_boot_thread(void) 402 { 403 struct thread_core_local *l = thread_get_core_local(); 404 405 assert(l->curr_thread >= 0 && l->curr_thread < CFG_NUM_THREADS); 406 assert(threads[l->curr_thread].state == THREAD_STATE_ACTIVE); 407 assert(TAILQ_EMPTY(&threads[l->curr_thread].mutexes)); 408 threads[l->curr_thread].state = THREAD_STATE_FREE; 409 l->curr_thread = -1; 410 } 411 412 static void thread_alloc_and_run(struct thread_smc_args *args) 413 { 414 size_t n; 415 struct thread_core_local *l = thread_get_core_local(); 416 bool found_thread = false; 417 418 assert(l->curr_thread == -1); 419 420 lock_global(); 421 422 for (n = 0; n < CFG_NUM_THREADS; n++) { 423 if (threads[n].state == THREAD_STATE_FREE) { 424 threads[n].state = THREAD_STATE_ACTIVE; 425 found_thread = true; 426 break; 427 } 428 } 429 430 unlock_global(); 431 432 if (!found_thread) { 433 args->a0 = TEESMC_RETURN_ETHREAD_LIMIT; 434 return; 435 } 436 437 l->curr_thread = n; 438 439 threads[n].flags = 0; 440 init_regs(threads + n, args); 441 442 /* Save Hypervisor Client ID */ 443 threads[n].hyp_clnt_id = args->a7; 444 445 thread_lazy_save_ns_vfp(); 446 thread_resume(&threads[n].regs); 447 } 448 449 #ifdef ARM32 450 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 451 struct thread_smc_args *args) 452 { 453 /* 454 * Update returned values from RPC, values will appear in 455 * r0-r3 when thread is resumed. 456 */ 457 regs->r0 = args->a0; 458 regs->r1 = args->a1; 459 regs->r2 = args->a2; 460 regs->r3 = args->a3; 461 } 462 #endif /*ARM32*/ 463 464 #ifdef ARM64 465 static void copy_a0_to_a3(struct thread_ctx_regs *regs, 466 struct thread_smc_args *args) 467 { 468 /* 469 * Update returned values from RPC, values will appear in 470 * x0-x3 when thread is resumed. 471 */ 472 regs->x[0] = args->a0; 473 regs->x[1] = args->a1; 474 regs->x[2] = args->a2; 475 regs->x[3] = args->a3; 476 } 477 #endif /*ARM64*/ 478 479 static void thread_resume_from_rpc(struct thread_smc_args *args) 480 { 481 size_t n = args->a3; /* thread id */ 482 struct thread_core_local *l = thread_get_core_local(); 483 uint32_t rv = 0; 484 485 assert(l->curr_thread == -1); 486 487 lock_global(); 488 489 if (n < CFG_NUM_THREADS && 490 threads[n].state == THREAD_STATE_SUSPENDED && 491 args->a7 == threads[n].hyp_clnt_id) 492 threads[n].state = THREAD_STATE_ACTIVE; 493 else 494 rv = TEESMC_RETURN_ERESUME; 495 496 unlock_global(); 497 498 if (rv) { 499 args->a0 = rv; 500 return; 501 } 502 503 l->curr_thread = n; 504 505 if (threads[n].have_user_map) 506 core_mmu_set_user_map(&threads[n].user_map); 507 508 /* 509 * Return from RPC to request service of an IRQ must not 510 * get parameters from non-secure world. 511 */ 512 if (threads[n].flags & THREAD_FLAGS_COPY_ARGS_ON_RETURN) { 513 copy_a0_to_a3(&threads[n].regs, args); 514 threads[n].flags &= ~THREAD_FLAGS_COPY_ARGS_ON_RETURN; 515 } 516 517 thread_lazy_save_ns_vfp(); 518 thread_resume(&threads[n].regs); 519 } 520 521 void thread_handle_fast_smc(struct thread_smc_args *args) 522 { 523 thread_check_canaries(); 524 thread_fast_smc_handler_ptr(args); 525 /* Fast handlers must not unmask any exceptions */ 526 assert(thread_get_exceptions() == THREAD_EXCP_ALL); 527 } 528 529 void thread_handle_std_smc(struct thread_smc_args *args) 530 { 531 thread_check_canaries(); 532 533 if (args->a0 == TEESMC32_CALL_RETURN_FROM_RPC) 534 thread_resume_from_rpc(args); 535 else 536 thread_alloc_and_run(args); 537 } 538 539 /* Helper routine for the assembly function thread_std_smc_entry() */ 540 void __thread_std_smc_entry(struct thread_smc_args *args) 541 { 542 struct thread_ctx *thr = threads + thread_get_id(); 543 544 if (!thr->rpc_arg) { 545 paddr_t parg; 546 void *arg; 547 548 parg = thread_rpc_alloc_arg( 549 TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 550 if (!parg || !ALIGNMENT_IS_OK(parg, struct teesmc32_arg) || 551 core_pa2va(parg, &arg)) { 552 thread_rpc_free_arg(parg); 553 args->a0 = TEESMC_RETURN_ENOMEM; 554 return; 555 } 556 557 thr->rpc_arg = arg; 558 thr->rpc_parg = parg; 559 } 560 561 thread_std_smc_handler_ptr(args); 562 } 563 564 void thread_handle_abort(uint32_t abort_type, struct thread_abort_regs *regs) 565 { 566 thread_abort_handler_ptr(abort_type, regs); 567 } 568 569 void *thread_get_tmp_sp(void) 570 { 571 struct thread_core_local *l = thread_get_core_local(); 572 573 return (void *)l->tmp_stack_va_end; 574 } 575 576 #ifdef ARM64 577 vaddr_t thread_get_saved_thread_sp(void) 578 { 579 struct thread_core_local *l = thread_get_core_local(); 580 int ct = l->curr_thread; 581 582 assert(ct != -1); 583 return threads[ct].kern_sp; 584 } 585 #endif /*ARM64*/ 586 587 void thread_state_free(void) 588 { 589 struct thread_core_local *l = thread_get_core_local(); 590 int ct = l->curr_thread; 591 592 assert(ct != -1); 593 assert(TAILQ_EMPTY(&threads[ct].mutexes)); 594 595 thread_lazy_restore_ns_vfp(); 596 597 lock_global(); 598 599 assert(threads[ct].state == THREAD_STATE_ACTIVE); 600 threads[ct].state = THREAD_STATE_FREE; 601 threads[ct].flags = 0; 602 l->curr_thread = -1; 603 604 unlock_global(); 605 } 606 607 #ifdef ARM32 608 static bool is_from_user(uint32_t cpsr) 609 { 610 return (cpsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 611 } 612 #endif 613 614 #ifdef ARM64 615 static bool is_from_user(uint32_t cpsr) 616 { 617 if (cpsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 618 return true; 619 if (((cpsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 620 SPSR_64_MODE_EL0) 621 return true; 622 return false; 623 } 624 #endif 625 626 int thread_state_suspend(uint32_t flags, uint32_t cpsr, vaddr_t pc) 627 { 628 struct thread_core_local *l = thread_get_core_local(); 629 int ct = l->curr_thread; 630 631 assert(ct != -1); 632 633 thread_check_canaries(); 634 635 if (is_from_user(cpsr)) 636 thread_user_save_vfp(); 637 thread_lazy_restore_ns_vfp(); 638 639 lock_global(); 640 641 assert(threads[ct].state == THREAD_STATE_ACTIVE); 642 threads[ct].flags |= flags; 643 threads[ct].regs.cpsr = cpsr; 644 threads[ct].regs.pc = pc; 645 threads[ct].state = THREAD_STATE_SUSPENDED; 646 647 threads[ct].have_user_map = core_mmu_user_mapping_is_active(); 648 if (threads[ct].have_user_map) { 649 core_mmu_get_user_map(&threads[ct].user_map); 650 core_mmu_set_user_map(NULL); 651 } 652 653 654 l->curr_thread = -1; 655 656 unlock_global(); 657 658 return ct; 659 } 660 661 #ifdef ARM32 662 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 663 { 664 l->tmp_stack_va_end = sp; 665 thread_set_irq_sp(sp); 666 thread_set_fiq_sp(sp); 667 } 668 669 static void set_abt_stack(struct thread_core_local *l __unused, vaddr_t sp) 670 { 671 thread_set_abt_sp(sp); 672 } 673 #endif /*ARM32*/ 674 675 #ifdef ARM64 676 static void set_tmp_stack(struct thread_core_local *l, vaddr_t sp) 677 { 678 /* 679 * We're already using the tmp stack when this function is called 680 * so there's no need to assign it to any stack pointer. However, 681 * we'll need to restore it at different times so store it here. 682 */ 683 l->tmp_stack_va_end = sp; 684 } 685 686 static void set_abt_stack(struct thread_core_local *l, vaddr_t sp) 687 { 688 l->abt_stack_va_end = sp; 689 } 690 #endif /*ARM64*/ 691 692 bool thread_init_stack(uint32_t thread_id, vaddr_t sp) 693 { 694 if (thread_id >= CFG_NUM_THREADS) 695 return false; 696 threads[thread_id].stack_va_end = sp; 697 return true; 698 } 699 700 int thread_get_id(void) 701 { 702 /* thread_get_core_local() requires IRQs to be disabled */ 703 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 704 struct thread_core_local *l; 705 int ct; 706 707 l = thread_get_core_local(); 708 ct = l->curr_thread; 709 assert((ct >= 0) && (ct < CFG_NUM_THREADS)); 710 711 thread_unmask_exceptions(exceptions); 712 return ct; 713 } 714 715 static void init_handlers(const struct thread_handlers *handlers) 716 { 717 thread_std_smc_handler_ptr = handlers->std_smc; 718 thread_fast_smc_handler_ptr = handlers->fast_smc; 719 thread_fiq_handler_ptr = handlers->fiq; 720 thread_svc_handler_ptr = handlers->svc; 721 thread_abort_handler_ptr = handlers->abort; 722 thread_cpu_on_handler_ptr = handlers->cpu_on; 723 thread_cpu_off_handler_ptr = handlers->cpu_off; 724 thread_cpu_suspend_handler_ptr = handlers->cpu_suspend; 725 thread_cpu_resume_handler_ptr = handlers->cpu_resume; 726 thread_system_off_handler_ptr = handlers->system_off; 727 thread_system_reset_handler_ptr = handlers->system_reset; 728 } 729 730 731 #ifdef CFG_WITH_PAGER 732 static void init_thread_stacks(void) 733 { 734 size_t n; 735 736 /* 737 * Allocate virtual memory for thread stacks. 738 */ 739 for (n = 0; n < CFG_NUM_THREADS; n++) { 740 tee_mm_entry_t *mm; 741 vaddr_t sp; 742 743 /* Find vmem for thread stack and its protection gap */ 744 mm = tee_mm_alloc(&tee_mm_vcore, 745 SMALL_PAGE_SIZE + STACK_THREAD_SIZE); 746 TEE_ASSERT(mm); 747 748 /* Claim eventual physical page */ 749 tee_pager_add_pages(tee_mm_get_smem(mm), tee_mm_get_size(mm), 750 true); 751 752 /* Realloc both protection vmem and stack vmem separately */ 753 sp = tee_mm_get_smem(mm); 754 tee_mm_free(mm); 755 mm = tee_mm_alloc2(&tee_mm_vcore, sp, SMALL_PAGE_SIZE); 756 TEE_ASSERT(mm); 757 mm = tee_mm_alloc2(&tee_mm_vcore, sp + SMALL_PAGE_SIZE, 758 STACK_THREAD_SIZE); 759 TEE_ASSERT(mm); 760 761 /* init effective stack */ 762 sp = tee_mm_get_smem(mm) + tee_mm_get_bytes(mm); 763 if (!thread_init_stack(n, sp)) 764 panic(); 765 766 /* Add the area to the pager */ 767 tee_pager_add_area(mm, TEE_PAGER_AREA_RW, NULL, NULL); 768 } 769 } 770 #else 771 static void init_thread_stacks(void) 772 { 773 size_t n; 774 775 /* Assign the thread stacks */ 776 for (n = 0; n < CFG_NUM_THREADS; n++) { 777 if (!thread_init_stack(n, GET_STACK(stack_thread[n]))) 778 panic(); 779 } 780 } 781 #endif /*CFG_WITH_PAGER*/ 782 783 void thread_init_primary(const struct thread_handlers *handlers) 784 { 785 /* 786 * The COMPILE_TIME_ASSERT only works in function context. These 787 * checks verifies that the offsets used in assembly code matches 788 * what's used in C code. 789 */ 790 #ifdef ARM32 791 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r0) == 792 THREAD_SVC_REG_R0_OFFS); 793 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r1) == 794 THREAD_SVC_REG_R1_OFFS); 795 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r2) == 796 THREAD_SVC_REG_R2_OFFS); 797 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r3) == 798 THREAD_SVC_REG_R3_OFFS); 799 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r4) == 800 THREAD_SVC_REG_R4_OFFS); 801 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r5) == 802 THREAD_SVC_REG_R5_OFFS); 803 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r6) == 804 THREAD_SVC_REG_R6_OFFS); 805 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, r7) == 806 THREAD_SVC_REG_R7_OFFS); 807 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, lr) == 808 THREAD_SVC_REG_LR_OFFS); 809 COMPILE_TIME_ASSERT(offsetof(struct thread_svc_regs, spsr) == 810 THREAD_SVC_REG_SPSR_OFFS); 811 #endif /*ARM32*/ 812 #ifdef ARM64 813 /* struct thread_abort_regs */ 814 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, x22) == 815 THREAD_ABT_REG_X_OFFS(22)); 816 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, elr) == 817 THREAD_ABT_REG_ELR_OFFS); 818 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, spsr) == 819 THREAD_ABT_REG_SPSR_OFFS); 820 COMPILE_TIME_ASSERT(offsetof(struct thread_abort_regs, sp_el0) == 821 THREAD_ABT_REG_SP_EL0_OFFS); 822 COMPILE_TIME_ASSERT(sizeof(struct thread_abort_regs) == 823 THREAD_ABT_REGS_SIZE); 824 825 /* struct thread_ctx */ 826 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx, kern_sp) == 827 THREAD_CTX_KERN_SP_OFFSET); 828 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx) == THREAD_CTX_SIZE); 829 830 /* struct thread_ctx_regs */ 831 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, sp) == 832 THREAD_CTX_REGS_SP_OFFSET); 833 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, pc) == 834 THREAD_CTX_REGS_PC_OFFSET); 835 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, cpsr) == 836 THREAD_CTX_REGS_SPSR_OFFSET); 837 COMPILE_TIME_ASSERT(offsetof(struct thread_ctx_regs, x[23]) == 838 THREAD_CTX_REGS_X_OFFSET(23)); 839 COMPILE_TIME_ASSERT(sizeof(struct thread_ctx_regs) == 840 THREAD_CTX_REGS_SIZE); 841 842 /* struct thread_user_mode_rec */ 843 COMPILE_TIME_ASSERT( 844 offsetof(struct thread_user_mode_rec, exit_status0_ptr) == 845 THREAD_USER_MODE_REC_EXIT_STATUS0_PTR_OFFSET); 846 COMPILE_TIME_ASSERT( 847 offsetof(struct thread_user_mode_rec, exit_status1_ptr) == 848 THREAD_USER_MODE_REC_EXIT_STATUS1_PTR_OFFSET); 849 COMPILE_TIME_ASSERT( 850 offsetof(struct thread_user_mode_rec, x[1]) == 851 THREAD_USER_MODE_REC_X_OFFSET(20)); 852 COMPILE_TIME_ASSERT(sizeof(struct thread_user_mode_rec) == 853 THREAD_USER_MODE_REC_SIZE); 854 855 /* struct thread_core_local */ 856 COMPILE_TIME_ASSERT( 857 offsetof(struct thread_core_local, tmp_stack_va_end) == 858 THREAD_CORE_LOCAL_TMP_STACK_VA_END_OFFSET); 859 COMPILE_TIME_ASSERT( 860 offsetof(struct thread_core_local, curr_thread) == 861 THREAD_CORE_LOCAL_CURR_THREAD_OFFSET); 862 COMPILE_TIME_ASSERT( 863 offsetof(struct thread_core_local, flags) == 864 THREAD_CORE_LOCAL_FLAGS_OFFSET); 865 COMPILE_TIME_ASSERT( 866 offsetof(struct thread_core_local, abt_stack_va_end) == 867 THREAD_CORE_LOCAL_ABT_STACK_VA_END_OFFSET); 868 COMPILE_TIME_ASSERT( 869 offsetof(struct thread_core_local, x[3]) == 870 THREAD_CORE_LOCAL_X_OFFSET(3)); 871 COMPILE_TIME_ASSERT(sizeof(struct thread_core_local) == 872 THREAD_CORE_LOCAL_SIZE); 873 874 #endif /*ARM64*/ 875 876 init_handlers(handlers); 877 878 /* Initialize canaries around the stacks */ 879 init_canaries(); 880 881 init_thread_stacks(); 882 } 883 884 static void init_sec_mon(size_t pos __maybe_unused) 885 { 886 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 887 /* Initialize secure monitor */ 888 sm_init(GET_STACK(stack_sm[pos])); 889 sm_set_entry_vector(thread_vector_table); 890 #endif 891 } 892 893 void thread_init_per_cpu(void) 894 { 895 size_t pos = get_core_pos(); 896 struct thread_core_local *l = thread_get_core_local(); 897 898 init_sec_mon(pos); 899 900 set_tmp_stack(l, GET_STACK(stack_tmp[pos])); 901 set_abt_stack(l, GET_STACK(stack_abt[pos])); 902 903 thread_init_vbar(); 904 } 905 906 void thread_set_tsd(void *tsd) 907 { 908 /* thread_get_core_local() requires IRQs to be disabled */ 909 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 910 struct thread_core_local *l; 911 int ct; 912 913 l = thread_get_core_local(); 914 ct = l->curr_thread; 915 916 assert(ct != -1); 917 assert(threads[ct].state == THREAD_STATE_ACTIVE); 918 threads[ct].tsd = tsd; 919 920 thread_unmask_exceptions(exceptions); 921 } 922 923 void *thread_get_tsd(void) 924 { 925 /* thread_get_core_local() requires IRQs to be disabled */ 926 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 927 struct thread_core_local *l; 928 int ct; 929 void *tsd; 930 931 l = thread_get_core_local(); 932 ct = l->curr_thread; 933 934 if (ct == -1 || threads[ct].state != THREAD_STATE_ACTIVE) 935 tsd = NULL; 936 else 937 tsd = threads[ct].tsd; 938 939 thread_unmask_exceptions(exceptions); 940 return tsd; 941 } 942 943 struct thread_ctx_regs *thread_get_ctx_regs(void) 944 { 945 struct thread_core_local *l = thread_get_core_local(); 946 947 assert(l->curr_thread != -1); 948 return &threads[l->curr_thread].regs; 949 } 950 951 void thread_set_irq(bool enable) 952 { 953 /* thread_get_core_local() requires IRQs to be disabled */ 954 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 955 struct thread_core_local *l; 956 957 l = thread_get_core_local(); 958 959 assert(l->curr_thread != -1); 960 961 if (enable) { 962 threads[l->curr_thread].flags |= THREAD_FLAGS_IRQ_ENABLE; 963 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 964 } else { 965 /* 966 * No need to disable IRQ here since it's already disabled 967 * above. 968 */ 969 threads[l->curr_thread].flags &= ~THREAD_FLAGS_IRQ_ENABLE; 970 } 971 } 972 973 void thread_restore_irq(void) 974 { 975 /* thread_get_core_local() requires IRQs to be disabled */ 976 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 977 struct thread_core_local *l; 978 979 l = thread_get_core_local(); 980 981 assert(l->curr_thread != -1); 982 983 if (threads[l->curr_thread].flags & THREAD_FLAGS_IRQ_ENABLE) 984 thread_set_exceptions(exceptions & ~THREAD_EXCP_IRQ); 985 } 986 987 #ifdef CFG_WITH_VFP 988 uint32_t thread_kernel_enable_vfp(void) 989 { 990 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); 991 struct thread_ctx *thr = threads + thread_get_id(); 992 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 993 994 assert(!vfp_is_enabled()); 995 996 if (!thr->vfp_state.ns_saved) { 997 vfp_lazy_save_state_final(&thr->vfp_state.ns); 998 thr->vfp_state.ns_saved = true; 999 } else if (thr->vfp_state.sec_lazy_saved && 1000 !thr->vfp_state.sec_saved) { 1001 /* 1002 * This happens when we're handling an abort while the 1003 * thread was using the VFP state. 1004 */ 1005 vfp_lazy_save_state_final(&thr->vfp_state.sec); 1006 thr->vfp_state.sec_saved = true; 1007 } else if (tuv && tuv->lazy_saved && !tuv->saved) { 1008 /* 1009 * This can happen either during syscall or abort 1010 * processing (while processing a syscall). 1011 */ 1012 vfp_lazy_save_state_final(&tuv->vfp); 1013 tuv->saved = true; 1014 } 1015 1016 vfp_enable(); 1017 return exceptions; 1018 } 1019 1020 void thread_kernel_disable_vfp(uint32_t state) 1021 { 1022 uint32_t exceptions; 1023 1024 assert(vfp_is_enabled()); 1025 1026 vfp_disable(); 1027 exceptions = thread_get_exceptions(); 1028 assert(exceptions & THREAD_EXCP_IRQ); 1029 exceptions &= ~THREAD_EXCP_IRQ; 1030 exceptions |= state & THREAD_EXCP_IRQ; 1031 thread_set_exceptions(exceptions); 1032 } 1033 1034 void thread_kernel_save_vfp(void) 1035 { 1036 struct thread_ctx *thr = threads + thread_get_id(); 1037 1038 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1039 if (vfp_is_enabled()) { 1040 vfp_lazy_save_state_init(&thr->vfp_state.sec); 1041 thr->vfp_state.sec_lazy_saved = true; 1042 } 1043 } 1044 1045 void thread_kernel_restore_vfp(void) 1046 { 1047 struct thread_ctx *thr = threads + thread_get_id(); 1048 1049 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1050 assert(!vfp_is_enabled()); 1051 if (thr->vfp_state.sec_lazy_saved) { 1052 vfp_lazy_restore_state(&thr->vfp_state.sec, 1053 thr->vfp_state.sec_saved); 1054 thr->vfp_state.sec_saved = false; 1055 thr->vfp_state.sec_lazy_saved = false; 1056 } 1057 } 1058 1059 void thread_user_enable_vfp(struct thread_user_vfp_state *uvfp) 1060 { 1061 struct thread_ctx *thr = threads + thread_get_id(); 1062 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 1063 1064 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1065 assert(!vfp_is_enabled()); 1066 1067 if (!thr->vfp_state.ns_saved) { 1068 vfp_lazy_save_state_final(&thr->vfp_state.ns); 1069 thr->vfp_state.ns_saved = true; 1070 } else if (tuv && uvfp != tuv) { 1071 if (tuv->lazy_saved && !tuv->saved) { 1072 vfp_lazy_save_state_final(&tuv->vfp); 1073 tuv->saved = true; 1074 } 1075 } 1076 1077 if (uvfp->lazy_saved) 1078 vfp_lazy_restore_state(&uvfp->vfp, uvfp->saved); 1079 uvfp->lazy_saved = false; 1080 uvfp->saved = false; 1081 1082 thr->vfp_state.uvfp = uvfp; 1083 vfp_enable(); 1084 } 1085 1086 void thread_user_save_vfp(void) 1087 { 1088 struct thread_ctx *thr = threads + thread_get_id(); 1089 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 1090 1091 assert(thread_get_exceptions() & THREAD_EXCP_IRQ); 1092 if (!vfp_is_enabled()) 1093 return; 1094 1095 assert(tuv && !tuv->lazy_saved && !tuv->saved); 1096 vfp_lazy_save_state_init(&tuv->vfp); 1097 tuv->lazy_saved = true; 1098 } 1099 1100 void thread_user_clear_vfp(struct thread_user_vfp_state *uvfp) 1101 { 1102 struct thread_ctx *thr = threads + thread_get_id(); 1103 1104 if (uvfp == thr->vfp_state.uvfp) 1105 thr->vfp_state.uvfp = NULL; 1106 uvfp->lazy_saved = false; 1107 uvfp->saved = false; 1108 } 1109 #endif /*CFG_WITH_VFP*/ 1110 1111 #ifdef ARM32 1112 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1113 { 1114 uint32_t s; 1115 1116 if (!is_32bit) 1117 return false; 1118 1119 s = read_spsr(); 1120 s &= ~(CPSR_MODE_MASK | CPSR_T | CPSR_IT_MASK1 | CPSR_IT_MASK2); 1121 s |= CPSR_MODE_USR; 1122 if (entry_func & 1) 1123 s |= CPSR_T; 1124 *spsr = s; 1125 return true; 1126 } 1127 #endif 1128 1129 #ifdef ARM64 1130 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 1131 { 1132 uint32_t s; 1133 1134 if (is_32bit) { 1135 s = read_daif() & (SPSR_32_AIF_MASK << SPSR_32_AIF_SHIFT); 1136 s |= SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT; 1137 s |= (entry_func & SPSR_32_T_MASK) << SPSR_32_T_SHIFT; 1138 } else { 1139 s = read_daif() & (SPSR_64_DAIF_MASK << SPSR_64_DAIF_SHIFT); 1140 } 1141 1142 *spsr = s; 1143 return true; 1144 } 1145 #endif 1146 1147 uint32_t thread_enter_user_mode(unsigned long a0, unsigned long a1, 1148 unsigned long a2, unsigned long a3, unsigned long user_sp, 1149 unsigned long entry_func, bool is_32bit, 1150 uint32_t *exit_status0, uint32_t *exit_status1) 1151 { 1152 uint32_t spsr; 1153 1154 if (!get_spsr(is_32bit, entry_func, &spsr)) { 1155 *exit_status0 = 1; /* panic */ 1156 *exit_status1 = 0xbadbadba; 1157 return 0; 1158 } 1159 return __thread_enter_user_mode(a0, a1, a2, a3, user_sp, entry_func, 1160 spsr, exit_status0, exit_status1); 1161 } 1162 1163 void thread_add_mutex(struct mutex *m) 1164 { 1165 struct thread_core_local *l = thread_get_core_local(); 1166 int ct = l->curr_thread; 1167 1168 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1169 assert(m->owner_id == -1); 1170 m->owner_id = ct; 1171 TAILQ_INSERT_TAIL(&threads[ct].mutexes, m, link); 1172 } 1173 1174 void thread_rem_mutex(struct mutex *m) 1175 { 1176 struct thread_core_local *l = thread_get_core_local(); 1177 int ct = l->curr_thread; 1178 1179 assert(ct != -1 && threads[ct].state == THREAD_STATE_ACTIVE); 1180 assert(m->owner_id == ct); 1181 m->owner_id = -1; 1182 TAILQ_REMOVE(&threads[ct].mutexes, m, link); 1183 } 1184 1185 paddr_t thread_rpc_alloc_arg(size_t size) 1186 { 1187 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1188 TEESMC_RETURN_RPC_ALLOC_ARG, size}; 1189 1190 thread_rpc(rpc_args); 1191 return rpc_args[1]; 1192 } 1193 1194 paddr_t thread_rpc_alloc_payload(size_t size) 1195 { 1196 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1197 TEESMC_RETURN_RPC_ALLOC_PAYLOAD, size}; 1198 1199 thread_rpc(rpc_args); 1200 return rpc_args[1]; 1201 } 1202 1203 void thread_rpc_free_arg(paddr_t arg) 1204 { 1205 if (arg) { 1206 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1207 TEESMC_RETURN_RPC_FREE_ARG, arg}; 1208 1209 thread_rpc(rpc_args); 1210 } 1211 } 1212 void thread_rpc_free_payload(paddr_t payload) 1213 { 1214 if (payload) { 1215 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1216 TEESMC_RETURN_RPC_FREE_PAYLOAD, payload}; 1217 1218 thread_rpc(rpc_args); 1219 } 1220 } 1221 1222 static uint32_t rpc_cmd_nolock(uint32_t cmd, size_t num_params, 1223 struct teesmc32_param *params) 1224 { 1225 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 0 }; 1226 struct thread_ctx *thr = threads + thread_get_id(); 1227 struct teesmc32_arg *arg = thr->rpc_arg; 1228 paddr_t parg = thr->rpc_parg; 1229 const size_t params_size = sizeof(struct teesmc32_param) * num_params; 1230 size_t n; 1231 1232 TEE_ASSERT(arg && parg && num_params <= RPC_MAX_PARAMS); 1233 1234 memset(arg, 0, TEESMC32_GET_ARG_SIZE(RPC_MAX_PARAMS)); 1235 arg->cmd = cmd; 1236 arg->ret = TEE_ERROR_GENERIC; /* in case value isn't updated */ 1237 arg->num_params = num_params; 1238 memcpy(TEESMC32_GET_PARAMS(arg), params, params_size); 1239 1240 rpc_args[0] = TEESMC_RETURN_RPC_CMD; 1241 rpc_args[1] = parg; 1242 thread_rpc(rpc_args); 1243 1244 for (n = 0; n < num_params; n++) { 1245 switch (params[n].attr & TEESMC_ATTR_TYPE_MASK) { 1246 case TEESMC_ATTR_TYPE_VALUE_OUTPUT: 1247 case TEESMC_ATTR_TYPE_VALUE_INOUT: 1248 case TEESMC_ATTR_TYPE_MEMREF_OUTPUT: 1249 case TEESMC_ATTR_TYPE_MEMREF_INOUT: 1250 memcpy(params + n, TEESMC32_GET_PARAMS(arg) + n, 1251 sizeof(struct teesmc32_param)); 1252 break; 1253 default: 1254 break; 1255 } 1256 } 1257 1258 return arg->ret; 1259 } 1260 1261 uint32_t thread_rpc_cmd(uint32_t cmd, size_t num_params, 1262 struct teesmc32_param *params) 1263 { 1264 uint32_t ret; 1265 1266 ret = rpc_cmd_nolock(cmd, num_params, params); 1267 1268 return ret; 1269 } 1270 1271 void thread_optee_rpc_alloc_payload(size_t size, paddr_t *payload, 1272 paddr_t *cookie) 1273 { 1274 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] = { 1275 TEESMC_RETURN_OPTEE_RPC_ALLOC_PAYLOAD, size}; 1276 1277 thread_rpc(rpc_args); 1278 if (payload) 1279 *payload = rpc_args[1]; 1280 if (cookie) 1281 *cookie = rpc_args[2]; 1282 } 1283 1284 void thread_optee_rpc_free_payload(paddr_t cookie) 1285 { 1286 uint32_t rpc_args[THREAD_RPC_NUM_ARGS] ={ 1287 TEESMC_RETURN_OPTEE_RPC_FREE_PAYLOAD, cookie}; 1288 1289 thread_rpc(rpc_args); 1290 } 1291