1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2022, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * Copyright (c) 2020-2021, Arm Limited 6 */ 7 8 #include <platform_config.h> 9 10 #include <arm.h> 11 #include <assert.h> 12 #include <config.h> 13 #include <io.h> 14 #include <keep.h> 15 #include <kernel/asan.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/linker.h> 19 #include <kernel/lockdep.h> 20 #include <kernel/misc.h> 21 #include <kernel/panic.h> 22 #include <kernel/spinlock.h> 23 #include <kernel/spmc_sp_handler.h> 24 #include <kernel/tee_ta_manager.h> 25 #include <kernel/thread.h> 26 #include <kernel/thread_private.h> 27 #include <kernel/user_access.h> 28 #include <kernel/user_mode_ctx.h> 29 #include <kernel/virtualization.h> 30 #include <mm/core_memprot.h> 31 #include <mm/mobj.h> 32 #include <mm/tee_mm.h> 33 #include <mm/tee_pager.h> 34 #include <mm/vm.h> 35 #include <sm/sm.h> 36 #include <smccc.h> 37 #include <trace.h> 38 #include <util.h> 39 40 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 41 static vaddr_t thread_user_kcode_va __nex_bss; 42 long thread_user_kcode_offset __nex_bss; 43 static size_t thread_user_kcode_size __nex_bss; 44 #endif 45 46 #if defined(CFG_CORE_UNMAP_CORE_AT_EL0) && \ 47 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 48 long thread_user_kdata_sp_offset __nex_bss; 49 static uint8_t thread_user_kdata_page[ 50 ROUNDUP(sizeof(struct thread_core_local) * CFG_TEE_CORE_NB_CORE, 51 SMALL_PAGE_SIZE)] 52 __aligned(SMALL_PAGE_SIZE) 53 #ifndef CFG_NS_VIRTUALIZATION 54 __section(".nozi.kdata_page"); 55 #else 56 __section(".nex_nozi.kdata_page"); 57 #endif 58 #endif 59 60 #ifdef ARM32 61 uint32_t __nostackcheck thread_get_exceptions(void) 62 { 63 uint32_t cpsr = read_cpsr(); 64 65 return (cpsr >> CPSR_F_SHIFT) & THREAD_EXCP_ALL; 66 } 67 68 void __nostackcheck thread_set_exceptions(uint32_t exceptions) 69 { 70 uint32_t cpsr = read_cpsr(); 71 72 /* Foreign interrupts must not be unmasked while holding a spinlock */ 73 if (!(exceptions & THREAD_EXCP_FOREIGN_INTR)) 74 assert_have_no_spinlock(); 75 76 cpsr &= ~(THREAD_EXCP_ALL << CPSR_F_SHIFT); 77 cpsr |= ((exceptions & THREAD_EXCP_ALL) << CPSR_F_SHIFT); 78 79 barrier(); 80 write_cpsr(cpsr); 81 barrier(); 82 } 83 #endif /*ARM32*/ 84 85 #ifdef ARM64 86 uint32_t __nostackcheck thread_get_exceptions(void) 87 { 88 uint32_t daif = read_daif(); 89 90 return (daif >> DAIF_F_SHIFT) & THREAD_EXCP_ALL; 91 } 92 93 void __nostackcheck thread_set_exceptions(uint32_t exceptions) 94 { 95 uint32_t daif = read_daif(); 96 97 /* Foreign interrupts must not be unmasked while holding a spinlock */ 98 if (!(exceptions & THREAD_EXCP_FOREIGN_INTR)) 99 assert_have_no_spinlock(); 100 101 daif &= ~(THREAD_EXCP_ALL << DAIF_F_SHIFT); 102 daif |= ((exceptions & THREAD_EXCP_ALL) << DAIF_F_SHIFT); 103 104 barrier(); 105 write_daif(daif); 106 barrier(); 107 } 108 #endif /*ARM64*/ 109 110 uint32_t __nostackcheck thread_mask_exceptions(uint32_t exceptions) 111 { 112 uint32_t state = thread_get_exceptions(); 113 114 thread_set_exceptions(state | (exceptions & THREAD_EXCP_ALL)); 115 return state; 116 } 117 118 void __nostackcheck thread_unmask_exceptions(uint32_t state) 119 { 120 thread_set_exceptions(state & THREAD_EXCP_ALL); 121 } 122 123 static void thread_lazy_save_ns_vfp(void) 124 { 125 #ifdef CFG_WITH_VFP 126 struct thread_ctx *thr = threads + thread_get_id(); 127 128 thr->vfp_state.ns_saved = false; 129 vfp_lazy_save_state_init(&thr->vfp_state.ns); 130 #endif /*CFG_WITH_VFP*/ 131 } 132 133 static void thread_lazy_restore_ns_vfp(void) 134 { 135 #ifdef CFG_WITH_VFP 136 struct thread_ctx *thr = threads + thread_get_id(); 137 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 138 139 assert(!thr->vfp_state.sec_lazy_saved && !thr->vfp_state.sec_saved); 140 141 if (tuv && tuv->lazy_saved && !tuv->saved) { 142 vfp_lazy_save_state_final(&tuv->vfp, false /*!force_save*/); 143 tuv->saved = true; 144 } 145 146 vfp_lazy_restore_state(&thr->vfp_state.ns, thr->vfp_state.ns_saved); 147 thr->vfp_state.ns_saved = false; 148 #endif /*CFG_WITH_VFP*/ 149 } 150 151 #ifdef ARM32 152 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, 153 uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, 154 uint32_t a6, uint32_t a7, void *pc) 155 { 156 thread->regs.pc = (uint32_t)pc; 157 158 /* 159 * Stdcalls starts in SVC mode with masked foreign interrupts, masked 160 * Asynchronous abort and unmasked native interrupts. 161 */ 162 thread->regs.cpsr = read_cpsr() & ARM32_CPSR_E; 163 thread->regs.cpsr |= CPSR_MODE_SVC | CPSR_A | 164 (THREAD_EXCP_FOREIGN_INTR << ARM32_CPSR_F_SHIFT); 165 /* Enable thumb mode if it's a thumb instruction */ 166 if (thread->regs.pc & 1) 167 thread->regs.cpsr |= CPSR_T; 168 /* Reinitialize stack pointer */ 169 thread->regs.svc_sp = thread->stack_va_end; 170 171 /* 172 * Copy arguments into context. This will make the 173 * arguments appear in r0-r7 when thread is started. 174 */ 175 thread->regs.r0 = a0; 176 thread->regs.r1 = a1; 177 thread->regs.r2 = a2; 178 thread->regs.r3 = a3; 179 thread->regs.r4 = a4; 180 thread->regs.r5 = a5; 181 thread->regs.r6 = a6; 182 thread->regs.r7 = a7; 183 } 184 #endif /*ARM32*/ 185 186 #ifdef ARM64 187 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, 188 uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, 189 uint32_t a6, uint32_t a7, void *pc) 190 { 191 thread->regs.pc = (uint64_t)pc; 192 193 /* 194 * Stdcalls starts in SVC mode with masked foreign interrupts, masked 195 * Asynchronous abort and unmasked native interrupts. 196 */ 197 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 198 THREAD_EXCP_FOREIGN_INTR | DAIFBIT_ABT); 199 /* Reinitialize stack pointer */ 200 thread->regs.sp = thread->stack_va_end; 201 202 /* 203 * Copy arguments into context. This will make the 204 * arguments appear in x0-x7 when thread is started. 205 */ 206 thread->regs.x[0] = a0; 207 thread->regs.x[1] = a1; 208 thread->regs.x[2] = a2; 209 thread->regs.x[3] = a3; 210 thread->regs.x[4] = a4; 211 thread->regs.x[5] = a5; 212 thread->regs.x[6] = a6; 213 thread->regs.x[7] = a7; 214 215 /* Set up frame pointer as per the Aarch64 AAPCS */ 216 thread->regs.x[29] = 0; 217 } 218 #endif /*ARM64*/ 219 220 static void __thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, 221 uint32_t a3, uint32_t a4, uint32_t a5, 222 uint32_t a6, uint32_t a7, 223 void *pc, uint32_t flags) 224 { 225 struct thread_core_local *l = thread_get_core_local(); 226 bool found_thread = false; 227 size_t n = 0; 228 229 assert(l->curr_thread == THREAD_ID_INVALID); 230 231 thread_lock_global(); 232 233 for (n = 0; n < CFG_NUM_THREADS; n++) { 234 if (threads[n].state == THREAD_STATE_FREE) { 235 threads[n].state = THREAD_STATE_ACTIVE; 236 found_thread = true; 237 break; 238 } 239 } 240 241 thread_unlock_global(); 242 243 if (!found_thread) 244 return; 245 246 l->curr_thread = n; 247 248 threads[n].flags = flags; 249 init_regs(threads + n, a0, a1, a2, a3, a4, a5, a6, a7, pc); 250 #ifdef CFG_CORE_PAUTH 251 /* 252 * Copy the APIA key into the registers to be restored with 253 * thread_resume(). 254 */ 255 threads[n].regs.apiakey_hi = threads[n].keys.apia_hi; 256 threads[n].regs.apiakey_lo = threads[n].keys.apia_lo; 257 #endif 258 259 thread_lazy_save_ns_vfp(); 260 261 l->flags &= ~THREAD_CLF_TMP; 262 thread_resume(&threads[n].regs); 263 /*NOTREACHED*/ 264 panic(); 265 } 266 267 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, 268 uint32_t a4, uint32_t a5) 269 { 270 __thread_alloc_and_run(a0, a1, a2, a3, a4, a5, 0, 0, 271 thread_std_smc_entry, 0); 272 } 273 274 #ifdef CFG_SECURE_PARTITION 275 void thread_sp_alloc_and_run(struct thread_smc_args *args __maybe_unused) 276 { 277 __thread_alloc_and_run(args->a0, args->a1, args->a2, args->a3, args->a4, 278 args->a5, args->a6, args->a7, 279 spmc_sp_thread_entry, THREAD_FLAGS_FFA_ONLY); 280 } 281 #endif 282 283 #ifdef ARM32 284 static void copy_a0_to_a3(struct thread_ctx_regs *regs, uint32_t a0, 285 uint32_t a1, uint32_t a2, uint32_t a3) 286 { 287 /* 288 * Update returned values from RPC, values will appear in 289 * r0-r3 when thread is resumed. 290 */ 291 regs->r0 = a0; 292 regs->r1 = a1; 293 regs->r2 = a2; 294 regs->r3 = a3; 295 } 296 #endif /*ARM32*/ 297 298 #ifdef ARM64 299 static void copy_a0_to_a3(struct thread_ctx_regs *regs, uint32_t a0, 300 uint32_t a1, uint32_t a2, uint32_t a3) 301 { 302 /* 303 * Update returned values from RPC, values will appear in 304 * x0-x3 when thread is resumed. 305 */ 306 regs->x[0] = a0; 307 regs->x[1] = a1; 308 regs->x[2] = a2; 309 regs->x[3] = a3; 310 } 311 #endif /*ARM64*/ 312 313 #ifdef ARM32 314 static bool is_from_user(uint32_t cpsr) 315 { 316 return (cpsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 317 } 318 #endif 319 320 #ifdef ARM64 321 static bool is_from_user(uint32_t cpsr) 322 { 323 if (cpsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 324 return true; 325 if (((cpsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 326 SPSR_64_MODE_EL0) 327 return true; 328 return false; 329 } 330 #endif 331 332 #ifdef CFG_SYSCALL_FTRACE 333 static void __noprof ftrace_suspend(void) 334 { 335 struct ts_session *s = TAILQ_FIRST(&thread_get_tsd()->sess_stack); 336 TEE_Result res = TEE_SUCCESS; 337 338 if (s && s->fbuf) { 339 res = vm_check_access_rights(to_user_mode_ctx(s->ctx), 340 TEE_MEMORY_ACCESS_WRITE | 341 TEE_MEMORY_ACCESS_ANY_OWNER, 342 (uaddr_t)s->fbuf, 343 sizeof(*s->fbuf)); 344 if (!res) 345 s->fbuf->syscall_trace_suspended = true; 346 } 347 } 348 349 static void __noprof ftrace_resume(void) 350 { 351 struct ts_session *s = TAILQ_FIRST(&thread_get_tsd()->sess_stack); 352 TEE_Result res = TEE_SUCCESS; 353 354 if (s && s->fbuf) { 355 res = vm_check_access_rights(to_user_mode_ctx(s->ctx), 356 TEE_MEMORY_ACCESS_WRITE | 357 TEE_MEMORY_ACCESS_ANY_OWNER, 358 (uaddr_t)s->fbuf, 359 sizeof(*s->fbuf)); 360 if (!res) 361 s->fbuf->syscall_trace_suspended = false; 362 } 363 } 364 #else 365 static void __noprof ftrace_suspend(void) 366 { 367 } 368 369 static void __noprof ftrace_resume(void) 370 { 371 } 372 #endif 373 374 static bool is_user_mode(struct thread_ctx_regs *regs) 375 { 376 return is_from_user((uint32_t)regs->cpsr); 377 } 378 379 void thread_resume_from_rpc(uint32_t thread_id, uint32_t a0, uint32_t a1, 380 uint32_t a2, uint32_t a3) 381 { 382 size_t n = thread_id; 383 struct thread_core_local *l = thread_get_core_local(); 384 bool found_thread = false; 385 386 assert(l->curr_thread == THREAD_ID_INVALID); 387 388 thread_lock_global(); 389 390 if (n < CFG_NUM_THREADS && threads[n].state == THREAD_STATE_SUSPENDED) { 391 threads[n].state = THREAD_STATE_ACTIVE; 392 found_thread = true; 393 } 394 395 thread_unlock_global(); 396 397 if (!found_thread) 398 return; 399 400 l->curr_thread = n; 401 402 if (threads[n].have_user_map) { 403 core_mmu_set_user_map(&threads[n].user_map); 404 if (threads[n].flags & THREAD_FLAGS_EXIT_ON_FOREIGN_INTR) 405 tee_ta_ftrace_update_times_resume(); 406 } 407 408 if (is_user_mode(&threads[n].regs)) 409 tee_ta_update_session_utime_resume(); 410 411 /* 412 * Return from RPC to request service of a foreign interrupt must not 413 * get parameters from non-secure world. 414 */ 415 if (threads[n].flags & THREAD_FLAGS_COPY_ARGS_ON_RETURN) { 416 copy_a0_to_a3(&threads[n].regs, a0, a1, a2, a3); 417 threads[n].flags &= ~THREAD_FLAGS_COPY_ARGS_ON_RETURN; 418 } 419 420 thread_lazy_save_ns_vfp(); 421 422 if (threads[n].have_user_map) 423 ftrace_resume(); 424 425 l->flags &= ~THREAD_CLF_TMP; 426 thread_resume(&threads[n].regs); 427 /*NOTREACHED*/ 428 panic(); 429 } 430 431 #ifdef ARM64 432 static uint64_t spsr_from_pstate(void) 433 { 434 uint64_t spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, 0); 435 436 spsr |= read_daif(); 437 if (IS_ENABLED(CFG_PAN) && feat_pan_implemented() && read_pan()) 438 spsr |= SPSR_64_PAN; 439 440 return spsr; 441 } 442 443 void __thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) 444 { 445 thread_rpc_spsr(rv, spsr_from_pstate()); 446 } 447 448 vaddr_t thread_get_saved_thread_sp(void) 449 { 450 struct thread_core_local *l = thread_get_core_local(); 451 int ct = l->curr_thread; 452 453 assert(ct != THREAD_ID_INVALID); 454 return threads[ct].kern_sp; 455 } 456 #endif /*ARM64*/ 457 458 #ifdef ARM32 459 bool __noprof thread_is_in_normal_mode(void) 460 { 461 return (read_cpsr() & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_SVC; 462 } 463 #endif 464 465 void thread_state_free(void) 466 { 467 struct thread_core_local *l = thread_get_core_local(); 468 int ct = l->curr_thread; 469 470 assert(ct != THREAD_ID_INVALID); 471 472 thread_lazy_restore_ns_vfp(); 473 tee_pager_release_phys( 474 (void *)(threads[ct].stack_va_end - STACK_THREAD_SIZE), 475 STACK_THREAD_SIZE); 476 477 thread_lock_global(); 478 479 assert(threads[ct].state == THREAD_STATE_ACTIVE); 480 threads[ct].state = THREAD_STATE_FREE; 481 threads[ct].flags = 0; 482 l->curr_thread = THREAD_ID_INVALID; 483 484 if (IS_ENABLED(CFG_NS_VIRTUALIZATION)) 485 virt_unset_guest(); 486 thread_unlock_global(); 487 } 488 489 #ifdef CFG_WITH_PAGER 490 static void release_unused_kernel_stack(struct thread_ctx *thr, 491 uint32_t cpsr __maybe_unused) 492 { 493 #ifdef ARM64 494 /* 495 * If we're from user mode then thr->regs.sp is the saved user 496 * stack pointer and thr->kern_sp holds the last kernel stack 497 * pointer. But if we're from kernel mode then thr->kern_sp isn't 498 * up to date so we need to read from thr->regs.sp instead. 499 */ 500 vaddr_t sp = is_from_user(cpsr) ? thr->kern_sp : thr->regs.sp; 501 #else 502 vaddr_t sp = thr->regs.svc_sp; 503 #endif 504 vaddr_t base = thr->stack_va_end - STACK_THREAD_SIZE; 505 size_t len = sp - base; 506 507 tee_pager_release_phys((void *)base, len); 508 } 509 #else 510 static void release_unused_kernel_stack(struct thread_ctx *thr __unused, 511 uint32_t cpsr __unused) 512 { 513 } 514 #endif 515 516 int thread_state_suspend(uint32_t flags, uint32_t cpsr, vaddr_t pc) 517 { 518 struct thread_core_local *l = thread_get_core_local(); 519 int ct = l->curr_thread; 520 521 assert(ct != THREAD_ID_INVALID); 522 523 if (core_mmu_user_mapping_is_active()) 524 ftrace_suspend(); 525 526 thread_check_canaries(); 527 528 release_unused_kernel_stack(threads + ct, cpsr); 529 530 if (is_from_user(cpsr)) { 531 thread_user_save_vfp(); 532 tee_ta_update_session_utime_suspend(); 533 tee_ta_gprof_sample_pc(pc); 534 } 535 thread_lazy_restore_ns_vfp(); 536 537 thread_lock_global(); 538 539 assert(threads[ct].state == THREAD_STATE_ACTIVE); 540 threads[ct].flags |= flags; 541 threads[ct].regs.cpsr = cpsr; 542 threads[ct].regs.pc = pc; 543 threads[ct].state = THREAD_STATE_SUSPENDED; 544 545 threads[ct].have_user_map = core_mmu_user_mapping_is_active(); 546 if (threads[ct].have_user_map) { 547 if (threads[ct].flags & THREAD_FLAGS_EXIT_ON_FOREIGN_INTR) 548 tee_ta_ftrace_update_times_suspend(); 549 core_mmu_get_user_map(&threads[ct].user_map); 550 core_mmu_set_user_map(NULL); 551 } 552 553 if (IS_ENABLED(CFG_SECURE_PARTITION)) { 554 struct ts_session *ts_sess = 555 TAILQ_FIRST(&threads[ct].tsd.sess_stack); 556 557 spmc_sp_set_to_preempted(ts_sess); 558 } 559 560 l->curr_thread = THREAD_ID_INVALID; 561 562 if (IS_ENABLED(CFG_NS_VIRTUALIZATION)) 563 virt_unset_guest(); 564 565 thread_unlock_global(); 566 567 return ct; 568 } 569 570 static void __maybe_unused 571 set_core_local_kcode_offset(struct thread_core_local *cls, long offset) 572 { 573 size_t n = 0; 574 575 for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) 576 cls[n].kcode_offset = offset; 577 } 578 579 static void init_user_kcode(void) 580 { 581 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 582 vaddr_t v = (vaddr_t)thread_excp_vect; 583 vaddr_t ve = (vaddr_t)thread_excp_vect_end; 584 585 thread_user_kcode_va = ROUNDDOWN(v, CORE_MMU_USER_CODE_SIZE); 586 ve = ROUNDUP(ve, CORE_MMU_USER_CODE_SIZE); 587 thread_user_kcode_size = ve - thread_user_kcode_va; 588 589 core_mmu_get_user_va_range(&v, NULL); 590 thread_user_kcode_offset = thread_user_kcode_va - v; 591 592 set_core_local_kcode_offset(thread_core_local, 593 thread_user_kcode_offset); 594 #if defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 595 set_core_local_kcode_offset((void *)thread_user_kdata_page, 596 thread_user_kcode_offset); 597 /* 598 * When transitioning to EL0 subtract SP with this much to point to 599 * this special kdata page instead. SP is restored by add this much 600 * while transitioning back to EL1. 601 */ 602 v += thread_user_kcode_size; 603 thread_user_kdata_sp_offset = (vaddr_t)thread_core_local - v; 604 #endif 605 #endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 606 } 607 608 void thread_init_primary(void) 609 { 610 init_user_kcode(); 611 } 612 613 static uint32_t __maybe_unused get_midr_implementer(uint32_t midr) 614 { 615 return (midr >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK; 616 } 617 618 static uint32_t __maybe_unused get_midr_primary_part(uint32_t midr) 619 { 620 return (midr >> MIDR_PRIMARY_PART_NUM_SHIFT) & 621 MIDR_PRIMARY_PART_NUM_MASK; 622 } 623 624 static uint32_t __maybe_unused get_midr_variant(uint32_t midr) 625 { 626 return (midr >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK; 627 } 628 629 static uint32_t __maybe_unused get_midr_revision(uint32_t midr) 630 { 631 return (midr >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK; 632 } 633 634 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 635 #ifdef ARM64 636 static bool probe_workaround_available(uint32_t wa_id) 637 { 638 int32_t r; 639 640 r = thread_smc(SMCCC_VERSION, 0, 0, 0); 641 if (r < 0) 642 return false; 643 if (r < 0x10001) /* compare with version 1.1 */ 644 return false; 645 646 /* Version >= 1.1, so SMCCC_ARCH_FEATURES is available */ 647 r = thread_smc(SMCCC_ARCH_FEATURES, wa_id, 0, 0); 648 return r >= 0; 649 } 650 651 static vaddr_t __maybe_unused select_vector_wa_spectre_v2(void) 652 { 653 if (probe_workaround_available(SMCCC_ARCH_WORKAROUND_1)) { 654 DMSG("SMCCC_ARCH_WORKAROUND_1 (%#08" PRIx32 ") available", 655 SMCCC_ARCH_WORKAROUND_1); 656 DMSG("SMC Workaround for CVE-2017-5715 used"); 657 return (vaddr_t)thread_excp_vect_wa_spectre_v2; 658 } 659 660 DMSG("SMCCC_ARCH_WORKAROUND_1 (%#08" PRIx32 ") unavailable", 661 SMCCC_ARCH_WORKAROUND_1); 662 DMSG("SMC Workaround for CVE-2017-5715 not needed (if ARM-TF is up to date)"); 663 return (vaddr_t)thread_excp_vect; 664 } 665 #else 666 static vaddr_t __maybe_unused select_vector_wa_spectre_v2(void) 667 { 668 return (vaddr_t)thread_excp_vect_wa_spectre_v2; 669 } 670 #endif 671 #endif 672 673 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 674 static vaddr_t select_vector_wa_spectre_bhb(uint8_t loop_count __maybe_unused) 675 { 676 /* 677 * Spectre-BHB has only been analyzed for AArch64 so far. For 678 * AArch32 fall back to the Spectre-V2 workaround which is likely 679 * to work even if perhaps a bit more expensive than a more 680 * optimized workaround. 681 */ 682 #ifdef ARM64 683 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 684 struct thread_core_local *cl = (void *)thread_user_kdata_page; 685 686 cl[get_core_pos()].bhb_loop_count = loop_count; 687 #endif 688 thread_get_core_local()->bhb_loop_count = loop_count; 689 690 DMSG("Spectre-BHB CVE-2022-23960 workaround enabled with \"K\" = %u", 691 loop_count); 692 693 return (vaddr_t)thread_excp_vect_wa_spectre_bhb; 694 #else 695 return select_vector_wa_spectre_v2(); 696 #endif 697 } 698 #endif 699 700 static vaddr_t get_excp_vect(void) 701 { 702 #ifdef CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 703 uint32_t midr = read_midr(); 704 uint8_t vers = 0; 705 706 if (get_midr_implementer(midr) != MIDR_IMPLEMENTER_ARM) 707 return (vaddr_t)thread_excp_vect; 708 /* 709 * Variant rx, Revision py, for instance 710 * Variant 2 Revision 0 = r2p0 = 0x20 711 */ 712 vers = (get_midr_variant(midr) << 4) | get_midr_revision(midr); 713 714 /* 715 * Spectre-V2 (CVE-2017-5715) software workarounds covers what's 716 * needed for Spectre-BHB (CVE-2022-23960) too. The workaround for 717 * Spectre-V2 is more expensive than the one for Spectre-BHB so if 718 * possible select the workaround for Spectre-BHB. 719 */ 720 switch (get_midr_primary_part(midr)) { 721 #ifdef ARM32 722 /* Spectre-V2 */ 723 case CORTEX_A8_PART_NUM: 724 case CORTEX_A9_PART_NUM: 725 case CORTEX_A17_PART_NUM: 726 #endif 727 /* Spectre-V2 */ 728 case CORTEX_A57_PART_NUM: 729 case CORTEX_A73_PART_NUM: 730 case CORTEX_A75_PART_NUM: 731 return select_vector_wa_spectre_v2(); 732 #ifdef ARM32 733 /* Spectre-V2 */ 734 case CORTEX_A15_PART_NUM: 735 return (vaddr_t)thread_excp_vect_wa_a15_spectre_v2; 736 #endif 737 /* 738 * Spectre-V2 for vers < r1p0 739 * Spectre-BHB for vers >= r1p0 740 */ 741 case CORTEX_A72_PART_NUM: 742 if (vers < 0x10) 743 return select_vector_wa_spectre_v2(); 744 return select_vector_wa_spectre_bhb(8); 745 746 /* 747 * Doing the more safe but expensive Spectre-V2 workaround for CPUs 748 * still being researched on the best mitigation sequence. 749 */ 750 case CORTEX_A65_PART_NUM: 751 case CORTEX_A65AE_PART_NUM: 752 case NEOVERSE_E1_PART_NUM: 753 return select_vector_wa_spectre_v2(); 754 755 /* Spectre-BHB */ 756 case CORTEX_A76_PART_NUM: 757 case CORTEX_A76AE_PART_NUM: 758 case CORTEX_A77_PART_NUM: 759 return select_vector_wa_spectre_bhb(24); 760 case CORTEX_A78_PART_NUM: 761 case CORTEX_A78AE_PART_NUM: 762 case CORTEX_A78C_PART_NUM: 763 case CORTEX_A710_PART_NUM: 764 case CORTEX_X1_PART_NUM: 765 case CORTEX_X2_PART_NUM: 766 return select_vector_wa_spectre_bhb(32); 767 case NEOVERSE_N1_PART_NUM: 768 return select_vector_wa_spectre_bhb(24); 769 case NEOVERSE_N2_PART_NUM: 770 case NEOVERSE_V1_PART_NUM: 771 return select_vector_wa_spectre_bhb(32); 772 773 default: 774 return (vaddr_t)thread_excp_vect; 775 } 776 #endif /*CFG_CORE_WORKAROUND_SPECTRE_BP_SEC*/ 777 778 return (vaddr_t)thread_excp_vect; 779 } 780 781 void thread_init_per_cpu(void) 782 { 783 thread_init_vbar(get_excp_vect()); 784 785 #ifdef CFG_FTRACE_SUPPORT 786 /* 787 * Enable accesses to frequency register and physical counter 788 * register in EL0/PL0 required for timestamping during 789 * function tracing. 790 */ 791 write_cntkctl(read_cntkctl() | CNTKCTL_PL0PCTEN); 792 #endif 793 } 794 795 #ifdef CFG_WITH_VFP 796 uint32_t thread_kernel_enable_vfp(void) 797 { 798 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_FOREIGN_INTR); 799 struct thread_ctx *thr = threads + thread_get_id(); 800 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 801 802 assert(!vfp_is_enabled()); 803 804 if (!thr->vfp_state.ns_saved) { 805 vfp_lazy_save_state_final(&thr->vfp_state.ns, 806 true /*force_save*/); 807 thr->vfp_state.ns_saved = true; 808 } else if (thr->vfp_state.sec_lazy_saved && 809 !thr->vfp_state.sec_saved) { 810 /* 811 * This happens when we're handling an abort while the 812 * thread was using the VFP state. 813 */ 814 vfp_lazy_save_state_final(&thr->vfp_state.sec, 815 false /*!force_save*/); 816 thr->vfp_state.sec_saved = true; 817 } else if (tuv && tuv->lazy_saved && !tuv->saved) { 818 /* 819 * This can happen either during syscall or abort 820 * processing (while processing a syscall). 821 */ 822 vfp_lazy_save_state_final(&tuv->vfp, false /*!force_save*/); 823 tuv->saved = true; 824 } 825 826 vfp_enable(); 827 return exceptions; 828 } 829 830 void thread_kernel_disable_vfp(uint32_t state) 831 { 832 uint32_t exceptions; 833 834 assert(vfp_is_enabled()); 835 836 vfp_disable(); 837 exceptions = thread_get_exceptions(); 838 assert(exceptions & THREAD_EXCP_FOREIGN_INTR); 839 exceptions &= ~THREAD_EXCP_FOREIGN_INTR; 840 exceptions |= state & THREAD_EXCP_FOREIGN_INTR; 841 thread_set_exceptions(exceptions); 842 } 843 844 void thread_kernel_save_vfp(void) 845 { 846 struct thread_ctx *thr = threads + thread_get_id(); 847 848 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 849 if (vfp_is_enabled()) { 850 vfp_lazy_save_state_init(&thr->vfp_state.sec); 851 thr->vfp_state.sec_lazy_saved = true; 852 } 853 } 854 855 void thread_kernel_restore_vfp(void) 856 { 857 struct thread_ctx *thr = threads + thread_get_id(); 858 859 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 860 assert(!vfp_is_enabled()); 861 if (thr->vfp_state.sec_lazy_saved) { 862 vfp_lazy_restore_state(&thr->vfp_state.sec, 863 thr->vfp_state.sec_saved); 864 thr->vfp_state.sec_saved = false; 865 thr->vfp_state.sec_lazy_saved = false; 866 } 867 } 868 869 void thread_user_enable_vfp(struct thread_user_vfp_state *uvfp) 870 { 871 struct thread_ctx *thr = threads + thread_get_id(); 872 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 873 874 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 875 assert(!vfp_is_enabled()); 876 877 if (!thr->vfp_state.ns_saved) { 878 vfp_lazy_save_state_final(&thr->vfp_state.ns, 879 true /*force_save*/); 880 thr->vfp_state.ns_saved = true; 881 } else if (tuv && uvfp != tuv) { 882 if (tuv->lazy_saved && !tuv->saved) { 883 vfp_lazy_save_state_final(&tuv->vfp, 884 false /*!force_save*/); 885 tuv->saved = true; 886 } 887 } 888 889 if (uvfp->lazy_saved) 890 vfp_lazy_restore_state(&uvfp->vfp, uvfp->saved); 891 uvfp->lazy_saved = false; 892 uvfp->saved = false; 893 894 thr->vfp_state.uvfp = uvfp; 895 vfp_enable(); 896 } 897 898 void thread_user_save_vfp(void) 899 { 900 struct thread_ctx *thr = threads + thread_get_id(); 901 struct thread_user_vfp_state *tuv = thr->vfp_state.uvfp; 902 903 assert(thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR); 904 if (!vfp_is_enabled()) 905 return; 906 907 assert(tuv && !tuv->lazy_saved && !tuv->saved); 908 vfp_lazy_save_state_init(&tuv->vfp); 909 tuv->lazy_saved = true; 910 } 911 912 void thread_user_clear_vfp(struct user_mode_ctx *uctx) 913 { 914 struct thread_user_vfp_state *uvfp = &uctx->vfp; 915 struct thread_ctx *thr = threads + thread_get_id(); 916 917 if (uvfp == thr->vfp_state.uvfp) 918 thr->vfp_state.uvfp = NULL; 919 uvfp->lazy_saved = false; 920 uvfp->saved = false; 921 } 922 #endif /*CFG_WITH_VFP*/ 923 924 #ifdef ARM32 925 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 926 { 927 uint32_t s; 928 929 if (!is_32bit) 930 return false; 931 932 s = read_cpsr(); 933 s &= ~(CPSR_MODE_MASK | CPSR_T | CPSR_IT_MASK1 | CPSR_IT_MASK2); 934 s |= CPSR_MODE_USR; 935 if (entry_func & 1) 936 s |= CPSR_T; 937 *spsr = s; 938 return true; 939 } 940 #endif 941 942 #ifdef ARM64 943 static bool get_spsr(bool is_32bit, unsigned long entry_func, uint32_t *spsr) 944 { 945 uint32_t s; 946 947 if (is_32bit) { 948 s = read_daif() & (SPSR_32_AIF_MASK << SPSR_32_AIF_SHIFT); 949 s |= SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT; 950 s |= (entry_func & SPSR_32_T_MASK) << SPSR_32_T_SHIFT; 951 } else { 952 s = read_daif() & (SPSR_64_DAIF_MASK << SPSR_64_DAIF_SHIFT); 953 } 954 955 *spsr = s; 956 return true; 957 } 958 #endif 959 960 static void set_ctx_regs(struct thread_ctx_regs *regs, unsigned long a0, 961 unsigned long a1, unsigned long a2, unsigned long a3, 962 unsigned long user_sp, unsigned long entry_func, 963 uint32_t spsr, 964 struct thread_pauth_keys *keys __maybe_unused) 965 { 966 /* 967 * First clear all registers to avoid leaking information from 968 * other TAs or even the Core itself. 969 */ 970 *regs = (struct thread_ctx_regs){ }; 971 #ifdef ARM32 972 regs->r0 = a0; 973 regs->r1 = a1; 974 regs->r2 = a2; 975 regs->r3 = a3; 976 regs->usr_sp = user_sp; 977 regs->pc = entry_func; 978 regs->cpsr = spsr; 979 #endif 980 #ifdef ARM64 981 regs->x[0] = a0; 982 regs->x[1] = a1; 983 regs->x[2] = a2; 984 regs->x[3] = a3; 985 regs->pc = entry_func; 986 regs->cpsr = spsr; 987 regs->x[13] = user_sp; /* Used when running TA in Aarch32 */ 988 regs->sp = user_sp; /* Used when running TA in Aarch64 */ 989 #ifdef CFG_TA_PAUTH 990 assert(keys); 991 regs->apiakey_hi = keys->apia_hi; 992 regs->apiakey_lo = keys->apia_lo; 993 #endif 994 /* Set frame pointer (user stack can't be unwound past this point) */ 995 regs->x[29] = 0; 996 #endif 997 } 998 999 static struct thread_pauth_keys *thread_get_pauth_keys(void) 1000 { 1001 #if defined(CFG_TA_PAUTH) 1002 struct ts_session *s = ts_get_current_session(); 1003 1004 if (is_user_ta_ctx(s->ctx)) { 1005 struct user_ta_ctx *utc = to_user_ta_ctx(s->ctx); 1006 1007 return &utc->uctx.keys; 1008 } else if (is_sp_ctx(s->ctx)) { 1009 struct sp_ctx *spc = to_sp_ctx(s->ctx); 1010 1011 return &spc->uctx.keys; 1012 } 1013 1014 panic("[abort] Only user TAs and SPs support PAUTH keys"); 1015 #else 1016 return NULL; 1017 #endif 1018 } 1019 1020 uint32_t thread_enter_user_mode(unsigned long a0, unsigned long a1, 1021 unsigned long a2, unsigned long a3, unsigned long user_sp, 1022 unsigned long entry_func, bool is_32bit, 1023 uint32_t *exit_status0, uint32_t *exit_status1) 1024 { 1025 uint32_t spsr = 0; 1026 uint32_t exceptions = 0; 1027 uint32_t rc = 0; 1028 struct thread_ctx_regs *regs = NULL; 1029 struct thread_pauth_keys *keys = NULL; 1030 1031 tee_ta_update_session_utime_resume(); 1032 1033 keys = thread_get_pauth_keys(); 1034 1035 /* Derive SPSR from current CPSR/PSTATE readout. */ 1036 if (!get_spsr(is_32bit, entry_func, &spsr)) { 1037 *exit_status0 = 1; /* panic */ 1038 *exit_status1 = 0xbadbadba; 1039 return 0; 1040 } 1041 1042 exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); 1043 /* 1044 * We're using the per thread location of saved context registers 1045 * for temporary storage. Now that exceptions are masked they will 1046 * not be used for any thing else until they are eventually 1047 * unmasked when user mode has been entered. 1048 */ 1049 regs = thread_get_ctx_regs(); 1050 set_ctx_regs(regs, a0, a1, a2, a3, user_sp, entry_func, spsr, keys); 1051 rc = __thread_enter_user_mode(regs, exit_status0, exit_status1); 1052 thread_unmask_exceptions(exceptions); 1053 return rc; 1054 } 1055 1056 #ifdef CFG_CORE_UNMAP_CORE_AT_EL0 1057 void thread_get_user_kcode(struct mobj **mobj, size_t *offset, 1058 vaddr_t *va, size_t *sz) 1059 { 1060 core_mmu_get_user_va_range(va, NULL); 1061 *mobj = mobj_tee_ram_rx; 1062 *sz = thread_user_kcode_size; 1063 *offset = thread_user_kcode_va - (vaddr_t)mobj_get_va(*mobj, 0, *sz); 1064 } 1065 #endif 1066 1067 #if defined(CFG_CORE_UNMAP_CORE_AT_EL0) && \ 1068 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64) 1069 void thread_get_user_kdata(struct mobj **mobj, size_t *offset, 1070 vaddr_t *va, size_t *sz) 1071 { 1072 vaddr_t v; 1073 1074 core_mmu_get_user_va_range(&v, NULL); 1075 *va = v + thread_user_kcode_size; 1076 *mobj = mobj_tee_ram_rw; 1077 *sz = sizeof(thread_user_kdata_page); 1078 *offset = (vaddr_t)thread_user_kdata_page - 1079 (vaddr_t)mobj_get_va(*mobj, 0, *sz); 1080 } 1081 #endif 1082 1083 static void setup_unwind_user_mode(struct thread_scall_regs *regs) 1084 { 1085 #ifdef ARM32 1086 regs->lr = (uintptr_t)thread_unwind_user_mode; 1087 regs->spsr = read_cpsr(); 1088 #endif 1089 #ifdef ARM64 1090 regs->elr = (uintptr_t)thread_unwind_user_mode; 1091 regs->spsr = spsr_from_pstate(); 1092 /* 1093 * Regs is the value of stack pointer before calling the SVC 1094 * handler. By the addition matches for the reserved space at the 1095 * beginning of el0_sync_svc(). This prepares the stack when 1096 * returning to thread_unwind_user_mode instead of a normal 1097 * exception return. 1098 */ 1099 regs->sp_el0 = (uint64_t)(regs + 1); 1100 #endif 1101 } 1102 1103 static void gprof_set_status(struct ts_session *s __maybe_unused, 1104 enum ts_gprof_status status __maybe_unused) 1105 { 1106 #ifdef CFG_TA_GPROF_SUPPORT 1107 if (s->ctx->ops->gprof_set_status) 1108 s->ctx->ops->gprof_set_status(status); 1109 #endif 1110 } 1111 1112 /* 1113 * Note: this function is weak just to make it possible to exclude it from 1114 * the unpaged area. 1115 */ 1116 void __weak thread_scall_handler(struct thread_scall_regs *regs) 1117 { 1118 struct ts_session *sess = NULL; 1119 uint32_t state = 0; 1120 1121 /* Enable native interrupts */ 1122 state = thread_get_exceptions(); 1123 thread_unmask_exceptions(state & ~THREAD_EXCP_NATIVE_INTR); 1124 1125 thread_user_save_vfp(); 1126 1127 sess = ts_get_current_session(); 1128 /* 1129 * User mode service has just entered kernel mode, suspend gprof 1130 * collection until we're about to switch back again. 1131 */ 1132 gprof_set_status(sess, TS_GPROF_SUSPEND); 1133 1134 /* Restore foreign interrupts which are disabled on exception entry */ 1135 thread_restore_foreign_intr(); 1136 1137 assert(sess && sess->handle_scall); 1138 if (sess->handle_scall(regs)) { 1139 /* We're about to switch back to user mode */ 1140 gprof_set_status(sess, TS_GPROF_RESUME); 1141 } else { 1142 /* We're returning from __thread_enter_user_mode() */ 1143 setup_unwind_user_mode(regs); 1144 } 1145 } 1146 1147 #ifdef CFG_WITH_ARM_TRUSTED_FW 1148 /* 1149 * These five functions are __weak to allow platforms to override them if 1150 * needed. 1151 */ 1152 unsigned long __weak thread_cpu_off_handler(unsigned long a0 __unused, 1153 unsigned long a1 __unused) 1154 { 1155 return 0; 1156 } 1157 DECLARE_KEEP_PAGER(thread_cpu_off_handler); 1158 1159 unsigned long __weak thread_cpu_suspend_handler(unsigned long a0 __unused, 1160 unsigned long a1 __unused) 1161 { 1162 return 0; 1163 } 1164 DECLARE_KEEP_PAGER(thread_cpu_suspend_handler); 1165 1166 unsigned long __weak thread_cpu_resume_handler(unsigned long a0 __unused, 1167 unsigned long a1 __unused) 1168 { 1169 return 0; 1170 } 1171 DECLARE_KEEP_PAGER(thread_cpu_resume_handler); 1172 1173 unsigned long __weak thread_system_off_handler(unsigned long a0 __unused, 1174 unsigned long a1 __unused) 1175 { 1176 return 0; 1177 } 1178 DECLARE_KEEP_PAGER(thread_system_off_handler); 1179 1180 unsigned long __weak thread_system_reset_handler(unsigned long a0 __unused, 1181 unsigned long a1 __unused) 1182 { 1183 return 0; 1184 } 1185 DECLARE_KEEP_PAGER(thread_system_reset_handler); 1186 #endif /*CFG_WITH_ARM_TRUSTED_FW*/ 1187 1188 #ifdef CFG_CORE_WORKAROUND_ARM_NMFI 1189 void __noreturn interrupt_main_handler(void) 1190 { 1191 /* 1192 * Note: overrides the default implementation of this function so that 1193 * if there would be another handler defined there would be duplicate 1194 * symbol error during linking. 1195 */ 1196 panic("Secure interrupt received but it is not supported"); 1197 } 1198 #endif 1199