1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <asm.S> 29#include <arm.h> 30#include <arm32_macros.S> 31 32/* Let platforms override this if needed */ 33.weak get_core_pos 34 35FUNC get_core_pos , : 36 read_mpidr r0 37 /* Calculate CorePos = (ClusterId * 4) + CoreId */ 38 and r1, r0, #MPIDR_CPU_MASK 39 and r0, r0, #MPIDR_CLUSTER_MASK 40 add r0, r1, r0, LSR #6 41 bx lr 42END_FUNC get_core_pos 43 44/* 45 * uint32_t temp_set_mode(int cpu_mode) 46 * returns cpsr to be set 47 */ 48LOCAL_FUNC temp_set_mode , : 49 mov r1, r0 50 cmp r1, #CPSR_MODE_USR /* update mode: usr -> sys */ 51 moveq r1, #CPSR_MODE_SYS 52 cpsid aif /* disable interrupts */ 53 mrs r0, cpsr /* get cpsr with disabled its*/ 54 bic r0, #CPSR_MODE_MASK /* clear mode */ 55 orr r0, r1 /* set expected mode */ 56 bx lr 57END_FUNC temp_set_mode 58 59/* uint32_t read_mode_sp(int cpu_mode) */ 60FUNC read_mode_sp , : 61 push {r4, lr} 62 mrs r4, cpsr /* save cpsr */ 63 bl temp_set_mode 64 msr cpsr, r0 /* set the new mode */ 65 mov r0, sp /* get the function result */ 66 msr cpsr, r4 /* back to the old mode */ 67 pop {r4, pc} 68END_FUNC read_mode_sp 69 70/* uint32_t read_mode_lr(int cpu_mode) */ 71FUNC read_mode_lr , : 72 push {r4, lr} 73 mrs r4, cpsr /* save cpsr */ 74 bl temp_set_mode 75 msr cpsr, r0 /* set the new mode */ 76 mov r0, lr /* get the function result */ 77 msr cpsr, r4 /* back to the old mode */ 78 pop {r4, pc} 79END_FUNC read_mode_lr 80