1/* 2 * Copyright (c) 2014, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28/* 29 * Copyright (c) 2008-2010 Travis Geiselbrecht 30 * 31 * Permission is hereby granted, free of charge, to any person obtaining 32 * a copy of this software and associated documentation files 33 * (the "Software"), to deal in the Software without restriction, 34 * including without limitation the rights to use, copy, modify, merge, 35 * publish, distribute, sublicense, and/or sell copies of the Software, 36 * and to permit persons to whom the Software is furnished to do so, 37 * subject to the following conditions: 38 * 39 * The above copyright notice and this permission notice shall be 40 * included in all copies or substantial portions of the Software. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 43 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 44 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 45 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 46 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 47 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 48 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 49 */ 50 51#include <platform_config.h> 52 53#ifndef SMALL_PAGE_SIZE 54#define SMALL_PAGE_SIZE 4096 55#endif 56#ifndef ROUNDUP 57#define ROUNDUP(x, y) ((((x) + (y) - 1) / (y)) * (y)) 58#endif 59 60OUTPUT_FORMAT(CFG_KERN_LINKER_FORMAT) 61OUTPUT_ARCH(CFG_KERN_LINKER_ARCH) 62 63ENTRY(_start) 64SECTIONS 65{ 66 . = CFG_TEE_LOAD_ADDR; 67 68 __text_start = .; 69 __flatmap_unpg_rx_start = __text_start; 70 71 .text : { 72 KEEP(*(.text.boot.vectab1)) 73 KEEP(*(.text.boot.vectab2)) 74 KEEP(*(.text.boot)) 75 76 . = ALIGN(8); 77 __initcall_start = .; 78 KEEP(*(.initcall1)) 79 KEEP(*(.initcall2)) 80 KEEP(*(.initcall3)) 81 KEEP(*(.initcall4)) 82 __initcall_end = .; 83 84#ifdef CFG_WITH_PAGER 85 *(.text) 86/* Include list of sections needed for paging */ 87#include <text_unpaged.ld.S> 88#else 89 *(.text .text.*) 90#endif 91 *(.sram.text.glue_7* .gnu.linkonce.t.*) 92 . = ALIGN(8); 93 } 94 __text_end = .; 95 96 __flatmap_unpg_rx_size = . - __flatmap_unpg_rx_start; 97 __flatmap_unpg_ro_start = .; 98 99 .rodata : ALIGN(8) { 100 __rodata_start = .; 101 *(.gnu.linkonce.r.*) 102#ifdef CFG_WITH_PAGER 103 *(.rodata .rodata.__unpaged) 104#include <rodata_unpaged.ld.S> 105#else 106#ifdef CFG_DT 107 __rodata_dtdrv_start = .; 108 KEEP(*(.rodata.dtdrv)) 109 __rodata_dtdrv_end = .; 110#endif 111 *(.rodata .rodata.*) 112 113 /* 114 * 8 to avoid unwanted padding between __start_ta_head_section 115 * and the first structure in ta_head_section, in 64-bit 116 * builds 117 */ 118 . = ALIGN(8); 119 __start_ta_head_section = . ; 120 KEEP(*(ta_head_section)) 121 __stop_ta_head_section = . ; 122 . = ALIGN(8); 123 __start_phys_mem_map_section = . ; 124 KEEP(*(phys_mem_map_section)) 125 __end_phys_mem_map_section = . ; 126 . = ALIGN(8); 127 __start_phys_sdp_mem_section = . ; 128 KEEP(*(phys_sdp_mem_section)) 129 __end_phys_sdp_mem_section = . ; 130#endif 131 . = ALIGN(8); 132 __rodata_end = .; 133 } 134 135 .interp : { *(.interp) } 136 .hash : { *(.hash) } 137 .dynsym : { *(.dynsym) } 138 .dynstr : { *(.dynstr) } 139 .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) } 140 .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) } 141 .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) } 142 .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) } 143 .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } 144 .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } 145 .rel.got : { *(.rel.got) } 146 .rela.got : { *(.rela.got) } 147 .rel.ctors : { *(.rel.ctors) } 148 .rela.ctors : { *(.rela.ctors) } 149 .rel.dtors : { *(.rel.dtors) } 150 .rela.dtors : { *(.rela.dtors) } 151 .rel.init : { *(.rel.init) } 152 .rela.init : { *(.rela.init) } 153 .rel.fini : { *(.rel.fini) } 154 .rela.fini : { *(.rela.fini) } 155 .rel.bss : { *(.rel.bss) } 156 .rela.bss : { *(.rela.bss) } 157 .rel.plt : { *(.rel.plt) } 158 .rela.plt : { *(.rela.plt) } 159 .init : { *(.init) } =0x9090 160 .plt : { *(.plt) } 161 162 /* .ARM.exidx is sorted, so has to go in its own output section. */ 163 .ARM.exidx : { 164 __exidx_start = .; 165 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 166 __exidx_end = .; 167 } 168 169 .ARM.extab : { 170 __extab_start = .; 171 *(.ARM.extab*) 172 __extab_end = .; 173 } 174 175 /* Start page aligned read-write memory */ 176#ifdef CFG_CORE_RWDATA_NOEXEC 177 . = ALIGN(SMALL_PAGE_SIZE); 178#endif 179 __flatmap_unpg_ro_size = . - __flatmap_unpg_ro_start; 180 __flatmap_unpg_rw_start = .; 181 182 .data : ALIGN(8) { 183 /* writable data */ 184 __data_start_rom = .; 185 /* in one segment binaries, the rom data address is on top 186 of the ram data address */ 187 __early_bss_start = .; 188 *(.early_bss .early_bss.*) 189 . = ALIGN(8); 190 __early_bss_end = .; 191 __data_start = .; 192 *(.data .data.* .gnu.linkonce.d.*) 193 . = ALIGN(8); 194 } 195 196 .ctors : ALIGN(8) { 197 __ctor_list = .; 198 KEEP(*(.ctors .ctors.* .init_array .init_array.*)) 199 __ctor_end = .; 200 } 201 .dtors : ALIGN(8) { 202 __dtor_list = .; 203 KEEP(*(.dtors .dtors.* .fini_array .fini_array.*)) 204 __dtor_end = .; 205 } 206 .got : { *(.got.plt) *(.got) } 207 .dynamic : { *(.dynamic) } 208 209 __data_end = .; 210 /* unintialized data */ 211 .bss : ALIGN(8) { 212 __bss_start = .; 213 *(.bss .bss.*) 214 *(.gnu.linkonce.b.*) 215 *(COMMON) 216 . = ALIGN(8); 217 __bss_end = .; 218 } 219 220 .heap1 (NOLOAD) : { 221 /* 222 * We're keeping track of the padding added before the 223 * .nozi section so we can do something useful with 224 * this otherwise wasted memory. 225 */ 226 __heap1_start = .; 227#ifndef CFG_WITH_PAGER 228 . += CFG_CORE_HEAP_SIZE; 229#endif 230 . = ALIGN(16 * 1024); 231 __heap1_end = .; 232 } 233 234 /* 235 * Uninitialized data that shouldn't be zero initialized at 236 * runtime. 237 * 238 * L1 mmu table requires 16 KiB alignment 239 */ 240 .nozi (NOLOAD) : { 241 __nozi_start = .; 242 ASSERT(!(__nozi_start & (16 * 1024 - 1)), "align nozi to 16kB"); 243 244 KEEP(*(.nozi .nozi.*)) 245 . = ALIGN(16); 246 __nozi_end = .; 247 __nozi_stack_start = .; 248 KEEP(*(.nozi_stack)) 249 . = ALIGN(8); 250 __nozi_stack_end = .; 251 } 252 253#ifdef CFG_WITH_PAGER 254 .heap2 (NOLOAD) : { 255 __heap2_start = .; 256 /* 257 * Reserve additional memory for heap, the total should be 258 * at least CFG_CORE_HEAP_SIZE, but count what has already 259 * been reserved in .heap1 260 */ 261 . += CFG_CORE_HEAP_SIZE - (__heap1_end - __heap1_start); 262 . = ALIGN(SMALL_PAGE_SIZE); 263 __heap2_end = .; 264 } 265 266 /* Start page aligned read-only memory */ 267 __flatmap_unpg_rw_size = . - __flatmap_unpg_rw_start; 268 269 __init_start = .; 270 __flatmap_init_rx_start = .; 271 272 ASSERT(!(__flatmap_init_rx_start & (SMALL_PAGE_SIZE - 1)), 273 "read-write memory is not paged aligned") 274 275 .text_init : { 276/* 277 * Include list of sections needed for boot initialization, this list 278 * overlaps with unpaged.ld.S but since unpaged.ld.S is first all those 279 * sections will go into the unpaged area. 280 */ 281#include <text_init.ld.S> 282 . = ALIGN(8); 283 } 284 285 __flatmap_init_rx_size = . - __flatmap_init_rx_start; 286 __flatmap_init_ro_start = .; 287 288 .rodata_init : { 289#include <rodata_init.ld.S> 290 . = ALIGN(8); 291 __start_phys_mem_map_section = . ; 292 KEEP(*(phys_mem_map_section)) 293 __end_phys_mem_map_section = . ; 294 . = ALIGN(8); 295 __start_phys_sdp_mem_section = . ; 296 KEEP(*(phys_sdp_mem_section)) 297 __end_phys_sdp_mem_section = . ; 298 . = ALIGN(8); 299 } 300 __rodata_init_end = .; 301 302 __init_end = ROUNDUP(__rodata_init_end, SMALL_PAGE_SIZE); 303 __init_size = __init_end - __init_start; 304 305 /* vcore flat map stops here. No need to page align, rodata follows. */ 306 __flatmap_init_ro_size = __init_end - __flatmap_init_ro_start; 307 308 .text_pageable : ALIGN(8) { 309 *(.text*) 310 . = ALIGN(8); 311 } 312 313 .rodata_pageable : ALIGN(8) { 314#ifdef CFG_DT 315 __rodata_dtdrv_start = .; 316 KEEP(*(.rodata.dtdrv)) 317 __rodata_dtdrv_end = .; 318#endif 319 *(.rodata*) 320 /* 321 * 8 to avoid unwanted padding between __start_ta_head_section 322 * and the first structure in ta_head_section, in 64-bit 323 * builds 324 */ 325 . = ALIGN(8); 326 __start_ta_head_section = . ; 327 KEEP(*(ta_head_section)) 328 __stop_ta_head_section = . ; 329 . = ALIGN(SMALL_PAGE_SIZE); 330 } 331 332 __pageable_part_end = .; 333 __pageable_part_start = __init_end; 334 __pageable_start = __init_start; 335 __pageable_end = __pageable_part_end; 336 337 /* 338 * Assign a safe spot to store the hashes of the pages before 339 * heap is initialized. 340 */ 341 __tmp_hashes_start = __init_end; 342 __tmp_hashes_size = ((__pageable_end - __pageable_start) / 343 SMALL_PAGE_SIZE) * 32; 344 __tmp_hashes_end = __tmp_hashes_start + __tmp_hashes_size; 345 346 __init_mem_usage = __tmp_hashes_end - CFG_TEE_LOAD_ADDR; 347 348 ASSERT(CFG_TEE_LOAD_ADDR >= CFG_TEE_RAM_START, 349 "Load address before start of physical memory") 350 ASSERT(CFG_TEE_LOAD_ADDR < (CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE), 351 "Load address after end of physical memory") 352 ASSERT(__tmp_hashes_end < (CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE), 353 "OP-TEE can't fit init part into available physical memory") 354 ASSERT((CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE - __init_end) > 355 SMALL_PAGE_SIZE, "Too few free pages to initialize paging") 356 357 358#endif /*CFG_WITH_PAGER*/ 359 360#ifdef CFG_CORE_SANITIZE_KADDRESS 361 . = CFG_TEE_RAM_START + (CFG_TEE_RAM_VA_SIZE * 8) / 9 - 8; 362 . = ALIGN(8); 363 .asan_shadow : { 364 __asan_shadow_start = .; 365 . += CFG_TEE_RAM_VA_SIZE / 9; 366 __asan_shadow_end = .; 367 } 368#endif /*CFG_CORE_SANITIZE_KADDRESS*/ 369 370 __end = .; 371 372#ifndef CFG_WITH_PAGER 373 __init_size = __data_end - CFG_TEE_LOAD_ADDR; 374 __init_mem_usage = __end - CFG_TEE_LOAD_ADDR; 375#endif 376 . = CFG_TEE_RAM_START + CFG_TEE_RAM_VA_SIZE; 377 378 _end_of_ram = .; 379 380#ifndef CFG_WITH_PAGER 381 __flatmap_unpg_rw_size = _end_of_ram - __flatmap_unpg_rw_start; 382#endif 383 384 /DISCARD/ : { 385 /* Strip unnecessary stuff */ 386 *(.comment .note .eh_frame) 387 /* Strip meta variables */ 388 *(__keep_meta_vars*) 389 } 390 391} 392 393/* Unpaged read-only memories */ 394PROVIDE(__vcore_unpg_rx_start = __flatmap_unpg_rx_start); 395PROVIDE(__vcore_unpg_ro_start = __flatmap_unpg_ro_start); 396PROVIDE(__vcore_unpg_rx_size = __flatmap_unpg_rx_size + 397 __flatmap_unpg_ro_size); 398PROVIDE(__vcore_unpg_ro_size = 0); 399 400/* Unpaged read-write memory */ 401PROVIDE(__vcore_unpg_rw_start = __flatmap_unpg_rw_start); 402PROVIDE(__vcore_unpg_rw_size = __flatmap_unpg_rw_size); 403 404#ifdef CFG_WITH_PAGER 405/* 406 * Core init mapping shall cover up to end of the physical RAM. 407 * This is required since the hash table is appended to the 408 * binary data after the firmware build sequence. 409 */ 410#define __FLATMAP_PAGER_TRAILING_SPACE \ 411 (CFG_TEE_RAM_START + CFG_TEE_RAM_PH_SIZE - \ 412 (__flatmap_init_ro_start + __flatmap_init_ro_size)) 413 414/* Paged/init read-only memories */ 415PROVIDE(__vcore_init_rx_start = __flatmap_init_rx_start); 416PROVIDE(__vcore_init_ro_start = __flatmap_init_ro_start); 417PROVIDE(__vcore_init_rx_size = __flatmap_init_rx_size + 418 __flatmap_init_ro_size + 419 __FLATMAP_PAGER_TRAILING_SPACE); 420PROVIDE(__vcore_init_ro_size = 0); 421#endif /* CFG_WITH_PAGER */ 422