1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2015-2022, Linaro Limited 4 * Copyright (c) 2021, Arm Limited 5 */ 6 7#include <platform_config.h> 8 9#include <arm64_macros.S> 10#include <arm.h> 11#include <asm.S> 12#include <generated/asm-defines.h> 13#include <keep.h> 14#include <kernel/thread_private.h> 15#include <sm/optee_smc.h> 16#include <sm/teesmc_opteed.h> 17#include <sm/teesmc_opteed_macros.h> 18 19 /* 20 * Setup SP_EL0 and SPEL1, SP will be set to SP_EL0. 21 * SP_EL0 is assigned: 22 * stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD 23 * SP_EL1 is assigned thread_core_local[cpu_id] 24 */ 25 .macro set_sp 26 bl __get_core_pos 27 cmp x0, #CFG_TEE_CORE_NB_CORE 28 /* Unsupported CPU, park it before it breaks something */ 29 bge unhandled_cpu 30 add x0, x0, #1 31 adr_l x1, stack_tmp_stride 32 ldr w1, [x1] 33 mul x1, x0, x1 34 35 /* x0 = stack_tmp - STACK_TMP_GUARD */ 36 adr_l x2, stack_tmp_rel 37 ldr w0, [x2] 38 add x0, x0, x2 39 40 msr spsel, #0 41 add sp, x1, x0 42 bl thread_get_core_local 43 msr spsel, #1 44 mov sp, x0 45 msr spsel, #0 46 .endm 47 48 .macro read_feat_mte reg 49 mrs \reg, id_aa64pfr1_el1 50 ubfx \reg, \reg, #ID_AA64PFR1_EL1_MTE_SHIFT, #4 51 .endm 52 53 .macro set_sctlr_el1 54 mrs x0, sctlr_el1 55 orr x0, x0, #SCTLR_I 56 orr x0, x0, #SCTLR_SA 57 orr x0, x0, #SCTLR_SPAN 58#if defined(CFG_CORE_RWDATA_NOEXEC) 59 orr x0, x0, #SCTLR_WXN 60#endif 61#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 62 orr x0, x0, #SCTLR_A 63#else 64 bic x0, x0, #SCTLR_A 65#endif 66#ifdef CFG_MEMTAG 67 read_feat_mte x1 68 cmp w1, #1 69 b.ls 111f 70 orr x0, x0, #(SCTLR_ATA | SCTLR_ATA0) 71 bic x0, x0, #SCTLR_TCF_MASK 72 bic x0, x0, #SCTLR_TCF0_MASK 73111: 74#endif 75#if defined(CFG_TA_PAUTH) && defined(CFG_TA_BTI) 76 orr x0, x0, #SCTLR_BT0 77#endif 78#if defined(CFG_CORE_PAUTH) && defined(CFG_CORE_BTI) 79 orr x0, x0, #SCTLR_BT1 80#endif 81 msr sctlr_el1, x0 82 .endm 83 84 .macro init_memtag_per_cpu 85 read_feat_mte x0 86 cmp w0, #1 87 b.ls 11f 88 89#ifdef CFG_TEE_CORE_DEBUG 90 /* 91 * This together with GCR_EL1.RRND = 0 will make the tags 92 * acquired with the irg instruction deterministic. 93 */ 94 mov_imm x0, 0xcafe00 95 msr rgsr_el1, x0 96 /* Avoid tag = 0x0 and 0xf */ 97 mov x0, #0 98#else 99 /* 100 * Still avoid tag = 0x0 and 0xf as we use that tag for 101 * everything which isn't explicitly tagged. Setting 102 * GCR_EL1.RRND = 1 to allow an implementation specific 103 * method of generating the tags. 104 */ 105 mov x0, #GCR_EL1_RRND 106#endif 107 orr x0, x0, #1 108 orr x0, x0, #(1 << 15) 109 msr gcr_el1, x0 110 111 /* 112 * Enable the tag checks on the current CPU. 113 * 114 * Depends on boot_init_memtag() having cleared tags for 115 * TEE core memory. Well, not really, addresses with the 116 * tag value 0b0000 will use unchecked access due to 117 * TCR_TCMA0. 118 */ 119 mrs x0, tcr_el1 120 orr x0, x0, #TCR_TBI0 121 orr x0, x0, #TCR_TCMA0 122 msr tcr_el1, x0 123 124 mrs x0, sctlr_el1 125 orr x0, x0, #SCTLR_TCF_SYNC 126 orr x0, x0, #SCTLR_TCF0_SYNC 127 msr sctlr_el1, x0 128 129 isb 13011: 131 .endm 132 133 .macro init_pauth_per_cpu 134 msr spsel, #1 135 ldp x0, x1, [sp, #THREAD_CORE_LOCAL_KEYS] 136 msr spsel, #0 137 write_apiakeyhi x0 138 write_apiakeylo x1 139 mrs x0, sctlr_el1 140 orr x0, x0, #SCTLR_ENIA 141 msr sctlr_el1, x0 142 isb 143 .endm 144 145FUNC _start , : 146 /* 147 * If CFG_CORE_FFA is enabled, then x0 if non-NULL holds the TOS FW 148 * config [1] address, else x0 if non-NULL holds the pagable part 149 * address. 150 * 151 * [1] A TF-A concept: TOS_FW_CONFIG - Trusted OS Firmware 152 * configuration file. Used by Trusted OS (BL32), that is, OP-TEE 153 * here. 154 */ 155 mov x19, x0 156#if defined(CFG_DT_ADDR) 157 ldr x20, =CFG_DT_ADDR 158#else 159 mov x20, x2 /* Save DT address */ 160#endif 161 162 adr x0, reset_vect_table 163 msr vbar_el1, x0 164 isb 165 166 set_sctlr_el1 167 isb 168 169#ifdef CFG_WITH_PAGER 170 /* 171 * Move init code into correct location and move hashes to a 172 * temporary safe location until the heap is initialized. 173 * 174 * The binary is built as: 175 * [Pager code, rodata and data] : In correct location 176 * [Init code and rodata] : Should be copied to __init_start 177 * [struct boot_embdata + data] : Should be saved before 178 * initializing pager, first uint32_t tells the length of the data 179 */ 180 adr x0, __init_start /* dst */ 181 adr x1, __data_end /* src */ 182 adr x2, __init_end 183 sub x2, x2, x0 /* init len */ 184 ldr w4, [x1, x2] /* length of hashes etc */ 185 add x2, x2, x4 /* length of init and hashes etc */ 186 /* Copy backwards (as memmove) in case we're overlapping */ 187 add x0, x0, x2 /* __init_start + len */ 188 add x1, x1, x2 /* __data_end + len */ 189 adr x3, cached_mem_end 190 str x0, [x3] 191 adr x2, __init_start 192copy_init: 193 ldp x3, x4, [x1, #-16]! 194 stp x3, x4, [x0, #-16]! 195 cmp x0, x2 196 b.gt copy_init 197#else 198 /* 199 * The binary is built as: 200 * [Core, rodata and data] : In correct location 201 * [struct boot_embdata + data] : Should be moved to __end, first 202 * uint32_t tells the length of the struct + data 203 */ 204 adr_l x0, __end /* dst */ 205 adr_l x1, __data_end /* src */ 206 ldr w2, [x1] /* struct boot_embdata::total_len */ 207 /* Copy backwards (as memmove) in case we're overlapping */ 208 add x0, x0, x2 209 add x1, x1, x2 210 adr x3, cached_mem_end 211 str x0, [x3] 212 adr_l x2, __end 213 214copy_init: 215 ldp x3, x4, [x1, #-16]! 216 stp x3, x4, [x0, #-16]! 217 cmp x0, x2 218 b.gt copy_init 219#endif 220 221 /* 222 * Clear .bss, this code obviously depends on the linker keeping 223 * start/end of .bss at least 8 byte aligned. 224 */ 225 adr_l x0, __bss_start 226 adr_l x1, __bss_end 227clear_bss: 228 str xzr, [x0], #8 229 cmp x0, x1 230 b.lt clear_bss 231 232#ifdef CFG_VIRTUALIZATION 233 /* 234 * Clear .nex_bss, this code obviously depends on the linker keeping 235 * start/end of .bss at least 8 byte aligned. 236 */ 237 adr x0, __nex_bss_start 238 adr x1, __nex_bss_end 239clear_nex_bss: 240 str xzr, [x0], #8 241 cmp x0, x1 242 b.lt clear_nex_bss 243#endif 244 245 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 246 set_sp 247 248 bl thread_init_thread_core_local 249 250 /* Enable aborts now that we can receive exceptions */ 251 msr daifclr, #DAIFBIT_ABT 252 253 /* 254 * Invalidate dcache for all memory used during initialization to 255 * avoid nasty surprices when the cache is turned on. We must not 256 * invalidate memory not used by OP-TEE since we may invalidate 257 * entries used by for instance ARM Trusted Firmware. 258 */ 259 adr_l x0, __text_start 260 ldr x1, cached_mem_end 261 sub x1, x1, x0 262 bl dcache_cleaninv_range 263 264 /* Enable Console */ 265 bl console_init 266 267#ifdef CFG_MEMTAG 268 /* 269 * If FEAT_MTE2 is available, initializes the memtag callbacks. 270 * Tags for OP-TEE core memory are then cleared to make it safe to 271 * enable MEMTAG below. 272 */ 273 bl boot_init_memtag 274#endif 275 276#ifdef CFG_CORE_ASLR 277 mov x0, x20 278 bl get_aslr_seed 279#else 280 mov x0, #0 281#endif 282 283 adr x1, boot_mmu_config 284 bl core_init_mmu_map 285 286#ifdef CFG_CORE_ASLR 287 /* 288 * Process relocation information again updating for the new 289 * offset. We're doing this now before MMU is enabled as some of 290 * the memory will become write protected. 291 */ 292 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 293 /* 294 * Update cached_mem_end address with load offset since it was 295 * calculated before relocation. 296 */ 297 adr x5, cached_mem_end 298 ldr x6, [x5] 299 add x6, x6, x0 300 str x6, [x5] 301 bl relocate 302#endif 303 304 bl __get_core_pos 305 bl enable_mmu 306#ifdef CFG_CORE_ASLR 307 /* 308 * Reinitialize console, since register_serial_console() has 309 * previously registered a PA and with ASLR the VA is different 310 * from the PA. 311 */ 312 bl console_init 313#endif 314 315#ifdef CFG_VIRTUALIZATION 316 /* 317 * Initialize partition tables for each partition to 318 * default_partition which has been relocated now to a different VA 319 */ 320 bl core_mmu_set_default_prtn_tbl 321#endif 322 323 mov x0, x19 /* pagable part address */ 324 mov x1, #-1 325 bl boot_init_primary_early 326 327#ifdef CFG_MEMTAG 328 init_memtag_per_cpu 329#endif 330 331#ifndef CFG_VIRTUALIZATION 332 mov x21, sp 333 adr_l x0, threads 334 ldr x0, [x0, #THREAD_CTX_STACK_VA_END] 335 mov sp, x0 336 bl thread_get_core_local 337 mov x22, x0 338 str wzr, [x22, #THREAD_CORE_LOCAL_FLAGS] 339#endif 340 mov x0, x20 /* DT address */ 341 bl boot_init_primary_late 342#ifdef CFG_CORE_PAUTH 343 init_pauth_per_cpu 344#endif 345 346#ifndef CFG_VIRTUALIZATION 347 mov x0, #THREAD_CLF_TMP 348 str w0, [x22, #THREAD_CORE_LOCAL_FLAGS] 349 mov sp, x21 350#endif 351 352#ifdef _CFG_CORE_STACK_PROTECTOR 353 /* Update stack canary value */ 354 bl plat_get_random_stack_canary 355 adr_l x5, __stack_chk_guard 356 str x0, [x5] 357#endif 358 359 /* 360 * In case we've touched memory that secondary CPUs will use before 361 * they have turned on their D-cache, clean and invalidate the 362 * D-cache before exiting to normal world. 363 */ 364 adr_l x0, __text_start 365 ldr x1, cached_mem_end 366 sub x1, x1, x0 367 bl dcache_cleaninv_range 368 369 370 /* 371 * Clear current thread id now to allow the thread to be reused on 372 * next entry. Matches the thread_init_boot_thread in 373 * boot.c. 374 */ 375#ifndef CFG_VIRTUALIZATION 376 bl thread_clr_boot_thread 377#endif 378 379#ifdef CFG_CORE_FFA 380 adr x0, cpu_on_handler 381 /* 382 * Compensate for the load offset since cpu_on_handler() is 383 * called with MMU off. 384 */ 385 ldr x1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 386 sub x0, x0, x1 387 bl thread_spmc_register_secondary_ep 388 b thread_ffa_msg_wait 389#else 390 /* 391 * Pass the vector address returned from main_init 392 * Compensate for the load offset since cpu_on_handler() is 393 * called with MMU off. 394 */ 395 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 396 adr x1, thread_vector_table 397 sub x1, x1, x0 398 mov x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 399 smc #0 400 /* SMC should not return */ 401 panic_at_smc_return 402#endif 403END_FUNC _start 404DECLARE_KEEP_INIT _start 405 406 .section .identity_map.data 407 .balign 8 408LOCAL_DATA cached_mem_end , : 409 .skip 8 410END_DATA cached_mem_end 411 412#ifdef CFG_CORE_ASLR 413LOCAL_FUNC relocate , : 414 /* x0 holds load offset */ 415#ifdef CFG_WITH_PAGER 416 adr_l x6, __init_end 417#else 418 adr_l x6, __end 419#endif 420 ldp w2, w3, [x6, #BOOT_EMBDATA_RELOC_OFFSET] 421 422 mov_imm x1, TEE_RAM_START 423 add x2, x2, x6 /* start of relocations */ 424 add x3, x3, x2 /* end of relocations */ 425 426 /* 427 * Relocations are not formatted as Rela64, instead they are in a 428 * compressed format created by get_reloc_bin() in 429 * scripts/gen_tee_bin.py 430 * 431 * All the R_AARCH64_RELATIVE relocations are translated into a 432 * list list of 32-bit offsets from TEE_RAM_START. At each address 433 * a 64-bit value pointed out which increased with the load offset. 434 */ 435 436#ifdef CFG_WITH_PAGER 437 /* 438 * With pager enabled we can only relocate the pager and init 439 * parts, the rest has to be done when a page is populated. 440 */ 441 sub x6, x6, x1 442#endif 443 444 b 2f 445 /* Loop over the relocation addresses and process all entries */ 4461: ldr w4, [x2], #4 447#ifdef CFG_WITH_PAGER 448 /* Skip too large addresses */ 449 cmp x4, x6 450 b.ge 2f 451#endif 452 add x4, x4, x1 453 ldr x5, [x4] 454 add x5, x5, x0 455 str x5, [x4] 456 4572: cmp x2, x3 458 b.ne 1b 459 460 ret 461END_FUNC relocate 462#endif 463 464/* 465 * void enable_mmu(unsigned long core_pos); 466 * 467 * This function depends on being mapped with in the identity map where 468 * physical address and virtual address is the same. After MMU has been 469 * enabled the instruction pointer will be updated to execute as the new 470 * offset instead. Stack pointers and the return address are updated. 471 */ 472LOCAL_FUNC enable_mmu , : , .identity_map 473 adr x1, boot_mmu_config 474 load_xregs x1, 0, 2, 6 475 /* 476 * x0 = core_pos 477 * x2 = tcr_el1 478 * x3 = mair_el1 479 * x4 = ttbr0_el1_base 480 * x5 = ttbr0_core_offset 481 * x6 = load_offset 482 */ 483 msr tcr_el1, x2 484 msr mair_el1, x3 485 486 /* 487 * ttbr0_el1 = ttbr0_el1_base + ttbr0_core_offset * core_pos 488 */ 489 madd x1, x5, x0, x4 490 msr ttbr0_el1, x1 491 msr ttbr1_el1, xzr 492 isb 493 494 /* Invalidate TLB */ 495 tlbi vmalle1 496 497 /* 498 * Make sure translation table writes have drained into memory and 499 * the TLB invalidation is complete. 500 */ 501 dsb sy 502 isb 503 504 /* Enable the MMU */ 505 mrs x1, sctlr_el1 506 orr x1, x1, #SCTLR_M 507 msr sctlr_el1, x1 508 isb 509 510 /* Update vbar */ 511 mrs x1, vbar_el1 512 add x1, x1, x6 513 msr vbar_el1, x1 514 isb 515 516 /* Invalidate instruction cache and branch predictor */ 517 ic iallu 518 isb 519 520 /* Enable I and D cache */ 521 mrs x1, sctlr_el1 522 orr x1, x1, #SCTLR_I 523 orr x1, x1, #SCTLR_C 524 msr sctlr_el1, x1 525 isb 526 527 /* Adjust stack pointers and return address */ 528 msr spsel, #1 529 add sp, sp, x6 530 msr spsel, #0 531 add sp, sp, x6 532 add x30, x30, x6 533 534 ret 535END_FUNC enable_mmu 536 537 .section .identity_map.data 538 .balign 8 539DATA boot_mmu_config , : /* struct core_mmu_config */ 540 .skip CORE_MMU_CONFIG_SIZE 541END_DATA boot_mmu_config 542 543FUNC cpu_on_handler , : 544 mov x19, x0 545 mov x20, x1 546 mov x21, x30 547 548 adr x0, reset_vect_table 549 msr vbar_el1, x0 550 isb 551 552 set_sctlr_el1 553 isb 554 555 /* Enable aborts now that we can receive exceptions */ 556 msr daifclr, #DAIFBIT_ABT 557 558 bl __get_core_pos 559 bl enable_mmu 560 561 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 562 set_sp 563 564#ifdef CFG_MEMTAG 565 init_memtag_per_cpu 566#endif 567#ifdef CFG_CORE_PAUTH 568 init_pauth_per_cpu 569#endif 570 571 mov x0, x19 572 mov x1, x20 573#ifdef CFG_CORE_FFA 574 bl boot_cpu_on_handler 575 b thread_ffa_msg_wait 576#else 577 mov x30, x21 578 b boot_cpu_on_handler 579#endif 580END_FUNC cpu_on_handler 581DECLARE_KEEP_PAGER cpu_on_handler 582 583LOCAL_FUNC unhandled_cpu , : 584 wfi 585 b unhandled_cpu 586END_FUNC unhandled_cpu 587 588LOCAL_DATA stack_tmp_rel , : 589 .word stack_tmp - stack_tmp_rel - STACK_TMP_GUARD 590END_DATA stack_tmp_rel 591 592 /* 593 * This macro verifies that the a given vector doesn't exceed the 594 * architectural limit of 32 instructions. This is meant to be placed 595 * immedately after the last instruction in the vector. It takes the 596 * vector entry as the parameter 597 */ 598 .macro check_vector_size since 599 .if (. - \since) > (32 * 4) 600 .error "Vector exceeds 32 instructions" 601 .endif 602 .endm 603 604 .section .identity_map, "ax", %progbits 605 .align 11 606LOCAL_FUNC reset_vect_table , :, .identity_map, , nobti 607 /* ----------------------------------------------------- 608 * Current EL with SP0 : 0x0 - 0x180 609 * ----------------------------------------------------- 610 */ 611SynchronousExceptionSP0: 612 b SynchronousExceptionSP0 613 check_vector_size SynchronousExceptionSP0 614 615 .align 7 616IrqSP0: 617 b IrqSP0 618 check_vector_size IrqSP0 619 620 .align 7 621FiqSP0: 622 b FiqSP0 623 check_vector_size FiqSP0 624 625 .align 7 626SErrorSP0: 627 b SErrorSP0 628 check_vector_size SErrorSP0 629 630 /* ----------------------------------------------------- 631 * Current EL with SPx: 0x200 - 0x380 632 * ----------------------------------------------------- 633 */ 634 .align 7 635SynchronousExceptionSPx: 636 b SynchronousExceptionSPx 637 check_vector_size SynchronousExceptionSPx 638 639 .align 7 640IrqSPx: 641 b IrqSPx 642 check_vector_size IrqSPx 643 644 .align 7 645FiqSPx: 646 b FiqSPx 647 check_vector_size FiqSPx 648 649 .align 7 650SErrorSPx: 651 b SErrorSPx 652 check_vector_size SErrorSPx 653 654 /* ----------------------------------------------------- 655 * Lower EL using AArch64 : 0x400 - 0x580 656 * ----------------------------------------------------- 657 */ 658 .align 7 659SynchronousExceptionA64: 660 b SynchronousExceptionA64 661 check_vector_size SynchronousExceptionA64 662 663 .align 7 664IrqA64: 665 b IrqA64 666 check_vector_size IrqA64 667 668 .align 7 669FiqA64: 670 b FiqA64 671 check_vector_size FiqA64 672 673 .align 7 674SErrorA64: 675 b SErrorA64 676 check_vector_size SErrorA64 677 678 /* ----------------------------------------------------- 679 * Lower EL using AArch32 : 0x0 - 0x180 680 * ----------------------------------------------------- 681 */ 682 .align 7 683SynchronousExceptionA32: 684 b SynchronousExceptionA32 685 check_vector_size SynchronousExceptionA32 686 687 .align 7 688IrqA32: 689 b IrqA32 690 check_vector_size IrqA32 691 692 .align 7 693FiqA32: 694 b FiqA32 695 check_vector_size FiqA32 696 697 .align 7 698SErrorA32: 699 b SErrorA32 700 check_vector_size SErrorA32 701 702END_FUNC reset_vect_table 703 704BTI(emit_aarch64_feature_1_and GNU_PROPERTY_AARCH64_FEATURE_1_BTI) 705