1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6#include <platform_config.h> 7 8#include <arm64_macros.S> 9#include <arm.h> 10#include <asm.S> 11#include <generated/asm-defines.h> 12#include <keep.h> 13#include <sm/optee_smc.h> 14#include <sm/teesmc_opteed.h> 15#include <sm/teesmc_opteed_macros.h> 16 17 /* 18 * Setup SP_EL0 and SPEL1, SP will be set to SP_EL0. 19 * SP_EL0 is assigned stack_tmp_export + cpu_id * stack_tmp_stride 20 * SP_EL1 is assigned thread_core_local[cpu_id] 21 */ 22 .macro set_sp 23 bl __get_core_pos 24 cmp x0, #CFG_TEE_CORE_NB_CORE 25 /* Unsupported CPU, park it before it breaks something */ 26 bge unhandled_cpu 27 adr x1, stack_tmp_stride 28 ldr w1, [x1] 29 mul x1, x0, x1 30 adrp x0, stack_tmp_export 31 add x0, x0, :lo12:stack_tmp_export 32 ldr x0, [x0] 33 msr spsel, #0 34 add sp, x1, x0 35 bl thread_get_core_local 36 msr spsel, #1 37 mov sp, x0 38 msr spsel, #0 39 .endm 40 41 .macro set_sctlr_el1 42 mrs x0, sctlr_el1 43 orr x0, x0, #SCTLR_I 44 orr x0, x0, #SCTLR_SA 45 orr x0, x0, #SCTLR_SPAN 46#if defined(CFG_CORE_RWDATA_NOEXEC) 47 orr x0, x0, #SCTLR_WXN 48#endif 49#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 50 orr x0, x0, #SCTLR_A 51#else 52 bic x0, x0, #SCTLR_A 53#endif 54 msr sctlr_el1, x0 55 .endm 56 57FUNC _start , : 58 mov x19, x0 /* Save pagable part address */ 59#if defined(CFG_DT_ADDR) 60 ldr x20, =CFG_DT_ADDR 61#else 62 mov x20, x2 /* Save DT address */ 63#endif 64 65 adr x0, reset_vect_table 66 msr vbar_el1, x0 67 isb 68 69 set_sctlr_el1 70 isb 71 72#ifdef CFG_WITH_PAGER 73 /* 74 * Move init code into correct location and move hashes to a 75 * temporary safe location until the heap is initialized. 76 * 77 * The binary is built as: 78 * [Pager code, rodata and data] : In correct location 79 * [Init code and rodata] : Should be copied to __init_start 80 * [struct boot_embdata + data] : Should be saved before 81 * initializing pager, first uint32_t tells the length of the data 82 */ 83 adr x0, __init_start /* dst */ 84 adr x1, __data_end /* src */ 85 adr x2, __init_end 86 sub x2, x2, x0 /* init len */ 87 ldr w4, [x1, x2] /* length of hashes etc */ 88 add x2, x2, x4 /* length of init and hashes etc */ 89 /* Copy backwards (as memmove) in case we're overlapping */ 90 add x0, x0, x2 /* __init_start + len */ 91 add x1, x1, x2 /* __data_end + len */ 92 adr x3, cached_mem_end 93 str x0, [x3] 94 adr x2, __init_start 95copy_init: 96 ldp x3, x4, [x1, #-16]! 97 stp x3, x4, [x0, #-16]! 98 cmp x0, x2 99 b.gt copy_init 100#else 101 /* 102 * The binary is built as: 103 * [Core, rodata and data] : In correct location 104 * [struct boot_embdata + data] : Should be moved to __end, first 105 * uint32_t tells the length of the struct + data 106 */ 107 adr_l x0, __end /* dst */ 108 adr_l x1, __data_end /* src */ 109 ldr w2, [x1] /* struct boot_embdata::total_len */ 110 /* Copy backwards (as memmove) in case we're overlapping */ 111 add x0, x0, x2 112 add x1, x1, x2 113 adr x3, cached_mem_end 114 str x0, [x3] 115 adr_l x2, __end 116 117copy_init: 118 ldp x3, x4, [x1, #-16]! 119 stp x3, x4, [x0, #-16]! 120 cmp x0, x2 121 b.gt copy_init 122#endif 123 124 /* 125 * Clear .bss, this code obviously depends on the linker keeping 126 * start/end of .bss at least 8 byte aligned. 127 */ 128 adr_l x0, __bss_start 129 adr_l x1, __bss_end 130clear_bss: 131 str xzr, [x0], #8 132 cmp x0, x1 133 b.lt clear_bss 134 135#ifdef CFG_VIRTUALIZATION 136 /* 137 * Clear .nex_bss, this code obviously depends on the linker keeping 138 * start/end of .bss at least 8 byte aligned. 139 */ 140 adr x0, __nex_bss_start 141 adr x1, __nex_bss_end 142clear_nex_bss: 143 str xzr, [x0], #8 144 cmp x0, x1 145 b.lt clear_nex_bss 146#endif 147 148 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 149 set_sp 150 151 bl thread_init_thread_core_local 152 153 /* Enable aborts now that we can receive exceptions */ 154 msr daifclr, #DAIFBIT_ABT 155 156 /* 157 * Invalidate dcache for all memory used during initialization to 158 * avoid nasty surprices when the cache is turned on. We must not 159 * invalidate memory not used by OP-TEE since we may invalidate 160 * entries used by for instance ARM Trusted Firmware. 161 */ 162 adr_l x0, __text_start 163 ldr x1, cached_mem_end 164 sub x1, x1, x0 165 bl dcache_cleaninv_range 166 167 /* Enable Console */ 168 bl console_init 169 170#ifdef CFG_CORE_ASLR 171 mov x0, x20 172 bl get_aslr_seed 173#else 174 mov x0, #0 175#endif 176 177 adr x1, boot_mmu_config 178 bl core_init_mmu_map 179 180#ifdef CFG_CORE_ASLR 181 /* 182 * Process relocation information again updating for the new 183 * offset. We're doing this now before MMU is enabled as some of 184 * the memory will become write protected. 185 */ 186 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 187 /* 188 * Update cached_mem_end address with load offset since it was 189 * calculated before relocation. 190 */ 191 adr x5, cached_mem_end 192 ldr x6, [x5] 193 add x6, x6, x0 194 str x6, [x5] 195 bl relocate 196#endif 197 198 bl __get_core_pos 199 bl enable_mmu 200#ifdef CFG_CORE_ASLR 201 /* 202 * Reinitialize console, since register_serial_console() has 203 * previously registered a PA and with ASLR the VA is different 204 * from the PA. 205 */ 206 bl console_init 207#endif 208 209 mov x0, x19 /* pagable part address */ 210 mov x1, #-1 211 mov x2, x20 /* DT address */ 212 bl boot_init_primary 213 214 /* 215 * In case we've touched memory that secondary CPUs will use before 216 * they have turned on their D-cache, clean and invalidate the 217 * D-cache before exiting to normal world. 218 */ 219 adr_l x0, __text_start 220 ldr x1, cached_mem_end 221 sub x1, x1, x0 222 bl dcache_cleaninv_range 223 224 225 /* 226 * Clear current thread id now to allow the thread to be reused on 227 * next entry. Matches the thread_init_boot_thread in 228 * boot.c. 229 */ 230#ifndef CFG_VIRTUALIZATION 231 bl thread_clr_boot_thread 232#endif 233 234#ifdef CFG_CORE_FFA 235 adr x0, cpu_on_handler 236 /* 237 * Compensate for the load offset since cpu_on_handler() is 238 * called with MMU off. 239 */ 240 ldr x1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 241 sub x0, x0, x1 242 bl ffa_secondary_cpu_boot_req 243 b thread_ffa_msg_wait 244#else 245 /* 246 * Pass the vector address returned from main_init 247 * Compensate for the load offset since cpu_on_handler() is 248 * called with MMU off. 249 */ 250 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 251 adr x1, thread_vector_table 252 sub x1, x1, x0 253 mov x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 254 smc #0 255 b . /* SMC should not return */ 256#endif 257END_FUNC _start 258DECLARE_KEEP_INIT _start 259 260 .balign 8 261LOCAL_DATA cached_mem_end , : 262 .skip 8 263END_DATA cached_mem_end 264 265#ifdef CFG_CORE_ASLR 266LOCAL_FUNC relocate , : 267 /* x0 holds load offset */ 268#ifdef CFG_WITH_PAGER 269 adr_l x6, __init_end 270#else 271 adr_l x6, __end 272#endif 273 ldp w2, w3, [x6, #BOOT_EMBDATA_RELOC_OFFSET] 274 275 mov_imm x1, TEE_RAM_START 276 add x2, x2, x6 /* start of relocations */ 277 add x3, x3, x2 /* end of relocations */ 278 279 /* 280 * Relocations are not formatted as Rela64, instead they are in a 281 * compressed format created by get_reloc_bin() in 282 * scripts/gen_tee_bin.py 283 * 284 * All the R_AARCH64_RELATIVE relocations are translated into a 285 * list list of 32-bit offsets from TEE_RAM_START. At each address 286 * a 64-bit value pointed out which increased with the load offset. 287 */ 288 289#ifdef CFG_WITH_PAGER 290 /* 291 * With pager enabled we can only relocate the pager and init 292 * parts, the rest has to be done when a page is populated. 293 */ 294 sub x6, x6, x1 295#endif 296 297 b 2f 298 /* Loop over the relocation addresses and process all entries */ 2991: ldr w4, [x2], #4 300#ifdef CFG_WITH_PAGER 301 /* Skip too large addresses */ 302 cmp x4, x6 303 b.ge 2f 304#endif 305 add x4, x4, x1 306 ldr x5, [x4] 307 add x5, x5, x0 308 str x5, [x4] 309 3102: cmp x2, x3 311 b.ne 1b 312 313 ret 314END_FUNC relocate 315#endif 316 317/* 318 * void enable_mmu(unsigned long core_pos); 319 * 320 * This function depends on being mapped with in the identity map where 321 * physical address and virtual address is the same. After MMU has been 322 * enabled the instruction pointer will be updated to execute as the new 323 * offset instead. Stack pointers and the return address are updated. 324 */ 325LOCAL_FUNC enable_mmu , : , .identity_map 326 adr x1, boot_mmu_config 327 load_xregs x1, 0, 2, 6 328 /* 329 * x0 = core_pos 330 * x2 = tcr_el1 331 * x3 = mair_el1 332 * x4 = ttbr0_el1_base 333 * x5 = ttbr0_core_offset 334 * x6 = load_offset 335 */ 336 msr tcr_el1, x2 337 msr mair_el1, x3 338 339 /* 340 * ttbr0_el1 = ttbr0_el1_base + ttbr0_core_offset * core_pos 341 */ 342 madd x1, x5, x0, x4 343 msr ttbr0_el1, x1 344 msr ttbr1_el1, xzr 345 isb 346 347 /* Invalidate TLB */ 348 tlbi vmalle1 349 350 /* 351 * Make sure translation table writes have drained into memory and 352 * the TLB invalidation is complete. 353 */ 354 dsb sy 355 isb 356 357 /* Enable the MMU */ 358 mrs x1, sctlr_el1 359 orr x1, x1, #SCTLR_M 360 msr sctlr_el1, x1 361 isb 362 363 /* Update vbar */ 364 mrs x1, vbar_el1 365 add x1, x1, x6 366 msr vbar_el1, x1 367 isb 368 369 /* Invalidate instruction cache and branch predictor */ 370 ic iallu 371 isb 372 373 /* Enable I and D cache */ 374 mrs x1, sctlr_el1 375 orr x1, x1, #SCTLR_I 376 orr x1, x1, #SCTLR_C 377 msr sctlr_el1, x1 378 isb 379 380 /* Adjust stack pointers and return address */ 381 msr spsel, #1 382 add sp, sp, x6 383 msr spsel, #0 384 add sp, sp, x6 385 add x30, x30, x6 386 387 ret 388END_FUNC enable_mmu 389 390 .balign 8 391DATA boot_mmu_config , : /* struct core_mmu_config */ 392 .skip CORE_MMU_CONFIG_SIZE 393END_DATA boot_mmu_config 394 395FUNC cpu_on_handler , : 396 mov x19, x0 397 mov x20, x1 398 mov x21, x30 399 400 adr x0, reset_vect_table 401 msr vbar_el1, x0 402 isb 403 404 set_sctlr_el1 405 isb 406 407 /* Enable aborts now that we can receive exceptions */ 408 msr daifclr, #DAIFBIT_ABT 409 410 bl __get_core_pos 411 bl enable_mmu 412 413 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 414 set_sp 415 416 mov x0, x19 417 mov x1, x20 418#ifdef CFG_CORE_FFA 419 bl boot_cpu_on_handler 420 b thread_ffa_msg_wait 421#else 422 mov x30, x21 423 b boot_cpu_on_handler 424#endif 425END_FUNC cpu_on_handler 426DECLARE_KEEP_PAGER cpu_on_handler 427 428LOCAL_FUNC unhandled_cpu , : 429 wfi 430 b unhandled_cpu 431END_FUNC unhandled_cpu 432 433 /* 434 * This macro verifies that the a given vector doesn't exceed the 435 * architectural limit of 32 instructions. This is meant to be placed 436 * immedately after the last instruction in the vector. It takes the 437 * vector entry as the parameter 438 */ 439 .macro check_vector_size since 440 .if (. - \since) > (32 * 4) 441 .error "Vector exceeds 32 instructions" 442 .endif 443 .endm 444 445 .section .identity_map, "ax", %progbits 446 .align 11 447LOCAL_FUNC reset_vect_table , :, .identity_map 448 /* ----------------------------------------------------- 449 * Current EL with SP0 : 0x0 - 0x180 450 * ----------------------------------------------------- 451 */ 452SynchronousExceptionSP0: 453 b SynchronousExceptionSP0 454 check_vector_size SynchronousExceptionSP0 455 456 .align 7 457IrqSP0: 458 b IrqSP0 459 check_vector_size IrqSP0 460 461 .align 7 462FiqSP0: 463 b FiqSP0 464 check_vector_size FiqSP0 465 466 .align 7 467SErrorSP0: 468 b SErrorSP0 469 check_vector_size SErrorSP0 470 471 /* ----------------------------------------------------- 472 * Current EL with SPx: 0x200 - 0x380 473 * ----------------------------------------------------- 474 */ 475 .align 7 476SynchronousExceptionSPx: 477 b SynchronousExceptionSPx 478 check_vector_size SynchronousExceptionSPx 479 480 .align 7 481IrqSPx: 482 b IrqSPx 483 check_vector_size IrqSPx 484 485 .align 7 486FiqSPx: 487 b FiqSPx 488 check_vector_size FiqSPx 489 490 .align 7 491SErrorSPx: 492 b SErrorSPx 493 check_vector_size SErrorSPx 494 495 /* ----------------------------------------------------- 496 * Lower EL using AArch64 : 0x400 - 0x580 497 * ----------------------------------------------------- 498 */ 499 .align 7 500SynchronousExceptionA64: 501 b SynchronousExceptionA64 502 check_vector_size SynchronousExceptionA64 503 504 .align 7 505IrqA64: 506 b IrqA64 507 check_vector_size IrqA64 508 509 .align 7 510FiqA64: 511 b FiqA64 512 check_vector_size FiqA64 513 514 .align 7 515SErrorA64: 516 b SErrorA64 517 check_vector_size SErrorA64 518 519 /* ----------------------------------------------------- 520 * Lower EL using AArch32 : 0x0 - 0x180 521 * ----------------------------------------------------- 522 */ 523 .align 7 524SynchronousExceptionA32: 525 b SynchronousExceptionA32 526 check_vector_size SynchronousExceptionA32 527 528 .align 7 529IrqA32: 530 b IrqA32 531 check_vector_size IrqA32 532 533 .align 7 534FiqA32: 535 b FiqA32 536 check_vector_size FiqA32 537 538 .align 7 539SErrorA32: 540 b SErrorA32 541 check_vector_size SErrorA32 542 543END_FUNC reset_vect_table 544