xref: /optee_os/core/arch/arm/kernel/entry_a64.S (revision 9f34db38245c9b3a4e6e7e63eb78a75e23ab2da3) 
1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (c) 2015-2022, Linaro Limited
4 * Copyright (c) 2021-2023, Arm Limited
5 */
6
7#include <platform_config.h>
8
9#include <arm64_macros.S>
10#include <arm.h>
11#include <asm.S>
12#include <generated/asm-defines.h>
13#include <keep.h>
14#include <kernel/thread_private.h>
15#include <mm/core_mmu.h>
16#include <sm/optee_smc.h>
17#include <sm/teesmc_opteed.h>
18#include <sm/teesmc_opteed_macros.h>
19
20	/*
21	 * Setup SP_EL0 and SPEL1, SP will be set to SP_EL0.
22	 * SP_EL0 is assigned:
23	 *   stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD
24	 * SP_EL1 is assigned thread_core_local[cpu_id]
25	 */
26	.macro set_sp
27		bl	__get_core_pos
28		cmp	x0, #CFG_TEE_CORE_NB_CORE
29		/* Unsupported CPU, park it before it breaks something */
30		bge	unhandled_cpu
31		add	x0, x0, #1
32		adr_l	x1, stack_tmp_stride
33		ldr	w1, [x1]
34		mul	x1, x0, x1
35
36		/* x0 = stack_tmp - STACK_TMP_GUARD */
37		adr_l	x2, stack_tmp_rel
38		ldr	w0, [x2]
39		add	x0, x0, x2
40
41		msr	spsel, #0
42		add	sp, x1, x0
43		bl	thread_get_core_local
44		msr	spsel, #1
45		mov	sp, x0
46		msr	spsel, #0
47	.endm
48
49	.macro read_feat_mte reg
50		mrs	\reg, id_aa64pfr1_el1
51		ubfx	\reg, \reg, #ID_AA64PFR1_EL1_MTE_SHIFT, #4
52	.endm
53
54	.macro read_feat_pan reg
55		mrs	\reg, id_mmfr3_el1
56		ubfx	\reg, \reg, #ID_MMFR3_EL1_PAN_SHIFT, #4
57	.endm
58
59	.macro set_sctlr_el1
60		mrs	x0, sctlr_el1
61		orr	x0, x0, #SCTLR_I
62		orr	x0, x0, #SCTLR_SA
63		orr	x0, x0, #SCTLR_SPAN
64#if defined(CFG_CORE_RWDATA_NOEXEC)
65		orr	x0, x0, #SCTLR_WXN
66#endif
67#if defined(CFG_SCTLR_ALIGNMENT_CHECK)
68		orr	x0, x0, #SCTLR_A
69#else
70		bic	x0, x0, #SCTLR_A
71#endif
72#ifdef CFG_MEMTAG
73		read_feat_mte x1
74		cmp	w1, #1
75		b.ls	111f
76		orr	x0, x0, #(SCTLR_ATA | SCTLR_ATA0)
77		bic	x0, x0, #SCTLR_TCF_MASK
78		bic	x0, x0, #SCTLR_TCF0_MASK
79111:
80#endif
81#if defined(CFG_TA_PAUTH) && defined(CFG_TA_BTI)
82		orr	x0, x0, #SCTLR_BT0
83#endif
84#if defined(CFG_CORE_PAUTH) && defined(CFG_CORE_BTI)
85		orr	x0, x0, #SCTLR_BT1
86#endif
87		msr	sctlr_el1, x0
88	.endm
89
90	.macro init_memtag_per_cpu
91		read_feat_mte x0
92		cmp	w0, #1
93		b.ls	11f
94
95#ifdef CFG_TEE_CORE_DEBUG
96		/*
97		 * This together with GCR_EL1.RRND = 0 will make the tags
98		 * acquired with the irg instruction deterministic.
99		 */
100		mov_imm	x0, 0xcafe00
101		msr	rgsr_el1, x0
102		/* Avoid tag = 0x0 and 0xf */
103		mov	x0, #0
104#else
105		/*
106		 * Still avoid tag = 0x0 and 0xf as we use that tag for
107		 * everything which isn't explicitly tagged. Setting
108		 * GCR_EL1.RRND = 1 to allow an implementation specific
109		 * method of generating the tags.
110		 */
111		mov	x0, #GCR_EL1_RRND
112#endif
113		orr	x0, x0, #1
114		orr	x0, x0, #(1 << 15)
115		msr	gcr_el1, x0
116
117		/*
118		 * Enable the tag checks on the current CPU.
119		 *
120		 * Depends on boot_init_memtag() having cleared tags for
121		 * TEE core memory. Well, not really, addresses with the
122		 * tag value 0b0000 will use unchecked access due to
123		 * TCR_TCMA0.
124		 */
125		mrs	x0, tcr_el1
126		orr	x0, x0, #TCR_TBI0
127		orr	x0, x0, #TCR_TCMA0
128		msr	tcr_el1, x0
129
130		mrs	x0, sctlr_el1
131		orr	x0, x0, #SCTLR_TCF_SYNC
132		orr	x0, x0, #SCTLR_TCF0_SYNC
133		msr	sctlr_el1, x0
134
135		isb
13611:
137	.endm
138
139	.macro init_pauth_secondary_cpu
140		msr	spsel, #1
141		ldp	x0, x1, [sp, #THREAD_CORE_LOCAL_KEYS]
142		msr	spsel, #0
143		write_apiakeyhi x0
144		write_apiakeylo x1
145		mrs	x0, sctlr_el1
146		orr	x0, x0, #SCTLR_ENIA
147		msr	sctlr_el1, x0
148		isb
149	.endm
150
151	.macro init_pan
152		read_feat_pan x0
153		cmp	x0, #0
154		b.eq	1f
155		mrs	x0, sctlr_el1
156		bic	x0, x0, #SCTLR_SPAN
157		msr	sctlr_el1, x0
158		write_pan_enable
159	1:
160	.endm
161
162FUNC _start , :
163	/*
164	 * Temporary copy of boot argument registers, will be passed to
165	 * boot_save_args() further down.
166	 */
167	mov	x19, x0
168	mov	x20, x1
169	mov	x21, x2
170	mov	x22, x3
171
172	adr	x0, reset_vect_table
173	msr	vbar_el1, x0
174	isb
175
176#ifdef CFG_PAN
177	init_pan
178#endif
179
180	set_sctlr_el1
181	isb
182
183#ifdef CFG_WITH_PAGER
184	/*
185	 * Move init code into correct location and move hashes to a
186	 * temporary safe location until the heap is initialized.
187	 *
188	 * The binary is built as:
189	 * [Pager code, rodata and data] : In correct location
190	 * [Init code and rodata] : Should be copied to __init_start
191	 * [struct boot_embdata + data] : Should be saved before
192	 * initializing pager, first uint32_t tells the length of the data
193	 */
194	adr	x0, __init_start	/* dst */
195	adr	x1, __data_end		/* src */
196	adr	x2, __init_end
197	sub	x2, x2, x0		/* init len */
198	ldr	w4, [x1, x2]		/* length of hashes etc */
199	add	x2, x2, x4		/* length of init and hashes etc */
200	/* Copy backwards (as memmove) in case we're overlapping */
201	add	x0, x0, x2		/* __init_start + len */
202	add	x1, x1, x2		/* __data_end + len */
203	adr	x3, cached_mem_end
204	str	x0, [x3]
205	adr	x2, __init_start
206copy_init:
207	ldp	x3, x4, [x1, #-16]!
208	stp	x3, x4, [x0, #-16]!
209	cmp	x0, x2
210	b.gt	copy_init
211#else
212	/*
213	 * The binary is built as:
214	 * [Core, rodata and data] : In correct location
215	 * [struct boot_embdata + data] : Should be moved to __end, first
216	 * uint32_t tells the length of the struct + data
217	 */
218	adr_l	x0, __end		/* dst */
219	adr_l	x1, __data_end		/* src */
220	ldr	w2, [x1]		/* struct boot_embdata::total_len */
221	/* Copy backwards (as memmove) in case we're overlapping */
222	add	x0, x0, x2
223	add	x1, x1, x2
224	adr	x3, cached_mem_end
225	str	x0, [x3]
226	adr_l	x2, __end
227
228copy_init:
229	ldp	x3, x4, [x1, #-16]!
230	stp	x3, x4, [x0, #-16]!
231	cmp	x0, x2
232	b.gt	copy_init
233#endif
234
235	/*
236	 * Clear .bss, this code obviously depends on the linker keeping
237	 * start/end of .bss at least 8 byte aligned.
238	 */
239	adr_l	x0, __bss_start
240	adr_l	x1, __bss_end
241clear_bss:
242	str	xzr, [x0], #8
243	cmp	x0, x1
244	b.lt	clear_bss
245
246#ifdef CFG_NS_VIRTUALIZATION
247	/*
248	 * Clear .nex_bss, this code obviously depends on the linker keeping
249	 * start/end of .bss at least 8 byte aligned.
250	 */
251	adr_l	x0, __nex_bss_start
252	adr_l	x1, __nex_bss_end
253clear_nex_bss:
254	str	xzr, [x0], #8
255	cmp	x0, x1
256	b.lt	clear_nex_bss
257#endif
258
259
260#if defined(CFG_CORE_PHYS_RELOCATABLE)
261	/*
262	 * Save the base physical address, it will not change after this
263	 * point.
264	 */
265	adr_l	x2, core_mmu_tee_load_pa
266	adr	x1, _start		/* Load address */
267	str	x1, [x2]
268
269	mov_imm	x0, TEE_LOAD_ADDR	/* Compiled load address */
270	sub	x0, x1, x0		/* Relocatation offset */
271
272	cbz	x0, 1f
273	bl	relocate
2741:
275#endif
276
277	/* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */
278	set_sp
279
280	bl	thread_init_thread_core_local
281
282	/* Enable aborts now that we can receive exceptions */
283	msr	daifclr, #DAIFBIT_ABT
284
285	/*
286	 * Invalidate dcache for all memory used during initialization to
287	 * avoid nasty surprices when the cache is turned on. We must not
288	 * invalidate memory not used by OP-TEE since we may invalidate
289	 * entries used by for instance ARM Trusted Firmware.
290	 */
291	adr_l	x0, __text_start
292	ldr	x1, cached_mem_end
293	sub	x1, x1, x0
294	bl	dcache_cleaninv_range
295
296	/* Enable Console */
297	bl	console_init
298
299	mov	x0, x19
300	mov	x1, x20
301	mov	x2, x21
302	mov	x3, x22
303	mov	x4, xzr
304	bl	boot_save_args
305
306#ifdef CFG_MEMTAG
307	/*
308	 * If FEAT_MTE2 is available, initializes the memtag callbacks.
309	 * Tags for OP-TEE core memory are then cleared to make it safe to
310	 * enable MEMTAG below.
311	 */
312	bl	boot_init_memtag
313#endif
314
315#ifdef CFG_CORE_ASLR
316	bl	get_aslr_seed
317#ifdef CFG_CORE_ASLR_SEED
318	mov_imm	x0, CFG_CORE_ASLR_SEED
319#endif
320#else
321	mov	x0, #0
322#endif
323
324	adr	x1, boot_mmu_config
325	bl	core_init_mmu_map
326
327#ifdef CFG_CORE_ASLR
328	/*
329	 * Process relocation information again updating for the virtual
330	 * map offset. We're doing this now before MMU is enabled as some
331	 * of the memory will become write protected.
332	 */
333	ldr	x0, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
334	cbz	x0, 1f
335	/*
336	 * Update cached_mem_end address with load offset since it was
337	 * calculated before relocation.
338	 */
339	adr	x5, cached_mem_end
340	ldr	x6, [x5]
341	add	x6, x6, x0
342	str	x6, [x5]
343	adr	x1, _start		/* Load address */
344	bl	relocate
3451:
346#endif
347
348	bl	__get_core_pos
349	bl	enable_mmu
350#ifdef CFG_CORE_ASLR
351	/*
352	 * Reinitialize console, since register_serial_console() has
353	 * previously registered a PA and with ASLR the VA is different
354	 * from the PA.
355	 */
356	bl	console_init
357#endif
358
359#ifdef CFG_MEMTAG
360	bl	boot_clear_memtag
361#endif
362
363#ifdef CFG_NS_VIRTUALIZATION
364	/*
365	 * Initialize partition tables for each partition to
366	 * default_partition which has been relocated now to a different VA
367	 */
368	bl	core_mmu_set_default_prtn_tbl
369#endif
370
371	bl	boot_init_primary_early
372
373#ifdef CFG_MEMTAG
374	init_memtag_per_cpu
375#endif
376
377#ifndef CFG_NS_VIRTUALIZATION
378	mov	x23, sp
379	adr_l	x0, threads
380	ldr	x0, [x0, #THREAD_CTX_STACK_VA_END]
381	mov	sp, x0
382	bl	thread_get_core_local
383	mov	x24, x0
384	str	wzr, [x24, #THREAD_CORE_LOCAL_FLAGS]
385#endif
386	bl	boot_init_primary_late
387#ifdef CFG_CORE_PAUTH
388	adr_l	x0, threads
389	ldp	x1, x2, [x0, #THREAD_CTX_KEYS]
390	write_apiakeyhi x1
391	write_apiakeylo x2
392	mrs	x0, sctlr_el1
393	orr	x0, x0, #SCTLR_ENIA
394	msr	sctlr_el1, x0
395	isb
396#endif
397	bl	boot_init_primary_final
398
399#ifndef CFG_NS_VIRTUALIZATION
400	mov	x0, #THREAD_CLF_TMP
401	str     w0, [x24, #THREAD_CORE_LOCAL_FLAGS]
402	mov	sp, x23
403#ifdef CFG_CORE_PAUTH
404	ldp	x0, x1, [x24, #THREAD_CORE_LOCAL_KEYS]
405	write_apiakeyhi x0
406	write_apiakeylo x1
407	isb
408#endif
409#endif
410
411#ifdef _CFG_CORE_STACK_PROTECTOR
412	/* Update stack canary value */
413	sub	sp, sp, #0x10
414	mov	x0, sp
415	mov	x1, #1
416	mov	x2, #0x8
417	bl	plat_get_random_stack_canaries
418	ldr	x0, [sp]
419	adr_l	x5, __stack_chk_guard
420	str	x0, [x5]
421	add	sp, sp, #0x10
422#endif
423
424	/*
425	 * In case we've touched memory that secondary CPUs will use before
426	 * they have turned on their D-cache, clean and invalidate the
427	 * D-cache before exiting to normal world.
428	 */
429	adr_l	x0, __text_start
430	ldr	x1, cached_mem_end
431	sub	x1, x1, x0
432	bl	dcache_cleaninv_range
433
434
435	/*
436	 * Clear current thread id now to allow the thread to be reused on
437	 * next entry. Matches the thread_init_boot_thread in
438	 * boot.c.
439	 */
440#ifndef CFG_NS_VIRTUALIZATION
441	bl 	thread_clr_boot_thread
442#endif
443
444#ifdef CFG_CORE_FFA
445	adr	x0, cpu_on_handler
446	/*
447	 * Compensate for the virtual map offset since cpu_on_handler() is
448	 * called with MMU off.
449	 */
450	ldr	x1, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
451	sub	x0, x0, x1
452	bl	thread_spmc_register_secondary_ep
453	b	thread_ffa_msg_wait
454#else
455	/*
456	 * Pass the vector address returned from main_init Compensate for
457	 * the virtual map offset since cpu_on_handler() is called with MMU
458	 * off.
459	 */
460	ldr	x0, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
461	adr	x1, thread_vector_table
462	sub	x1, x1, x0
463	mov	x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE
464	smc	#0
465	/* SMC should not return */
466	panic_at_smc_return
467#endif
468END_FUNC _start
469DECLARE_KEEP_INIT _start
470
471	.section .identity_map.data
472	.balign	8
473LOCAL_DATA cached_mem_end , :
474	.skip	8
475END_DATA cached_mem_end
476
477#if defined(CFG_CORE_ASLR) || defined(CFG_CORE_PHYS_RELOCATABLE)
478LOCAL_FUNC relocate , :
479	/*
480	 * x0 holds relocate offset
481	 * x1 holds load address
482	 */
483#ifdef CFG_WITH_PAGER
484	adr_l	x6, __init_end
485#else
486	adr_l	x6, __end
487#endif
488	ldp	w2, w3, [x6, #BOOT_EMBDATA_RELOC_OFFSET]
489
490	add	x2, x2, x6	/* start of relocations */
491	add	x3, x3, x2	/* end of relocations */
492
493	/*
494	 * Relocations are not formatted as Rela64, instead they are in a
495	 * compressed format created by get_reloc_bin() in
496	 * scripts/gen_tee_bin.py
497	 *
498	 * All the R_AARCH64_RELATIVE relocations are translated into a
499	 * list of 32-bit offsets from TEE_LOAD_ADDR. At each address a
500	 * 64-bit value pointed out which increased with the load offset.
501	 */
502
503#ifdef CFG_WITH_PAGER
504	/*
505	 * With pager enabled we can only relocate the pager and init
506	 * parts, the rest has to be done when a page is populated.
507	 */
508	sub	x6, x6, x1
509#endif
510
511	b	2f
512	/* Loop over the relocation addresses and process all entries */
5131:	ldr	w4, [x2], #4
514#ifdef CFG_WITH_PAGER
515	/* Skip too large addresses */
516	cmp	x4, x6
517	b.ge	2f
518#endif
519	add	x4, x4, x1
520	ldr	x5, [x4]
521	add	x5, x5, x0
522	str	x5, [x4]
523
5242:	cmp	x2, x3
525	b.ne	1b
526
527	ret
528END_FUNC relocate
529#endif
530
531/*
532 * void enable_mmu(unsigned long core_pos);
533 *
534 * This function depends on being mapped with in the identity map where
535 * physical address and virtual address is the same. After MMU has been
536 * enabled the instruction pointer will be updated to execute as the new
537 * offset instead. Stack pointers and the return address are updated.
538 */
539LOCAL_FUNC enable_mmu , : , .identity_map
540	adr	x1, boot_mmu_config
541	load_xregs x1, 0, 2, 6
542	/*
543	 * x0 = core_pos
544	 * x2 = tcr_el1
545	 * x3 = mair_el1
546	 * x4 = ttbr0_el1_base
547	 * x5 = ttbr0_core_offset
548	 * x6 = load_offset
549	 */
550	msr	tcr_el1, x2
551	msr	mair_el1, x3
552
553	/*
554	 * ttbr0_el1 = ttbr0_el1_base + ttbr0_core_offset * core_pos
555	 */
556	madd	x1, x5, x0, x4
557	msr	ttbr0_el1, x1
558	msr	ttbr1_el1, xzr
559	isb
560
561	/* Invalidate TLB */
562	tlbi	vmalle1
563
564	/*
565	 * Make sure translation table writes have drained into memory and
566	 * the TLB invalidation is complete.
567	 */
568	dsb	sy
569	isb
570
571	/* Enable the MMU */
572	mrs	x1, sctlr_el1
573	orr	x1, x1, #SCTLR_M
574	msr	sctlr_el1, x1
575	isb
576
577	/* Update vbar */
578	mrs	x1, vbar_el1
579	add	x1, x1, x6
580	msr	vbar_el1, x1
581	isb
582
583	/* Invalidate instruction cache and branch predictor */
584	ic	iallu
585	isb
586
587	/* Enable I and D cache */
588	mrs	x1, sctlr_el1
589	orr	x1, x1, #SCTLR_I
590	orr	x1, x1, #SCTLR_C
591	msr	sctlr_el1, x1
592	isb
593
594	/* Adjust stack pointers and return address */
595	msr	spsel, #1
596	add	sp, sp, x6
597	msr	spsel, #0
598	add	sp, sp, x6
599	add	x30, x30, x6
600
601	ret
602END_FUNC enable_mmu
603
604	.section .identity_map.data
605	.balign	8
606DATA boot_mmu_config , : /* struct core_mmu_config */
607	.skip	CORE_MMU_CONFIG_SIZE
608END_DATA boot_mmu_config
609
610FUNC cpu_on_handler , :
611	mov	x19, x0
612	mov	x20, x1
613	mov	x21, x30
614
615	adr	x0, reset_vect_table
616	msr	vbar_el1, x0
617	isb
618
619	set_sctlr_el1
620	isb
621
622#ifdef CFG_PAN
623	init_pan
624#endif
625
626	/* Enable aborts now that we can receive exceptions */
627	msr	daifclr, #DAIFBIT_ABT
628
629	bl	__get_core_pos
630	bl	enable_mmu
631
632	/* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */
633	set_sp
634
635#ifdef CFG_MEMTAG
636	init_memtag_per_cpu
637#endif
638#ifdef CFG_CORE_PAUTH
639	init_pauth_secondary_cpu
640#endif
641
642	mov	x0, x19
643	mov	x1, x20
644#ifdef CFG_CORE_FFA
645	bl	boot_cpu_on_handler
646	b	thread_ffa_msg_wait
647#else
648	mov	x30, x21
649	b	boot_cpu_on_handler
650#endif
651END_FUNC cpu_on_handler
652DECLARE_KEEP_PAGER cpu_on_handler
653
654LOCAL_FUNC unhandled_cpu , :
655	wfi
656	b	unhandled_cpu
657END_FUNC unhandled_cpu
658
659LOCAL_DATA stack_tmp_rel , :
660	.word	stack_tmp - stack_tmp_rel - STACK_TMP_GUARD
661END_DATA stack_tmp_rel
662
663	/*
664	 * This macro verifies that the a given vector doesn't exceed the
665	 * architectural limit of 32 instructions. This is meant to be placed
666	 * immedately after the last instruction in the vector. It takes the
667	 * vector entry as the parameter
668	 */
669	.macro check_vector_size since
670	  .if (. - \since) > (32 * 4)
671	    .error "Vector exceeds 32 instructions"
672	  .endif
673	.endm
674
675	.section .identity_map, "ax", %progbits
676	.align	11
677LOCAL_FUNC reset_vect_table , :, .identity_map, , nobti
678	/* -----------------------------------------------------
679	 * Current EL with SP0 : 0x0 - 0x180
680	 * -----------------------------------------------------
681	 */
682SynchronousExceptionSP0:
683	b	SynchronousExceptionSP0
684	check_vector_size SynchronousExceptionSP0
685
686	.align	7
687IrqSP0:
688	b	IrqSP0
689	check_vector_size IrqSP0
690
691	.align	7
692FiqSP0:
693	b	FiqSP0
694	check_vector_size FiqSP0
695
696	.align	7
697SErrorSP0:
698	b	SErrorSP0
699	check_vector_size SErrorSP0
700
701	/* -----------------------------------------------------
702	 * Current EL with SPx: 0x200 - 0x380
703	 * -----------------------------------------------------
704	 */
705	.align	7
706SynchronousExceptionSPx:
707	b	SynchronousExceptionSPx
708	check_vector_size SynchronousExceptionSPx
709
710	.align	7
711IrqSPx:
712	b	IrqSPx
713	check_vector_size IrqSPx
714
715	.align	7
716FiqSPx:
717	b	FiqSPx
718	check_vector_size FiqSPx
719
720	.align	7
721SErrorSPx:
722	b	SErrorSPx
723	check_vector_size SErrorSPx
724
725	/* -----------------------------------------------------
726	 * Lower EL using AArch64 : 0x400 - 0x580
727	 * -----------------------------------------------------
728	 */
729	.align	7
730SynchronousExceptionA64:
731	b	SynchronousExceptionA64
732	check_vector_size SynchronousExceptionA64
733
734	.align	7
735IrqA64:
736	b	IrqA64
737	check_vector_size IrqA64
738
739	.align	7
740FiqA64:
741	b	FiqA64
742	check_vector_size FiqA64
743
744	.align	7
745SErrorA64:
746	b   	SErrorA64
747	check_vector_size SErrorA64
748
749	/* -----------------------------------------------------
750	 * Lower EL using AArch32 : 0x0 - 0x180
751	 * -----------------------------------------------------
752	 */
753	.align	7
754SynchronousExceptionA32:
755	b	SynchronousExceptionA32
756	check_vector_size SynchronousExceptionA32
757
758	.align	7
759IrqA32:
760	b	IrqA32
761	check_vector_size IrqA32
762
763	.align	7
764FiqA32:
765	b	FiqA32
766	check_vector_size FiqA32
767
768	.align	7
769SErrorA32:
770	b	SErrorA32
771	check_vector_size SErrorA32
772
773END_FUNC reset_vect_table
774
775BTI(emit_aarch64_feature_1_and     GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
776