1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, Linaro Limited 4 * Copyright (c) 2021, Arm Limited 5 */ 6 7#include <arm32_macros.S> 8#include <arm.h> 9#include <asm.S> 10#include <generated/asm-defines.h> 11#include <keep.h> 12#include <kernel/asan.h> 13#include <kernel/cache_helpers.h> 14#include <kernel/thread_private.h> 15#include <platform_config.h> 16#include <sm/optee_smc.h> 17#include <sm/teesmc_opteed.h> 18#include <sm/teesmc_opteed_macros.h> 19 20.arch_extension sec 21 22.section .data 23.balign 4 24 25#ifdef CFG_BOOT_SYNC_CPU 26.equ SEM_CPU_READY, 1 27#endif 28 29#ifdef CFG_PL310 30.section .rodata.init 31panic_boot_file: 32 .asciz __FILE__ 33 34/* 35 * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) 36 */ 37LOCAL_FUNC __assert_flat_mapped_range , : 38UNWIND( .cantunwind) 39 push { r4-r6, lr } 40 mov r4, r0 41 mov r5, r1 42 bl cpu_mmu_enabled 43 cmp r0, #0 44 beq 1f 45 mov r0, r4 46 bl virt_to_phys 47 cmp r0, r4 48 beq 1f 49 /* 50 * this must be compliant with the panic generic routine: 51 * __do_panic(__FILE__, __LINE__, __func__, str) 52 */ 53 ldr r0, =panic_boot_file 54 mov r1, r5 55 mov r2, #0 56 mov r3, #0 57 bl __do_panic 58 b . /* should NOT return */ 591: pop { r4-r6, pc } 60END_FUNC __assert_flat_mapped_range 61 62 /* panic if mmu is enable and vaddr != paddr (scratch lr) */ 63 .macro assert_flat_mapped_range va, line 64 ldr r0, \va 65 ldr r1, =\line 66 bl __assert_flat_mapped_range 67 .endm 68#endif /* CFG_PL310 */ 69 70WEAK_FUNC plat_cpu_reset_early , : 71 bx lr 72END_FUNC plat_cpu_reset_early 73DECLARE_KEEP_PAGER plat_cpu_reset_early 74 75 .section .identity_map, "ax" 76 .align 5 77LOCAL_FUNC reset_vect_table , : , .identity_map 78 b . 79 b . /* Undef */ 80 b . /* Syscall */ 81 b . /* Prefetch abort */ 82 b . /* Data abort */ 83 b . /* Reserved */ 84 b . /* IRQ */ 85 b . /* FIQ */ 86END_FUNC reset_vect_table 87 88 .macro cpu_is_ready 89#ifdef CFG_BOOT_SYNC_CPU 90 bl __get_core_pos 91 lsl r0, r0, #2 92 ldr r1,=sem_cpu_sync 93 ldr r2, =SEM_CPU_READY 94 str r2, [r1, r0] 95 dsb 96 sev 97#endif 98 .endm 99 100 .macro wait_primary 101#ifdef CFG_BOOT_SYNC_CPU 102 ldr r0, =sem_cpu_sync 103 mov r2, #SEM_CPU_READY 104 sev 1051: 106 ldr r1, [r0] 107 cmp r1, r2 108 wfene 109 bne 1b 110#endif 111 .endm 112 113 .macro wait_secondary 114#ifdef CFG_BOOT_SYNC_CPU 115 ldr r0, =sem_cpu_sync 116 mov r3, #CFG_TEE_CORE_NB_CORE 117 mov r2, #SEM_CPU_READY 118 sev 1191: 120 subs r3, r3, #1 121 beq 3f 122 add r0, r0, #4 1232: 124 ldr r1, [r0] 125 cmp r1, r2 126 wfene 127 bne 2b 128 b 1b 1293: 130#endif 131 .endm 132 133 /* 134 * set_sctlr : Setup some core configuration in CP15 SCTLR 135 * 136 * Setup required by current implementation of the OP-TEE core: 137 * - Disable data and instruction cache. 138 * - MMU is expected off and exceptions trapped in ARM mode. 139 * - Enable or disable alignment checks upon platform configuration. 140 * - Optionally enable write-implies-execute-never. 141 * - Optionally enable round robin strategy for cache replacement. 142 * 143 * Clobbers r0. 144 */ 145 .macro set_sctlr 146 read_sctlr r0 147 bic r0, r0, #(SCTLR_M | SCTLR_C) 148 bic r0, r0, #SCTLR_I 149 bic r0, r0, #SCTLR_TE 150 orr r0, r0, #SCTLR_SPAN 151#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 152 orr r0, r0, #SCTLR_A 153#else 154 bic r0, r0, #SCTLR_A 155#endif 156#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC) 157 orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN) 158#endif 159#if defined(CFG_ENABLE_SCTLR_RR) 160 orr r0, r0, #SCTLR_RR 161#endif 162 write_sctlr r0 163 .endm 164 165#if defined(CFG_CORE_SEL1_SPMC) && defined(CFG_WITH_ARM_TRUSTED_FW) 166 /* 167 * With OP-TEE as SPMC at S-EL1 the SPMD (SPD_spmd) in TF-A passes 168 * the DTB in r0, pagable part in r1, and the rest of the registers 169 * are unused 170 * 171 * Save boot arguments passed 172 * entry r0, saved r6: device tree address 173 * entry r1, saved r4: pagestore 174 * saved r5, r7: Zero 175 */ 176 .macro bootargs_entry 177 mov r6, r0 178 mov r4, r1 179 mov r5, #0 180 mov r7, #0 181 .endm 182#else 183 /* 184 * Save boot arguments 185 * entry r0, saved r4: pagestore 186 * entry r1, saved r7: (ARMv7 standard bootarg #1) 187 * entry r2, saved r6: device tree address, (ARMv7 standard bootarg #2) 188 * entry lr, saved r5: non-secure entry address (ARMv7 bootarg #0) 189 */ 190 .macro bootargs_entry 191#if defined(CFG_NS_ENTRY_ADDR) 192 ldr r5, =CFG_NS_ENTRY_ADDR 193#else 194 mov r5, lr 195#endif 196#if defined(CFG_PAGEABLE_ADDR) 197 ldr r4, =CFG_PAGEABLE_ADDR 198#else 199 mov r4, r0 200#endif 201#if defined(CFG_DT_ADDR) 202 ldr r6, =CFG_DT_ADDR 203#else 204 mov r6, r2 205#endif 206 mov r7, r1 207 .endm 208#endif 209 210 .macro maybe_init_spectre_workaround 211#if !defined(CFG_WITH_ARM_TRUSTED_FW) && \ 212 (defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \ 213 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)) 214 read_midr r0 215 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH 216 cmp r1, #MIDR_IMPLEMENTER_ARM 217 bne 1f 218 ubfx r1, r0, #MIDR_PRIMARY_PART_NUM_SHIFT, \ 219 #MIDR_PRIMARY_PART_NUM_WIDTH 220 221 movw r2, #CORTEX_A8_PART_NUM 222 cmp r1, r2 223 moveq r2, #ACTLR_CA8_ENABLE_INVALIDATE_BTB 224 beq 2f 225 226 movw r2, #CORTEX_A15_PART_NUM 227 cmp r1, r2 228 moveq r2, #ACTLR_CA15_ENABLE_INVALIDATE_BTB 229 bne 1f /* Skip it for all other CPUs */ 2302: 231 read_actlr r0 232 orr r0, r0, r2 233 write_actlr r0 234 isb 2351: 236#endif 237 .endm 238 239FUNC _start , : 240UNWIND( .cantunwind) 241 242 bootargs_entry 243 244 /* 245 * 32bit entry is expected to execute Supervisor mode, 246 * some bootloader may enter in Supervisor or Monitor 247 */ 248 cps #CPSR_MODE_SVC 249 250 /* Early ARM secure MP specific configuration */ 251 bl plat_cpu_reset_early 252 maybe_init_spectre_workaround 253 254 set_sctlr 255 isb 256 257 ldr r0, =reset_vect_table 258 write_vbar r0 259 260#if defined(CFG_WITH_ARM_TRUSTED_FW) 261 b reset_primary 262#else 263 bl __get_core_pos 264 cmp r0, #0 265 beq reset_primary 266 b reset_secondary 267#endif 268END_FUNC _start 269DECLARE_KEEP_INIT _start 270 271 /* 272 * Setup sp to point to the top of the tmp stack for the current CPU: 273 * sp is assigned stack_tmp_export + cpu_id * stack_tmp_stride 274 */ 275 .macro set_sp 276 bl __get_core_pos 277 cmp r0, #CFG_TEE_CORE_NB_CORE 278 /* Unsupported CPU, park it before it breaks something */ 279 bge unhandled_cpu 280 281 /* 282 * stack_tmp_stride and stack_tmp_stride_rel are the 283 * equivalent of: 284 * extern const u32 stack_tmp_stride; 285 * u32 stack_tmp_stride_rel = (u32)&stack_tmp_stride - 286 * (u32)&stack_tmp_stride_rel 287 * 288 * To load the value of stack_tmp_stride we do the equivalent 289 * of: 290 * *(u32 *)(stack_tmp_stride + (u32)&stack_tmp_stride_rel) 291 */ 292 adr r3, stack_tmp_stride_rel 293 ldr r1, [r3] 294 ldr r1, [r1, r3] 295 296 /* Same pattern as for stack_tmp_stride above */ 297 adr r3, stack_tmp_export_rel 298 ldr r2, [r3] 299 ldr r2, [r2, r3] 300 301 /* 302 * r0 is core pos 303 * r1 is value of stack_tmp_stride 304 * r2 is value of stack_tmp_export 305 */ 306 mul r1, r0, r1 307 add sp, r1, r2 308 .endm 309 310 /* 311 * Cache maintenance during entry: handle outer cache. 312 * End address is exclusive: first byte not to be changed. 313 * Note however arm_clX_inv/cleanbyva operate on full cache lines. 314 * 315 * Use ANSI #define to trap source file line number for PL310 assertion 316 */ 317 .macro __inval_cache_vrange vbase, vend, line 318#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 319 assert_flat_mapped_range (\vbase), (\line) 320 bl pl310_base 321 ldr r1, \vbase 322 ldr r2, \vend 323 bl arm_cl2_invbypa 324#endif 325 ldr r0, \vbase 326 ldr r1, \vend 327 sub r1, r1, r0 328 bl dcache_inv_range 329 .endm 330 331 .macro __flush_cache_vrange vbase, vend, line 332#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 333 assert_flat_mapped_range (\vbase), (\line) 334 ldr r0, \vbase 335 ldr r1, \vend 336 sub r1, r1, r0 337 bl dcache_clean_range 338 bl pl310_base 339 ldr r1, \vbase 340 ldr r2, \vend 341 bl arm_cl2_cleaninvbypa 342#endif 343 ldr r0, \vbase 344 ldr r1, \vend 345 sub r1, r1, r0 346 bl dcache_cleaninv_range 347 .endm 348 349#define inval_cache_vrange(vbase, vend) \ 350 __inval_cache_vrange vbase, vend, __LINE__ 351 352#define flush_cache_vrange(vbase, vend) \ 353 __flush_cache_vrange vbase, vend, __LINE__ 354 355#ifdef CFG_BOOT_SYNC_CPU 356#define flush_cpu_semaphores \ 357 flush_cache_vrange(sem_cpu_sync_start, sem_cpu_sync_end) 358#else 359#define flush_cpu_semaphores 360#endif 361 362LOCAL_FUNC reset_primary , : , .identity_map 363UNWIND( .cantunwind) 364 365 /* preserve r4-r7: bootargs */ 366 367#ifdef CFG_WITH_PAGER 368 /* 369 * Move init code into correct location and move hashes to a 370 * temporary safe location until the heap is initialized. 371 * 372 * The binary is built as: 373 * [Pager code, rodata and data] : In correct location 374 * [Init code and rodata] : Should be copied to __init_start 375 * [struct boot_embdata + data] : Should be saved before 376 * initializing pager, first uint32_t tells the length of the data 377 */ 378 ldr r0, =__init_start /* dst */ 379 ldr r1, =__data_end /* src */ 380 ldr r2, =__init_end 381 sub r2, r2, r0 /* init len */ 382 ldr r12, [r1, r2] /* length of hashes etc */ 383 add r2, r2, r12 /* length of init and hashes etc */ 384 /* Copy backwards (as memmove) in case we're overlapping */ 385 add r0, r0, r2 /* __init_start + len */ 386 add r1, r1, r2 /* __data_end + len */ 387 str r0, cached_mem_end 388 ldr r2, =__init_start 389copy_init: 390 ldmdb r1!, {r3, r8-r12} 391 stmdb r0!, {r3, r8-r12} 392 cmp r0, r2 393 bgt copy_init 394#else 395 /* 396 * The binary is built as: 397 * [Core, rodata and data] : In correct location 398 * [struct boot_embdata + data] : Should be moved to __end, first 399 * uint32_t tells the length of the struct + data 400 */ 401 ldr r0, =__end /* dst */ 402 ldr r1, =__data_end /* src */ 403 ldr r2, [r1] /* struct boot_embdata::total_len */ 404 /* Copy backwards (as memmove) in case we're overlapping */ 405 add r0, r0, r2 406 add r1, r1, r2 407 str r0, cached_mem_end 408 ldr r2, =__end 409 410copy_init: 411 ldmdb r1!, {r3, r8-r12} 412 stmdb r0!, {r3, r8-r12} 413 cmp r0, r2 414 bgt copy_init 415#endif 416 417 /* 418 * Clear .bss, this code obviously depends on the linker keeping 419 * start/end of .bss at least 8 byte aligned. 420 */ 421 ldr r0, =__bss_start 422 ldr r1, =__bss_end 423 mov r2, #0 424 mov r3, #0 425clear_bss: 426 stmia r0!, {r2, r3} 427 cmp r0, r1 428 bls clear_bss 429 430#ifdef CFG_VIRTUALIZATION 431 /* 432 * Clear .nex_bss, this code obviously depends on the linker keeping 433 * start/end of .bss at least 8 byte aligned. 434 */ 435 ldr r0, =__nex_bss_start 436 ldr r1, =__nex_bss_end 437 mov r2, #0 438 mov r3, #0 439clear_nex_bss: 440 stmia r0!, {r2, r3} 441 cmp r0, r1 442 bls clear_nex_bss 443#endif 444 445#ifdef CFG_CORE_SANITIZE_KADDRESS 446 /* First initialize the entire shadow area with no access */ 447 ldr r0, =__asan_shadow_start /* start */ 448 ldr r1, =__asan_shadow_end /* limit */ 449 mov r2, #ASAN_DATA_RED_ZONE 450shadow_no_access: 451 str r2, [r0], #4 452 cmp r0, r1 453 bls shadow_no_access 454 455 /* Mark the entire stack area as OK */ 456 ldr r2, =CFG_ASAN_SHADOW_OFFSET 457 ldr r0, =__nozi_stack_start /* start */ 458 lsr r0, r0, #ASAN_BLOCK_SHIFT 459 add r0, r0, r2 460 ldr r1, =__nozi_stack_end /* limit */ 461 lsr r1, r1, #ASAN_BLOCK_SHIFT 462 add r1, r1, r2 463 mov r2, #0 464shadow_stack_access_ok: 465 strb r2, [r0], #1 466 cmp r0, r1 467 bls shadow_stack_access_ok 468#endif 469 470 set_sp 471 472 bl thread_init_thread_core_local 473 474 /* complete ARM secure MP common configuration */ 475 bl plat_primary_init_early 476 477 /* Enable Console */ 478 bl console_init 479 480#ifdef CFG_PL310 481 bl pl310_base 482 bl arm_cl2_config 483#endif 484 485 /* 486 * Invalidate dcache for all memory used during initialization to 487 * avoid nasty surprices when the cache is turned on. We must not 488 * invalidate memory not used by OP-TEE since we may invalidate 489 * entries used by for instance ARM Trusted Firmware. 490 */ 491 inval_cache_vrange(cached_mem_start, cached_mem_end) 492 493#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 494 /* Enable PL310 if not yet enabled */ 495 bl pl310_base 496 bl arm_cl2_enable 497#endif 498 499#ifdef CFG_CORE_ASLR 500 mov r0, r6 501 bl get_aslr_seed 502#else 503 mov r0, #0 504#endif 505 506 ldr r1, =boot_mmu_config 507 bl core_init_mmu_map 508 509#ifdef CFG_CORE_ASLR 510 /* 511 * Process relocation information for updating with the new offset. 512 * We're doing this now before MMU is enabled as some of the memory 513 * will become write protected. 514 */ 515 ldr r0, =boot_mmu_config 516 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 517 /* 518 * Update cached_mem_end address with load offset since it was 519 * calculated before relocation. 520 */ 521 ldr r2, cached_mem_end 522 add r2, r2, r0 523 str r2, cached_mem_end 524 525 bl relocate 526#endif 527 528 bl __get_core_pos 529 bl enable_mmu 530#ifdef CFG_CORE_ASLR 531 /* 532 * Reinitialize console, since register_serial_console() has 533 * previously registered a PA and with ASLR the VA is different 534 * from the PA. 535 */ 536 bl console_init 537#endif 538 539#ifdef CFG_VIRTUALIZATION 540 /* 541 * Initialize partition tables for each partition to 542 * default_partition which has been relocated now to a different VA 543 */ 544 bl core_mmu_set_default_prtn_tbl 545#endif 546 547 mov r0, r4 /* pageable part address */ 548 mov r1, r5 /* ns-entry address */ 549 bl boot_init_primary_early 550#ifndef CFG_VIRTUALIZATION 551 mov r9, sp 552 ldr r0, =threads 553 ldr r0, [r0, #THREAD_CTX_STACK_VA_END] 554 mov sp, r0 555 bl thread_get_core_local 556 mov r8, r0 557 mov r0, #0 558 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 559#endif 560 mov r0, r6 /* DT address */ 561 bl boot_init_primary_late 562#ifndef CFG_VIRTUALIZATION 563 mov r0, #THREAD_CLF_TMP 564 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 565 mov sp, r9 566#endif 567 568 /* 569 * In case we've touched memory that secondary CPUs will use before 570 * they have turned on their D-cache, clean and invalidate the 571 * D-cache before exiting to normal world. 572 */ 573 flush_cache_vrange(cached_mem_start, cached_mem_end) 574 575 /* release secondary boot cores and sync with them */ 576 cpu_is_ready 577 flush_cpu_semaphores 578 wait_secondary 579 580#ifdef CFG_PL310_LOCKED 581#ifdef CFG_PL310_SIP_PROTOCOL 582#error "CFG_PL310_LOCKED must not be defined when CFG_PL310_SIP_PROTOCOL=y" 583#endif 584 /* lock/invalidate all lines: pl310 behaves as if disable */ 585 bl pl310_base 586 bl arm_cl2_lockallways 587 bl pl310_base 588 bl arm_cl2_cleaninvbyway 589#endif 590 591 /* 592 * Clear current thread id now to allow the thread to be reused on 593 * next entry. Matches the thread_init_boot_thread() in 594 * boot.c. 595 */ 596#ifndef CFG_VIRTUALIZATION 597 bl thread_clr_boot_thread 598#endif 599 600#ifdef CFG_CORE_FFA 601 ldr r0, =cpu_on_handler 602 /* 603 * Compensate for the load offset since cpu_on_handler() is 604 * called with MMU off. 605 */ 606 ldr r1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 607 sub r0, r0, r1 608 bl thread_spmc_register_secondary_ep 609 b thread_ffa_msg_wait 610#else /* CFG_CORE_FFA */ 611 612#if defined(CFG_WITH_ARM_TRUSTED_FW) 613 ldr r0, =boot_mmu_config 614 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 615 ldr r1, =thread_vector_table 616 /* Pass the vector address returned from main_init */ 617 sub r1, r1, r0 618#else 619 /* realy standard bootarg #1 and #2 to non secure entry */ 620 mov r4, #0 621 mov r3, r6 /* std bootarg #2 for register R2 */ 622 mov r2, r7 /* std bootarg #1 for register R1 */ 623 mov r1, #0 624#endif /* CFG_WITH_ARM_TRUSTED_FW */ 625 626 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 627 smc #0 628 /* SMC should not return */ 629 panic_at_smc_return 630#endif /* CFG_CORE_FFA */ 631END_FUNC reset_primary 632 633#ifdef CFG_BOOT_SYNC_CPU 634LOCAL_DATA sem_cpu_sync_start , : 635 .word sem_cpu_sync 636END_DATA sem_cpu_sync_start 637 638LOCAL_DATA sem_cpu_sync_end , : 639 .word sem_cpu_sync + (CFG_TEE_CORE_NB_CORE << 2) 640END_DATA sem_cpu_sync_end 641#endif 642 643LOCAL_DATA cached_mem_start , : 644 .word __text_start 645END_DATA cached_mem_start 646 647LOCAL_DATA cached_mem_end , : 648 .skip 4 649END_DATA cached_mem_end 650 651LOCAL_FUNC unhandled_cpu , : 652 wfi 653 b unhandled_cpu 654END_FUNC unhandled_cpu 655 656#ifdef CFG_CORE_ASLR 657LOCAL_FUNC relocate , : 658 push {r4-r5} 659 /* r0 holds load offset */ 660#ifdef CFG_WITH_PAGER 661 ldr r12, =__init_end 662#else 663 ldr r12, =__end 664#endif 665 ldr r2, [r12, #BOOT_EMBDATA_RELOC_OFFSET] 666 ldr r3, [r12, #BOOT_EMBDATA_RELOC_LEN] 667 668 mov_imm r1, TEE_RAM_START 669 add r2, r2, r12 /* start of relocations */ 670 add r3, r3, r2 /* end of relocations */ 671 672 /* 673 * Relocations are not formatted as Rel32, instead they are in a 674 * compressed format created by get_reloc_bin() in 675 * scripts/gen_tee_bin.py 676 * 677 * All the R_ARM_RELATIVE relocations are translated into a list 678 * list of 32-bit offsets from TEE_RAM_START. At each address a 679 * 32-bit value pointed out which increased with the load offset. 680 */ 681 682#ifdef CFG_WITH_PAGER 683 /* 684 * With pager enabled we can only relocate the pager and init 685 * parts, the rest has to be done when a page is populated. 686 */ 687 sub r12, r12, r1 688#endif 689 690 b 2f 691 /* Loop over the relocation addresses and process all entries */ 6921: ldr r4, [r2], #4 693#ifdef CFG_WITH_PAGER 694 /* Skip too large addresses */ 695 cmp r4, r12 696 bge 2f 697#endif 698 ldr r5, [r4, r1] 699 add r5, r5, r0 700 str r5, [r4, r1] 701 7022: cmp r2, r3 703 bne 1b 704 705 pop {r4-r5} 706 bx lr 707END_FUNC relocate 708#endif 709 710/* 711 * void enable_mmu(unsigned long core_pos); 712 * 713 * This function depends on being mapped with in the identity map where 714 * physical address and virtual address is the same. After MMU has been 715 * enabled the instruction pointer will be updated to execute as the new 716 * offset instead. Stack pointers and the return address are updated. 717 */ 718LOCAL_FUNC enable_mmu , : , .identity_map 719 /* r0 = core pos */ 720 adr r1, boot_mmu_config 721 722#ifdef CFG_WITH_LPAE 723 ldm r1!, {r2, r3} 724 /* 725 * r2 = ttbcr 726 * r3 = mair0 727 */ 728 write_ttbcr r2 729 write_mair0 r3 730 731 ldm r1!, {r2, r3} 732 /* 733 * r2 = ttbr0_base 734 * r3 = ttbr0_core_offset 735 */ 736 737 /* 738 * ttbr0_el1 = ttbr0_base + ttbr0_core_offset * core_pos 739 */ 740 mla r12, r0, r3, r2 741 mov r0, #0 742 write_ttbr0_64bit r12, r0 743 write_ttbr1_64bit r0, r0 744#else 745 ldm r1!, {r2, r3} 746 /* 747 * r2 = prrr 748 * r3 = nmrr 749 */ 750 write_prrr r2 751 write_nmrr r3 752 753 ldm r1!, {r2, r3} 754 /* 755 * r2 = dacr 756 * r3 = ttbcr 757 */ 758 write_dacr r2 759 write_ttbcr r3 760 761 ldm r1!, {r2} 762 /* r2 = ttbr */ 763 write_ttbr0 r2 764 write_ttbr1 r2 765 766 mov r2, #0 767 write_contextidr r2 768#endif 769 ldm r1!, {r2} 770 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */ 771 isb 772 773 /* Invalidate TLB */ 774 write_tlbiall 775 776 /* 777 * Make sure translation table writes have drained into memory and 778 * the TLB invalidation is complete. 779 */ 780 dsb sy 781 isb 782 783 read_sctlr r0 784 orr r0, r0, #SCTLR_M 785#ifndef CFG_WITH_LPAE 786 /* Enable Access flag (simplified access permissions) and TEX remap */ 787 orr r0, r0, #(SCTLR_AFE | SCTLR_TRE) 788#endif 789 write_sctlr r0 790 isb 791 792 /* Update vbar */ 793 read_vbar r1 794 add r1, r1, r2 795 write_vbar r1 796 isb 797 798 /* Invalidate instruction cache and branch predictor */ 799 write_iciallu 800 write_bpiall 801 isb 802 803 read_sctlr r0 804 /* Enable I and D cache */ 805 orr r0, r0, #SCTLR_I 806 orr r0, r0, #SCTLR_C 807#if defined(CFG_ENABLE_SCTLR_Z) 808 /* 809 * This is only needed on ARMv7 architecture and hence conditionned 810 * by configuration directive CFG_ENABLE_SCTLR_Z. For recent 811 * architectures, the program flow prediction is automatically 812 * enabled upon MMU enablement. 813 */ 814 orr r0, r0, #SCTLR_Z 815#endif 816 write_sctlr r0 817 isb 818 819 /* Adjust stack pointer and return address */ 820 add sp, sp, r2 821 add lr, lr, r2 822 823 bx lr 824END_FUNC enable_mmu 825 826LOCAL_DATA stack_tmp_export_rel , : 827 .word stack_tmp_export - stack_tmp_export_rel 828END_DATA stack_tmp_export_rel 829 830LOCAL_DATA stack_tmp_stride_rel , : 831 .word stack_tmp_stride - stack_tmp_stride_rel 832END_DATA stack_tmp_stride_rel 833 834DATA boot_mmu_config , : /* struct core_mmu_config */ 835 .skip CORE_MMU_CONFIG_SIZE 836END_DATA boot_mmu_config 837 838#if defined(CFG_WITH_ARM_TRUSTED_FW) 839FUNC cpu_on_handler , : , .identity_map 840UNWIND( .cantunwind) 841 mov r4, r0 842 mov r5, r1 843 mov r6, lr 844 845 set_sctlr 846 isb 847 848 adr r0, reset_vect_table 849 write_vbar r0 850 851 mov r4, lr 852 853 bl __get_core_pos 854 bl enable_mmu 855 856 set_sp 857 858 mov r0, r4 859 mov r1, r5 860 bl boot_cpu_on_handler 861#ifdef CFG_CORE_FFA 862 b thread_ffa_msg_wait 863#else 864 bx r6 865#endif 866END_FUNC cpu_on_handler 867DECLARE_KEEP_PAGER cpu_on_handler 868 869#else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 870 871LOCAL_FUNC reset_secondary , : , .identity_map 872UNWIND( .cantunwind) 873 adr r0, reset_vect_table 874 write_vbar r0 875 876 wait_primary 877 878 set_sp 879#ifdef CFG_CORE_ASLR 880 /* 881 * stack_tmp_export which is used as base when initializing sp has 882 * been relocated to the new offset. Since MMU isn't enabled on 883 * this CPU yet we need to restore the corresponding physical 884 * address. 885 */ 886 adr r0, boot_mmu_config 887 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 888 sub sp, sp, r0 889#endif 890 891#if defined (CFG_BOOT_SECONDARY_REQUEST) 892 /* if L1 is not invalidated before, do it here */ 893 mov r0, #DCACHE_OP_INV 894 bl dcache_op_level1 895#endif 896 897 bl __get_core_pos 898 bl enable_mmu 899 900 cpu_is_ready 901 902#if defined (CFG_BOOT_SECONDARY_REQUEST) 903 /* 904 * boot_core_hpen() return value (r0) is address of 905 * ns entry context structure 906 */ 907 bl boot_core_hpen 908 ldm r0, {r0, r6} 909#else 910 mov r0, r5 /* ns-entry address */ 911 mov r6, #0 912#endif 913 bl boot_init_secondary 914 915 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 916 mov r1, r6 917 mov r2, #0 918 mov r3, #0 919 mov r4, #0 920 smc #0 921 /* SMC should not return */ 922 panic_at_smc_return 923END_FUNC reset_secondary 924DECLARE_KEEP_PAGER reset_secondary 925#endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 926