1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, Linaro Limited 4 */ 5 6#include <arm32_macros.S> 7#include <arm.h> 8#include <asm.S> 9#include <generated/asm-defines.h> 10#include <keep.h> 11#include <kernel/asan.h> 12#include <kernel/cache_helpers.h> 13#include <kernel/unwind.h> 14#include <platform_config.h> 15#include <sm/optee_smc.h> 16#include <sm/teesmc_opteed.h> 17#include <sm/teesmc_opteed_macros.h> 18 19.arch_extension sec 20 21.section .data 22.balign 4 23 24#ifdef CFG_BOOT_SYNC_CPU 25.equ SEM_CPU_READY, 1 26#endif 27 28#ifdef CFG_PL310 29.section .rodata.init 30panic_boot_file: 31 .asciz __FILE__ 32 33/* 34 * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) 35 */ 36LOCAL_FUNC __assert_flat_mapped_range , : 37UNWIND( .fnstart) 38UNWIND( .cantunwind) 39 push { r4-r6, lr } 40 mov r4, r0 41 mov r5, r1 42 bl cpu_mmu_enabled 43 cmp r0, #0 44 beq 1f 45 mov r0, r4 46 bl virt_to_phys 47 cmp r0, r4 48 beq 1f 49 /* 50 * this must be compliant with the panic generic routine: 51 * __do_panic(__FILE__, __LINE__, __func__, str) 52 */ 53 ldr r0, =panic_boot_file 54 mov r1, r5 55 mov r2, #0 56 mov r3, #0 57 bl __do_panic 58 b . /* should NOT return */ 591: pop { r4-r6, pc } 60UNWIND( .fnend) 61END_FUNC __assert_flat_mapped_range 62 63 /* panic if mmu is enable and vaddr != paddr (scratch lr) */ 64 .macro assert_flat_mapped_range va, line 65 ldr r0, \va 66 ldr r1, =\line 67 bl __assert_flat_mapped_range 68 .endm 69#endif /* CFG_PL310 */ 70 71FUNC plat_cpu_reset_early , : 72UNWIND( .fnstart) 73 bx lr 74UNWIND( .fnend) 75END_FUNC plat_cpu_reset_early 76DECLARE_KEEP_PAGER plat_cpu_reset_early 77.weak plat_cpu_reset_early 78 79 .section .identity_map, "ax" 80 .align 5 81LOCAL_FUNC reset_vect_table , : , .identity_map 82 b . 83 b . /* Undef */ 84 b . /* Syscall */ 85 b . /* Prefetch abort */ 86 b . /* Data abort */ 87 b . /* Reserved */ 88 b . /* IRQ */ 89 b . /* FIQ */ 90END_FUNC reset_vect_table 91 92 .macro cpu_is_ready 93#ifdef CFG_BOOT_SYNC_CPU 94 bl __get_core_pos 95 lsl r0, r0, #2 96 ldr r1,=sem_cpu_sync 97 ldr r2, =SEM_CPU_READY 98 str r2, [r1, r0] 99 dsb 100 sev 101#endif 102 .endm 103 104 .macro wait_primary 105#ifdef CFG_BOOT_SYNC_CPU 106 ldr r0, =sem_cpu_sync 107 mov r2, #SEM_CPU_READY 108 sev 1091: 110 ldr r1, [r0] 111 cmp r1, r2 112 wfene 113 bne 1b 114#endif 115 .endm 116 117 .macro wait_secondary 118#ifdef CFG_BOOT_SYNC_CPU 119 ldr r0, =sem_cpu_sync 120 mov r3, #CFG_TEE_CORE_NB_CORE 121 mov r2, #SEM_CPU_READY 122 sev 1231: 124 subs r3, r3, #1 125 beq 3f 126 add r0, r0, #4 1272: 128 ldr r1, [r0] 129 cmp r1, r2 130 wfene 131 bne 2b 132 b 1b 1333: 134#endif 135 .endm 136 137 /* 138 * set_sctlr : Setup some core configuration in CP15 SCTLR 139 * 140 * Setup required by current implementation of the OP-TEE core: 141 * - Disable data and instruction cache. 142 * - MMU is expected off and exceptions trapped in ARM mode. 143 * - Enable or disable alignment checks upon platform configuration. 144 * - Optionally enable write-implies-execute-never. 145 * - Optionally enable round robin strategy for cache replacement. 146 * 147 * Clobbers r0. 148 */ 149 .macro set_sctlr 150 read_sctlr r0 151 bic r0, r0, #(SCTLR_M | SCTLR_C) 152 bic r0, r0, #SCTLR_I 153 bic r0, r0, #SCTLR_TE 154 orr r0, r0, #SCTLR_SPAN 155#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 156 orr r0, r0, #SCTLR_A 157#else 158 bic r0, r0, #SCTLR_A 159#endif 160#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC) 161 orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN) 162#endif 163#if defined(CFG_ENABLE_SCTLR_RR) 164 orr r0, r0, #SCTLR_RR 165#endif 166 write_sctlr r0 167 .endm 168 169 /* 170 * Save boot arguments 171 * entry r0, saved r4: pagestore 172 * entry r1, saved r7: (ARMv7 standard bootarg #1) 173 * entry r2, saved r6: device tree address, (ARMv7 standard bootarg #2) 174 * entry lr, saved r5: non-secure entry address (ARMv7 bootarg #0) 175 */ 176 .macro bootargs_entry 177#if defined(CFG_NS_ENTRY_ADDR) 178 ldr r5, =CFG_NS_ENTRY_ADDR 179#else 180 mov r5, lr 181#endif 182#if defined(CFG_PAGEABLE_ADDR) 183 ldr r4, =CFG_PAGEABLE_ADDR 184#else 185 mov r4, r0 186#endif 187#if defined(CFG_DT_ADDR) 188 ldr r6, =CFG_DT_ADDR 189#else 190 mov r6, r2 191#endif 192 mov r7, r1 193 .endm 194 195 .macro maybe_init_spectre_workaround 196#if !defined(CFG_WITH_ARM_TRUSTED_FW) && \ 197 (defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \ 198 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)) 199 read_midr r0 200 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH 201 cmp r1, #MIDR_IMPLEMENTER_ARM 202 bne 1f 203 ubfx r1, r0, #MIDR_PRIMARY_PART_NUM_SHIFT, \ 204 #MIDR_PRIMARY_PART_NUM_WIDTH 205 206 movw r2, #CORTEX_A8_PART_NUM 207 cmp r1, r2 208 moveq r2, #ACTLR_CA8_ENABLE_INVALIDATE_BTB 209 beq 2f 210 211 movw r2, #CORTEX_A15_PART_NUM 212 cmp r1, r2 213 moveq r2, #ACTLR_CA15_ENABLE_INVALIDATE_BTB 214 bne 1f /* Skip it for all other CPUs */ 2152: 216 read_actlr r0 217 orr r0, r0, r2 218 write_actlr r0 219 isb 2201: 221#endif 222 .endm 223 224FUNC _start , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 228 bootargs_entry 229 230 /* 231 * 32bit entry is expected to execute Supervisor mode, 232 * some bootloader may enter in Supervisor or Monitor 233 */ 234 cps #CPSR_MODE_SVC 235 236 /* Early ARM secure MP specific configuration */ 237 bl plat_cpu_reset_early 238 maybe_init_spectre_workaround 239 240 set_sctlr 241 isb 242 243 ldr r0, =reset_vect_table 244 write_vbar r0 245 246#if defined(CFG_WITH_ARM_TRUSTED_FW) 247 b reset_primary 248#else 249 bl __get_core_pos 250 cmp r0, #0 251 beq reset_primary 252 b reset_secondary 253#endif 254UNWIND( .fnend) 255END_FUNC _start 256DECLARE_KEEP_INIT _start 257 258 /* 259 * Setup sp to point to the top of the tmp stack for the current CPU: 260 * sp is assigned stack_tmp_export + cpu_id * stack_tmp_stride 261 */ 262 .macro set_sp 263 bl __get_core_pos 264 cmp r0, #CFG_TEE_CORE_NB_CORE 265 /* Unsupported CPU, park it before it breaks something */ 266 bge unhandled_cpu 267 268 /* 269 * stack_tmp_stride and stack_tmp_stride_rel are the 270 * equivalent of: 271 * extern const u32 stack_tmp_stride; 272 * u32 stack_tmp_stride_rel = (u32)&stack_tmp_stride - 273 * (u32)&stack_tmp_stride_rel 274 * 275 * To load the value of stack_tmp_stride we do the equivalent 276 * of: 277 * *(u32 *)(stack_tmp_stride + (u32)&stack_tmp_stride_rel) 278 */ 279 adr r3, stack_tmp_stride_rel 280 ldr r1, [r3] 281 ldr r1, [r1, r3] 282 283 /* Same pattern as for stack_tmp_stride above */ 284 adr r3, stack_tmp_export_rel 285 ldr r2, [r3] 286 ldr r2, [r2, r3] 287 288 /* 289 * r0 is core pos 290 * r1 is value of stack_tmp_stride 291 * r2 is value of stack_tmp_export 292 */ 293 mul r1, r0, r1 294 add sp, r1, r2 295 .endm 296 297 /* 298 * Cache maintenance during entry: handle outer cache. 299 * End address is exclusive: first byte not to be changed. 300 * Note however arm_clX_inv/cleanbyva operate on full cache lines. 301 * 302 * Use ANSI #define to trap source file line number for PL310 assertion 303 */ 304 .macro __inval_cache_vrange vbase, vend, line 305#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 306 assert_flat_mapped_range (\vbase), (\line) 307 bl pl310_base 308 ldr r1, \vbase 309 ldr r2, \vend 310 bl arm_cl2_invbypa 311#endif 312 ldr r0, \vbase 313 ldr r1, \vend 314 sub r1, r1, r0 315 bl dcache_inv_range 316 .endm 317 318 .macro __flush_cache_vrange vbase, vend, line 319#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 320 assert_flat_mapped_range (\vbase), (\line) 321 ldr r0, \vbase 322 ldr r1, \vend 323 sub r1, r1, r0 324 bl dcache_clean_range 325 bl pl310_base 326 ldr r1, \vbase 327 ldr r2, \vend 328 bl arm_cl2_cleaninvbypa 329#endif 330 ldr r0, \vbase 331 ldr r1, \vend 332 sub r1, r1, r0 333 bl dcache_cleaninv_range 334 .endm 335 336#define inval_cache_vrange(vbase, vend) \ 337 __inval_cache_vrange vbase, vend, __LINE__ 338 339#define flush_cache_vrange(vbase, vend) \ 340 __flush_cache_vrange vbase, vend, __LINE__ 341 342#ifdef CFG_BOOT_SYNC_CPU 343#define flush_cpu_semaphores \ 344 flush_cache_vrange(sem_cpu_sync_start, sem_cpu_sync_end) 345#else 346#define flush_cpu_semaphores 347#endif 348 349LOCAL_FUNC reset_primary , : , .identity_map 350UNWIND( .fnstart) 351UNWIND( .cantunwind) 352 353 /* preserve r4-r7: bootargs */ 354 355#ifdef CFG_WITH_PAGER 356 /* 357 * Move init code into correct location and move hashes to a 358 * temporary safe location until the heap is initialized. 359 * 360 * The binary is built as: 361 * [Pager code, rodata and data] : In correct location 362 * [Init code and rodata] : Should be copied to __init_start 363 * [struct boot_embdata + data] : Should be saved before 364 * initializing pager, first uint32_t tells the length of the data 365 */ 366 ldr r0, =__init_start /* dst */ 367 ldr r1, =__data_end /* src */ 368 ldr r2, =__init_end 369 sub r2, r2, r0 /* init len */ 370 ldr r12, [r1, r2] /* length of hashes etc */ 371 add r2, r2, r12 /* length of init and hashes etc */ 372 /* Copy backwards (as memmove) in case we're overlapping */ 373 add r0, r0, r2 /* __init_start + len */ 374 add r1, r1, r2 /* __data_end + len */ 375 str r0, cached_mem_end 376 ldr r2, =__init_start 377copy_init: 378 ldmdb r1!, {r3, r8-r12} 379 stmdb r0!, {r3, r8-r12} 380 cmp r0, r2 381 bgt copy_init 382#else 383 /* 384 * The binary is built as: 385 * [Core, rodata and data] : In correct location 386 * [struct boot_embdata + data] : Should be moved to __end, first 387 * uint32_t tells the length of the struct + data 388 */ 389 ldr r0, =__end /* dst */ 390 ldr r1, =__data_end /* src */ 391 ldr r2, [r1] /* struct boot_embdata::total_len */ 392 /* Copy backwards (as memmove) in case we're overlapping */ 393 add r0, r0, r2 394 add r1, r1, r2 395 str r0, cached_mem_end 396 ldr r2, =__end 397 398copy_init: 399 ldmdb r1!, {r3, r8-r12} 400 stmdb r0!, {r3, r8-r12} 401 cmp r0, r2 402 bgt copy_init 403#endif 404 405 /* 406 * Clear .bss, this code obviously depends on the linker keeping 407 * start/end of .bss at least 8 byte aligned. 408 */ 409 ldr r0, =__bss_start 410 ldr r1, =__bss_end 411 mov r2, #0 412 mov r3, #0 413clear_bss: 414 stmia r0!, {r2, r3} 415 cmp r0, r1 416 bls clear_bss 417 418#ifdef CFG_VIRTUALIZATION 419 /* 420 * Clear .nex_bss, this code obviously depends on the linker keeping 421 * start/end of .bss at least 8 byte aligned. 422 */ 423 ldr r0, =__nex_bss_start 424 ldr r1, =__nex_bss_end 425 mov r2, #0 426 mov r3, #0 427clear_nex_bss: 428 stmia r0!, {r2, r3} 429 cmp r0, r1 430 bls clear_nex_bss 431#endif 432 433#ifdef CFG_CORE_SANITIZE_KADDRESS 434 /* First initialize the entire shadow area with no access */ 435 ldr r0, =__asan_shadow_start /* start */ 436 ldr r1, =__asan_shadow_end /* limit */ 437 mov r2, #ASAN_DATA_RED_ZONE 438shadow_no_access: 439 str r2, [r0], #4 440 cmp r0, r1 441 bls shadow_no_access 442 443 /* Mark the entire stack area as OK */ 444 ldr r2, =CFG_ASAN_SHADOW_OFFSET 445 ldr r0, =__nozi_stack_start /* start */ 446 lsr r0, r0, #ASAN_BLOCK_SHIFT 447 add r0, r0, r2 448 ldr r1, =__nozi_stack_end /* limit */ 449 lsr r1, r1, #ASAN_BLOCK_SHIFT 450 add r1, r1, r2 451 mov r2, #0 452shadow_stack_access_ok: 453 strb r2, [r0], #1 454 cmp r0, r1 455 bls shadow_stack_access_ok 456#endif 457 458 set_sp 459 460 bl thread_init_thread_core_local 461 462 /* complete ARM secure MP common configuration */ 463 bl plat_primary_init_early 464 465 /* Enable Console */ 466 bl console_init 467 468#ifdef CFG_PL310 469 bl pl310_base 470 bl arm_cl2_config 471#endif 472 473 /* 474 * Invalidate dcache for all memory used during initialization to 475 * avoid nasty surprices when the cache is turned on. We must not 476 * invalidate memory not used by OP-TEE since we may invalidate 477 * entries used by for instance ARM Trusted Firmware. 478 */ 479 inval_cache_vrange(cached_mem_start, cached_mem_end) 480 481#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 482 /* Enable PL310 if not yet enabled */ 483 bl pl310_base 484 bl arm_cl2_enable 485#endif 486 487#ifdef CFG_CORE_ASLR 488 mov r0, r6 489 bl get_aslr_seed 490#else 491 mov r0, #0 492#endif 493 494 ldr r1, =boot_mmu_config 495 bl core_init_mmu_map 496 497#ifdef CFG_CORE_ASLR 498 /* 499 * Process relocation information for updating with the new offset. 500 * We're doing this now before MMU is enabled as some of the memory 501 * will become write protected. 502 */ 503 ldr r0, =boot_mmu_config 504 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 505 /* 506 * Update cached_mem_end address with load offset since it was 507 * calculated before relocation. 508 */ 509 ldr r2, cached_mem_end 510 add r2, r2, r0 511 str r2, cached_mem_end 512 513 bl relocate 514#endif 515 516 bl __get_core_pos 517 bl enable_mmu 518#ifdef CFG_CORE_ASLR 519 /* 520 * Reinitialize console, since register_serial_console() has 521 * previously registered a PA and with ASLR the VA is different 522 * from the PA. 523 */ 524 bl console_init 525#endif 526 527 mov r0, r4 /* pageable part address */ 528 mov r1, r5 /* ns-entry address */ 529 mov r2, r6 /* DT address */ 530 bl boot_init_primary 531 532 /* 533 * In case we've touched memory that secondary CPUs will use before 534 * they have turned on their D-cache, clean and invalidate the 535 * D-cache before exiting to normal world. 536 */ 537 flush_cache_vrange(cached_mem_start, cached_mem_end) 538 539 /* release secondary boot cores and sync with them */ 540 cpu_is_ready 541 flush_cpu_semaphores 542 wait_secondary 543 544#ifdef CFG_PL310_LOCKED 545#ifdef CFG_PL310_SIP_PROTOCOL 546#error "CFG_PL310_LOCKED must not be defined when CFG_PL310_SIP_PROTOCOL=y" 547#endif 548 /* lock/invalidate all lines: pl310 behaves as if disable */ 549 bl pl310_base 550 bl arm_cl2_lockallways 551 bl pl310_base 552 bl arm_cl2_cleaninvbyway 553#endif 554 555 /* 556 * Clear current thread id now to allow the thread to be reused on 557 * next entry. Matches the thread_init_boot_thread() in 558 * boot.c. 559 */ 560 bl thread_clr_boot_thread 561 562#ifdef CFG_CORE_FFA 563 ldr r0, =cpu_on_handler 564 /* 565 * Compensate for the load offset since cpu_on_handler() is 566 * called with MMU off. 567 */ 568 ldr r1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 569 sub r0, r0, r1 570 bl ffa_secondary_cpu_boot_req 571 b thread_ffa_msg_wait 572#else /* CFG_CORE_FFA */ 573 574#if defined(CFG_WITH_ARM_TRUSTED_FW) 575 ldr r0, =boot_mmu_config 576 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 577 ldr r1, =thread_vector_table 578 /* Pass the vector address returned from main_init */ 579 sub r1, r1, r0 580#else 581 /* realy standard bootarg #1 and #2 to non secure entry */ 582 mov r4, #0 583 mov r3, r6 /* std bootarg #2 for register R2 */ 584 mov r2, r7 /* std bootarg #1 for register R1 */ 585 mov r1, #0 586#endif /* CFG_WITH_ARM_TRUSTED_FW */ 587 588 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 589 smc #0 590 b . /* SMC should not return */ 591#endif /* CFG_CORE_FFA */ 592UNWIND( .fnend) 593END_FUNC reset_primary 594 595#ifdef CFG_BOOT_SYNC_CPU 596LOCAL_DATA sem_cpu_sync_start , : 597 .word sem_cpu_sync 598END_DATA sem_cpu_sync_start 599 600LOCAL_DATA sem_cpu_sync_end , : 601 .word sem_cpu_sync + (CFG_TEE_CORE_NB_CORE << 2) 602END_DATA sem_cpu_sync_end 603#endif 604 605LOCAL_DATA cached_mem_start , : 606 .word __text_start 607END_DATA cached_mem_start 608 609LOCAL_DATA cached_mem_end , : 610 .skip 4 611END_DATA cached_mem_end 612 613LOCAL_FUNC unhandled_cpu , : 614UNWIND( .fnstart) 615 wfi 616 b unhandled_cpu 617UNWIND( .fnend) 618END_FUNC unhandled_cpu 619 620#ifdef CFG_CORE_ASLR 621LOCAL_FUNC relocate , : 622 push {r4-r5} 623 /* r0 holds load offset */ 624#ifdef CFG_WITH_PAGER 625 ldr r12, =__init_end 626#else 627 ldr r12, =__end 628#endif 629 ldr r2, [r12, #BOOT_EMBDATA_RELOC_OFFSET] 630 ldr r3, [r12, #BOOT_EMBDATA_RELOC_LEN] 631 632 mov_imm r1, TEE_RAM_START 633 add r2, r2, r12 /* start of relocations */ 634 add r3, r3, r2 /* end of relocations */ 635 636 /* 637 * Relocations are not formatted as Rel32, instead they are in a 638 * compressed format created by get_reloc_bin() in 639 * scripts/gen_tee_bin.py 640 * 641 * All the R_ARM_RELATIVE relocations are translated into a list 642 * list of 32-bit offsets from TEE_RAM_START. At each address a 643 * 32-bit value pointed out which increased with the load offset. 644 */ 645 646#ifdef CFG_WITH_PAGER 647 /* 648 * With pager enabled we can only relocate the pager and init 649 * parts, the rest has to be done when a page is populated. 650 */ 651 sub r12, r12, r1 652#endif 653 654 b 2f 655 /* Loop over the relocation addresses and process all entries */ 6561: ldr r4, [r2], #4 657#ifdef CFG_WITH_PAGER 658 /* Skip too large addresses */ 659 cmp r4, r12 660 bge 2f 661#endif 662 ldr r5, [r4, r1] 663 add r5, r5, r0 664 str r5, [r4, r1] 665 6662: cmp r2, r3 667 bne 1b 668 669 pop {r4-r5} 670 bx lr 671END_FUNC relocate 672#endif 673 674/* 675 * void enable_mmu(unsigned long core_pos); 676 * 677 * This function depends on being mapped with in the identity map where 678 * physical address and virtual address is the same. After MMU has been 679 * enabled the instruction pointer will be updated to execute as the new 680 * offset instead. Stack pointers and the return address are updated. 681 */ 682LOCAL_FUNC enable_mmu , : , .identity_map 683 /* r0 = core pos */ 684 adr r1, boot_mmu_config 685 686#ifdef CFG_WITH_LPAE 687 ldm r1!, {r2, r3} 688 /* 689 * r2 = ttbcr 690 * r3 = mair0 691 */ 692 write_ttbcr r2 693 write_mair0 r3 694 695 ldm r1!, {r2, r3} 696 /* 697 * r2 = ttbr0_base 698 * r3 = ttbr0_core_offset 699 */ 700 701 /* 702 * ttbr0_el1 = ttbr0_base + ttbr0_core_offset * core_pos 703 */ 704 mla r12, r0, r3, r2 705 mov r0, #0 706 write_ttbr0_64bit r12, r0 707 write_ttbr1_64bit r0, r0 708#else 709 ldm r1!, {r2, r3} 710 /* 711 * r2 = prrr 712 * r3 = nmrr 713 */ 714 write_prrr r2 715 write_nmrr r3 716 717 ldm r1!, {r2, r3} 718 /* 719 * r2 = dacr 720 * r3 = ttbcr 721 */ 722 write_dacr r2 723 write_ttbcr r3 724 725 ldm r1!, {r2} 726 /* r2 = ttbr */ 727 write_ttbr0 r2 728 write_ttbr1 r2 729 730 mov r2, #0 731 write_contextidr r2 732#endif 733 ldm r1!, {r2} 734 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */ 735 isb 736 737 /* Invalidate TLB */ 738 write_tlbiall 739 740 /* 741 * Make sure translation table writes have drained into memory and 742 * the TLB invalidation is complete. 743 */ 744 dsb sy 745 isb 746 747 read_sctlr r0 748 orr r0, r0, #SCTLR_M 749#ifndef CFG_WITH_LPAE 750 /* Enable Access flag (simplified access permissions) and TEX remap */ 751 orr r0, r0, #(SCTLR_AFE | SCTLR_TRE) 752#endif 753 write_sctlr r0 754 isb 755 756 /* Update vbar */ 757 read_vbar r1 758 add r1, r1, r2 759 write_vbar r1 760 isb 761 762 /* Invalidate instruction cache and branch predictor */ 763 write_iciallu 764 write_bpiall 765 isb 766 767 read_sctlr r0 768 /* Enable I and D cache */ 769 orr r0, r0, #SCTLR_I 770 orr r0, r0, #SCTLR_C 771#if defined(CFG_ENABLE_SCTLR_Z) 772 /* 773 * This is only needed on ARMv7 architecture and hence conditionned 774 * by configuration directive CFG_ENABLE_SCTLR_Z. For recent 775 * architectures, the program flow prediction is automatically 776 * enabled upon MMU enablement. 777 */ 778 orr r0, r0, #SCTLR_Z 779#endif 780 write_sctlr r0 781 isb 782 783 /* Adjust stack pointer and return address */ 784 add sp, sp, r2 785 add lr, lr, r2 786 787 bx lr 788END_FUNC enable_mmu 789 790LOCAL_DATA stack_tmp_export_rel , : 791 .word stack_tmp_export - stack_tmp_export_rel 792END_DATA stack_tmp_export_rel 793 794LOCAL_DATA stack_tmp_stride_rel , : 795 .word stack_tmp_stride - stack_tmp_stride_rel 796END_DATA stack_tmp_stride_rel 797 798DATA boot_mmu_config , : /* struct core_mmu_config */ 799 .skip CORE_MMU_CONFIG_SIZE 800END_DATA boot_mmu_config 801 802#if defined(CFG_WITH_ARM_TRUSTED_FW) 803FUNC cpu_on_handler , : , .identity_map 804UNWIND( .fnstart) 805UNWIND( .cantunwind) 806 mov r4, r0 807 mov r5, r1 808 mov r6, lr 809 810 set_sctlr 811 isb 812 813 adr r0, reset_vect_table 814 write_vbar r0 815 816 mov r4, lr 817 818 bl __get_core_pos 819 bl enable_mmu 820 821 set_sp 822 823 mov r0, r4 824 mov r1, r5 825 bl boot_cpu_on_handler 826#ifdef CFG_CORE_FFA 827 b thread_ffa_msg_wait 828#else 829 bx r6 830#endif 831UNWIND( .fnend) 832END_FUNC cpu_on_handler 833DECLARE_KEEP_PAGER cpu_on_handler 834 835#else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 836 837LOCAL_FUNC reset_secondary , : , .identity_map 838UNWIND( .fnstart) 839UNWIND( .cantunwind) 840 adr r0, reset_vect_table 841 write_vbar r0 842 843 wait_primary 844 845 set_sp 846#ifdef CFG_CORE_ASLR 847 /* 848 * stack_tmp_export which is used as base when initializing sp has 849 * been relocated to the new offset. Since MMU isn't enabled on 850 * this CPU yet we need to restore the corresponding physical 851 * address. 852 */ 853 adr r0, boot_mmu_config 854 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 855 sub sp, sp, r0 856#endif 857 858#if defined (CFG_BOOT_SECONDARY_REQUEST) 859 /* if L1 is not invalidated before, do it here */ 860 mov r0, #DCACHE_OP_INV 861 bl dcache_op_level1 862#endif 863 864 bl __get_core_pos 865 bl enable_mmu 866 867 cpu_is_ready 868 869#if defined (CFG_BOOT_SECONDARY_REQUEST) 870 /* 871 * boot_core_hpen() return value (r0) is address of 872 * ns entry context structure 873 */ 874 bl boot_core_hpen 875 ldm r0, {r0, r6} 876#else 877 mov r0, r5 /* ns-entry address */ 878 mov r6, #0 879#endif 880 bl boot_init_secondary 881 882 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 883 mov r1, r6 884 mov r2, #0 885 mov r3, #0 886 mov r4, #0 887 smc #0 888 b . /* SMC should not return */ 889UNWIND( .fnend) 890END_FUNC reset_secondary 891DECLARE_KEEP_PAGER reset_secondary 892#endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 893