1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, Linaro Limited 4 * Copyright (c) 2021-2023, Arm Limited 5 */ 6 7#include <arm32_macros.S> 8#include <arm.h> 9#include <asm.S> 10#include <generated/asm-defines.h> 11#include <keep.h> 12#include <kernel/asan.h> 13#include <kernel/cache_helpers.h> 14#include <kernel/thread_private.h> 15#include <mm/core_mmu.h> 16#include <platform_config.h> 17#include <sm/optee_smc.h> 18#include <sm/teesmc_opteed.h> 19#include <sm/teesmc_opteed_macros.h> 20 21.arch_extension sec 22 23.section .data 24.balign 4 25 26#ifdef CFG_BOOT_SYNC_CPU 27.equ SEM_CPU_READY, 1 28#endif 29 30#ifdef CFG_PL310 31.section .rodata.init 32panic_boot_file: 33 .asciz __FILE__ 34 35/* 36 * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) 37 */ 38LOCAL_FUNC __assert_flat_mapped_range , : 39UNWIND( .cantunwind) 40 push { r4-r6, lr } 41 mov r4, r0 42 mov r5, r1 43 bl cpu_mmu_enabled 44 cmp r0, #0 45 beq 1f 46 mov r0, r4 47 bl virt_to_phys 48 cmp r0, r4 49 beq 1f 50 /* 51 * this must be compliant with the panic generic routine: 52 * __do_panic(__FILE__, __LINE__, __func__, str) 53 */ 54 ldr r0, =panic_boot_file 55 mov r1, r5 56 mov r2, #0 57 mov r3, #0 58 bl __do_panic 59 b . /* should NOT return */ 601: pop { r4-r6, pc } 61END_FUNC __assert_flat_mapped_range 62 63 /* panic if mmu is enable and vaddr != paddr (scratch lr) */ 64 .macro assert_flat_mapped_range va, line 65 ldr r0, \va 66 ldr r1, =\line 67 bl __assert_flat_mapped_range 68 .endm 69#endif /* CFG_PL310 */ 70 71WEAK_FUNC plat_cpu_reset_early , : 72 bx lr 73END_FUNC plat_cpu_reset_early 74DECLARE_KEEP_PAGER plat_cpu_reset_early 75 76 .section .identity_map, "ax" 77 .align 5 78LOCAL_FUNC reset_vect_table , : , .identity_map 79 b . 80 b . /* Undef */ 81 b . /* Syscall */ 82 b . /* Prefetch abort */ 83 b . /* Data abort */ 84 b . /* Reserved */ 85 b . /* IRQ */ 86 b . /* FIQ */ 87END_FUNC reset_vect_table 88 89 .macro cpu_is_ready 90#ifdef CFG_BOOT_SYNC_CPU 91 bl __get_core_pos 92 lsl r0, r0, #2 93 ldr r1,=sem_cpu_sync 94 ldr r2, =SEM_CPU_READY 95 str r2, [r1, r0] 96 dsb 97 sev 98#endif 99 .endm 100 101 .macro wait_primary 102#ifdef CFG_BOOT_SYNC_CPU 103 ldr r0, =sem_cpu_sync 104 mov r2, #SEM_CPU_READY 105 sev 1061: 107 ldr r1, [r0] 108 cmp r1, r2 109 wfene 110 bne 1b 111#endif 112 .endm 113 114 .macro wait_secondary 115#ifdef CFG_BOOT_SYNC_CPU 116 ldr r0, =sem_cpu_sync 117 mov r3, #CFG_TEE_CORE_NB_CORE 118 mov r2, #SEM_CPU_READY 119 sev 1201: 121 subs r3, r3, #1 122 beq 3f 123 add r0, r0, #4 1242: 125 ldr r1, [r0] 126 cmp r1, r2 127 wfene 128 bne 2b 129 b 1b 1303: 131#endif 132 .endm 133 134 /* 135 * set_sctlr : Setup some core configuration in CP15 SCTLR 136 * 137 * Setup required by current implementation of the OP-TEE core: 138 * - Disable data and instruction cache. 139 * - MMU is expected off and exceptions trapped in ARM mode. 140 * - Enable or disable alignment checks upon platform configuration. 141 * - Optionally enable write-implies-execute-never. 142 * - Optionally enable round robin strategy for cache replacement. 143 * 144 * Clobbers r0. 145 */ 146 .macro set_sctlr 147 read_sctlr r0 148 bic r0, r0, #(SCTLR_M | SCTLR_C) 149 bic r0, r0, #SCTLR_I 150 bic r0, r0, #SCTLR_TE 151 orr r0, r0, #SCTLR_SPAN 152#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 153 orr r0, r0, #SCTLR_A 154#else 155 bic r0, r0, #SCTLR_A 156#endif 157#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC) 158 orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN) 159#endif 160#if defined(CFG_ENABLE_SCTLR_RR) 161 orr r0, r0, #SCTLR_RR 162#endif 163 write_sctlr r0 164 .endm 165 166 .macro maybe_init_spectre_workaround 167#if !defined(CFG_WITH_ARM_TRUSTED_FW) && \ 168 (defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \ 169 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)) 170 read_midr r0 171 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH 172 cmp r1, #MIDR_IMPLEMENTER_ARM 173 bne 1f 174 ubfx r1, r0, #MIDR_PRIMARY_PART_NUM_SHIFT, \ 175 #MIDR_PRIMARY_PART_NUM_WIDTH 176 177 movw r2, #CORTEX_A8_PART_NUM 178 cmp r1, r2 179 moveq r2, #ACTLR_CA8_ENABLE_INVALIDATE_BTB 180 beq 2f 181 182 movw r2, #CORTEX_A15_PART_NUM 183 cmp r1, r2 184 moveq r2, #ACTLR_CA15_ENABLE_INVALIDATE_BTB 185 bne 1f /* Skip it for all other CPUs */ 1862: 187 read_actlr r0 188 orr r0, r0, r2 189 write_actlr r0 190 isb 1911: 192#endif 193 .endm 194 195FUNC _start , : 196UNWIND( .cantunwind) 197 /* 198 * Temporary copy of boot argument registers, will be passed to 199 * boot_save_args() further down. 200 */ 201 mov r4, r0 202 mov r5, r1 203 mov r6, r2 204 mov r7, r3 205 mov r8, lr 206 207 /* 208 * 32bit entry is expected to execute Supervisor mode, 209 * some bootloader may enter in Supervisor or Monitor 210 */ 211 cps #CPSR_MODE_SVC 212 213 /* Early ARM secure MP specific configuration */ 214 bl plat_cpu_reset_early 215 maybe_init_spectre_workaround 216 217 set_sctlr 218 isb 219 220 ldr r0, =reset_vect_table 221 write_vbar r0 222 223#if defined(CFG_WITH_ARM_TRUSTED_FW) 224 b reset_primary 225#else 226 bl __get_core_pos 227 cmp r0, #0 228 beq reset_primary 229 b reset_secondary 230#endif 231END_FUNC _start 232DECLARE_KEEP_INIT _start 233 234 /* 235 * Setup sp to point to the top of the tmp stack for the current CPU: 236 * sp is assigned: 237 * stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD 238 */ 239 .macro set_sp 240 bl __get_core_pos 241 cmp r0, #CFG_TEE_CORE_NB_CORE 242 /* Unsupported CPU, park it before it breaks something */ 243 bge unhandled_cpu 244 add r0, r0, #1 245 246 /* r2 = stack_tmp - STACK_TMP_GUARD */ 247 adr r3, stack_tmp_rel 248 ldr r2, [r3] 249 add r2, r2, r3 250 251 /* 252 * stack_tmp_stride and stack_tmp_stride_rel are the 253 * equivalent of: 254 * extern const u32 stack_tmp_stride; 255 * u32 stack_tmp_stride_rel = (u32)&stack_tmp_stride - 256 * (u32)&stack_tmp_stride_rel 257 * 258 * To load the value of stack_tmp_stride we do the equivalent 259 * of: 260 * *(u32 *)(stack_tmp_stride + (u32)&stack_tmp_stride_rel) 261 */ 262 adr r3, stack_tmp_stride_rel 263 ldr r1, [r3] 264 ldr r1, [r1, r3] 265 266 /* 267 * r0 is core pos + 1 268 * r1 is value of stack_tmp_stride 269 * r2 is value of stack_tmp + guard 270 */ 271 mul r1, r0, r1 272 add sp, r1, r2 273 .endm 274 275 /* 276 * Cache maintenance during entry: handle outer cache. 277 * End address is exclusive: first byte not to be changed. 278 * Note however arm_clX_inv/cleanbyva operate on full cache lines. 279 * 280 * Use ANSI #define to trap source file line number for PL310 assertion 281 */ 282 .macro __inval_cache_vrange vbase, vend, line 283#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 284 assert_flat_mapped_range (\vbase), (\line) 285 bl pl310_base 286 ldr r1, \vbase 287 ldr r2, =\vend 288 ldr r2, [r2] 289 bl arm_cl2_invbypa 290#endif 291 ldr r0, \vbase 292 ldr r1, =\vend 293 ldr r1, [r1] 294 sub r1, r1, r0 295 bl dcache_inv_range 296 .endm 297 298 .macro __flush_cache_vrange vbase, vend, line 299#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 300 assert_flat_mapped_range (\vbase), (\line) 301 ldr r0, \vbase 302 ldr r1, =\vend 303 ldr r1, [r1] 304 sub r1, r1, r0 305 bl dcache_clean_range 306 bl pl310_base 307 ldr r1, \vbase 308 ldr r2, =\vend 309 ldr r2, [r2] 310 bl arm_cl2_cleaninvbypa 311#endif 312 ldr r0, \vbase 313 ldr r1, =\vend 314 ldr r1, [r1] 315 sub r1, r1, r0 316 bl dcache_cleaninv_range 317 .endm 318 319#define inval_cache_vrange(vbase, vend) \ 320 __inval_cache_vrange vbase, vend, __LINE__ 321 322#define flush_cache_vrange(vbase, vend) \ 323 __flush_cache_vrange vbase, vend, __LINE__ 324 325#ifdef CFG_BOOT_SYNC_CPU 326#define flush_cpu_semaphores \ 327 flush_cache_vrange(sem_cpu_sync_start, sem_cpu_sync_end) 328#else 329#define flush_cpu_semaphores 330#endif 331 332LOCAL_FUNC reset_primary , : , .identity_map 333UNWIND( .cantunwind) 334 335 /* preserve r4-r8: bootargs */ 336 337#ifdef CFG_WITH_PAGER 338 /* 339 * Move init code into correct location and move hashes to a 340 * temporary safe location until the heap is initialized. 341 * 342 * The binary is built as: 343 * [Pager code, rodata and data] : In correct location 344 * [Init code and rodata] : Should be copied to __init_start 345 * [struct boot_embdata + data] : Should be saved before 346 * initializing pager, first uint32_t tells the length of the data 347 */ 348 ldr r0, =__init_start /* dst */ 349 ldr r1, =__data_end /* src */ 350 ldr r2, =__init_end 351 sub r2, r2, r0 /* init len */ 352 ldr r12, [r1, r2] /* length of hashes etc */ 353 add r2, r2, r12 /* length of init and hashes etc */ 354 /* Copy backwards (as memmove) in case we're overlapping */ 355 add r0, r0, r2 /* __init_start + len */ 356 add r1, r1, r2 /* __data_end + len */ 357 ldr r3, =boot_cached_mem_end 358 str r0, [r3] 359 ldr r2, =__init_start 360copy_init: 361 ldmdb r1!, {r3, r9-r12} 362 stmdb r0!, {r3, r9-r12} 363 cmp r0, r2 364 bgt copy_init 365#else 366 /* 367 * The binary is built as: 368 * [Core, rodata and data] : In correct location 369 * [struct boot_embdata + data] : Should be moved to __end, first 370 * uint32_t tells the length of the struct + data 371 */ 372 ldr r0, =__end /* dst */ 373 ldr r1, =__data_end /* src */ 374 ldr r2, [r1] /* struct boot_embdata::total_len */ 375 /* Copy backwards (as memmove) in case we're overlapping */ 376 add r0, r0, r2 377 add r1, r1, r2 378 ldr r3, =boot_cached_mem_end 379 str r2, [r3] 380 381copy_init: 382 ldmdb r1!, {r3, r9-r12} 383 stmdb r0!, {r3, r9-r12} 384 cmp r0, r2 385 bgt copy_init 386#endif 387 388 /* 389 * Clear .bss, this code obviously depends on the linker keeping 390 * start/end of .bss at least 8 byte aligned. 391 */ 392 ldr r0, =__bss_start 393 ldr r1, =__bss_end 394 mov r2, #0 395 mov r3, #0 396clear_bss: 397 stmia r0!, {r2, r3} 398 cmp r0, r1 399 bls clear_bss 400 401#ifdef CFG_NS_VIRTUALIZATION 402 /* 403 * Clear .nex_bss, this code obviously depends on the linker keeping 404 * start/end of .bss at least 8 byte aligned. 405 */ 406 ldr r0, =__nex_bss_start 407 ldr r1, =__nex_bss_end 408 mov r2, #0 409 mov r3, #0 410clear_nex_bss: 411 stmia r0!, {r2, r3} 412 cmp r0, r1 413 bls clear_nex_bss 414#endif 415 416#ifdef CFG_CORE_SANITIZE_KADDRESS 417 /* First initialize the entire shadow area with no access */ 418 ldr r0, =__asan_shadow_start /* start */ 419 ldr r1, =__asan_shadow_end /* limit */ 420 mov r2, #ASAN_DATA_RED_ZONE 421shadow_no_access: 422 str r2, [r0], #4 423 cmp r0, r1 424 bls shadow_no_access 425 426 /* Mark the entire stack area as OK */ 427 ldr r2, =CFG_ASAN_SHADOW_OFFSET 428 ldr r0, =__nozi_stack_start /* start */ 429 lsr r0, r0, #ASAN_BLOCK_SHIFT 430 add r0, r0, r2 431 ldr r1, =__nozi_stack_end /* limit */ 432 lsr r1, r1, #ASAN_BLOCK_SHIFT 433 add r1, r1, r2 434 mov r2, #0 435shadow_stack_access_ok: 436 strb r2, [r0], #1 437 cmp r0, r1 438 bls shadow_stack_access_ok 439#endif 440 441 set_sp 442 443 bl thread_init_thread_core_local 444 445 /* complete ARM secure MP common configuration */ 446 bl plat_primary_init_early 447 448 /* Enable Console */ 449 bl console_init 450 451 mov r0, r8 452 mov r1, #0 453 push {r0, r1} 454 mov r0, r4 455 mov r1, r5 456 mov r2, r6 457 mov r3, r7 458 bl boot_save_args 459 add sp, sp, #(2 * 4) 460 461#ifdef CFG_PL310 462 bl pl310_base 463 bl arm_cl2_config 464#endif 465 466 /* 467 * Invalidate dcache for all memory used during initialization to 468 * avoid nasty surprices when the cache is turned on. We must not 469 * invalidate memory not used by OP-TEE since we may invalidate 470 * entries used by for instance ARM Trusted Firmware. 471 */ 472 inval_cache_vrange(cached_mem_start, boot_cached_mem_end) 473 474#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 475 /* Enable PL310 if not yet enabled */ 476 bl pl310_base 477 bl arm_cl2_enable 478#endif 479 480#ifdef CFG_CORE_ASLR 481 bl get_aslr_seed 482#ifdef CFG_CORE_ASLR_SEED 483 mov_imm r0, CFG_CORE_ASLR_SEED 484#endif 485#else 486 mov r0, #0 487#endif 488 489 ldr r1, =boot_mmu_config 490 bl core_init_mmu_map 491 492#ifdef CFG_CORE_ASLR 493 /* 494 * Process relocation information for updating with the virtual map 495 * offset. We're doing this now before MMU is enabled as some of 496 * the memory will become write protected. 497 */ 498 ldr r0, =boot_mmu_config 499 ldr r0, [r0, #CORE_MMU_CONFIG_MAP_OFFSET] 500 /* 501 * Update boot_cached_mem_end address with load offset since it was 502 * calculated before relocation. 503 */ 504 ldr r3, =boot_cached_mem_end 505 ldr r2, [r3] 506 add r2, r2, r0 507 str r2, [r3] 508 509 bl relocate 510#endif 511 512 bl __get_core_pos 513 bl enable_mmu 514#ifdef CFG_CORE_ASLR 515 /* 516 * Reinitialize console, since register_serial_console() has 517 * previously registered a PA and with ASLR the VA is different 518 * from the PA. 519 */ 520 bl console_init 521#endif 522 523#ifdef CFG_NS_VIRTUALIZATION 524 /* 525 * Initialize partition tables for each partition to 526 * default_partition which has been relocated now to a different VA 527 */ 528 bl core_mmu_set_default_prtn_tbl 529#endif 530 531 bl boot_init_primary_early 532#ifndef CFG_NS_VIRTUALIZATION 533 mov r9, sp 534 ldr r0, =threads 535 ldr r0, [r0, #THREAD_CTX_STACK_VA_END] 536 mov sp, r0 537 bl thread_get_core_local 538 mov r8, r0 539 mov r0, #0 540 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 541#endif 542 bl boot_init_primary_late 543 bl boot_init_primary_final 544#ifndef CFG_NS_VIRTUALIZATION 545 mov r0, #THREAD_CLF_TMP 546 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 547 mov sp, r9 548#endif 549 550#ifdef _CFG_CORE_STACK_PROTECTOR 551 /* Update stack canary value */ 552 sub sp, sp, #0x8 553 mov r0, sp 554 mov r1, #1 555 mov r2, #0x4 556 bl plat_get_random_stack_canaries 557 ldr r0, [sp] 558 ldr r1, =__stack_chk_guard 559 str r0, [r1] 560 add sp, sp, #0x8 561#endif 562 563 /* 564 * In case we've touched memory that secondary CPUs will use before 565 * they have turned on their D-cache, clean and invalidate the 566 * D-cache before exiting to normal world. 567 */ 568 flush_cache_vrange(cached_mem_start, boot_cached_mem_end) 569 570 /* release secondary boot cores and sync with them */ 571 cpu_is_ready 572 flush_cpu_semaphores 573 wait_secondary 574 575#ifdef CFG_PL310_LOCKED 576#ifdef CFG_PL310_SIP_PROTOCOL 577#error "CFG_PL310_LOCKED must not be defined when CFG_PL310_SIP_PROTOCOL=y" 578#endif 579 /* lock/invalidate all lines: pl310 behaves as if disable */ 580 bl pl310_base 581 bl arm_cl2_lockallways 582 bl pl310_base 583 bl arm_cl2_cleaninvbyway 584#endif 585 586 /* 587 * Clear current thread id now to allow the thread to be reused on 588 * next entry. Matches the thread_init_boot_thread() in 589 * boot.c. 590 */ 591#ifndef CFG_NS_VIRTUALIZATION 592 bl thread_clr_boot_thread 593#endif 594 595#ifdef CFG_CORE_FFA 596 ldr r0, =cpu_on_handler 597 /* 598 * Compensate for the virtual map offset since cpu_on_handler() is 599 * called with MMU off. 600 */ 601 ldr r1, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET 602 sub r0, r0, r1 603 bl thread_spmc_register_secondary_ep 604 b thread_ffa_msg_wait 605#else /* CFG_CORE_FFA */ 606 607#if defined(CFG_WITH_ARM_TRUSTED_FW) 608 ldr r0, =boot_mmu_config 609 ldr r0, [r0, #CORE_MMU_CONFIG_MAP_OFFSET] 610 ldr r1, =thread_vector_table 611 /* Pass the vector address returned from main_init */ 612 sub r1, r1, r0 613#else 614 /* Relay standard bootarg #1 and #2 to non-secure entry */ 615 mov r4, #0 616 mov r3, r6 /* std bootarg #2 for register R2 */ 617 mov r2, r5 /* std bootarg #1 for register R1 */ 618 mov r1, #0 619#endif /* CFG_WITH_ARM_TRUSTED_FW */ 620 621 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 622 smc #0 623 /* SMC should not return */ 624 panic_at_smc_return 625#endif /* CFG_CORE_FFA */ 626END_FUNC reset_primary 627 628#ifdef CFG_BOOT_SYNC_CPU 629LOCAL_DATA sem_cpu_sync_start , : 630 .word sem_cpu_sync 631END_DATA sem_cpu_sync_start 632 633LOCAL_DATA sem_cpu_sync_end , : 634 .word sem_cpu_sync + (CFG_TEE_CORE_NB_CORE << 2) 635END_DATA sem_cpu_sync_end 636#endif 637 638LOCAL_DATA cached_mem_start , : 639 .word __text_start 640END_DATA cached_mem_start 641 642LOCAL_FUNC unhandled_cpu , : 643 wfi 644 b unhandled_cpu 645END_FUNC unhandled_cpu 646 647#ifdef CFG_CORE_ASLR 648LOCAL_FUNC relocate , : 649 push {r4-r5} 650 /* r0 holds load offset */ 651#ifdef CFG_WITH_PAGER 652 ldr r12, =__init_end 653#else 654 ldr r12, =__end 655#endif 656 ldr r2, [r12, #BOOT_EMBDATA_RELOC_OFFSET] 657 ldr r3, [r12, #BOOT_EMBDATA_RELOC_LEN] 658 659 mov_imm r1, TEE_LOAD_ADDR 660 add r2, r2, r12 /* start of relocations */ 661 add r3, r3, r2 /* end of relocations */ 662 663 /* 664 * Relocations are not formatted as Rel32, instead they are in a 665 * compressed format created by get_reloc_bin() in 666 * scripts/gen_tee_bin.py 667 * 668 * All the R_ARM_RELATIVE relocations are translated into a list of 669 * 32-bit offsets from TEE_LOAD_ADDR. At each address a 32-bit 670 * value pointed out which increased with the load offset. 671 */ 672 673#ifdef CFG_WITH_PAGER 674 /* 675 * With pager enabled we can only relocate the pager and init 676 * parts, the rest has to be done when a page is populated. 677 */ 678 sub r12, r12, r1 679#endif 680 681 b 2f 682 /* Loop over the relocation addresses and process all entries */ 6831: ldr r4, [r2], #4 684#ifdef CFG_WITH_PAGER 685 /* Skip too large addresses */ 686 cmp r4, r12 687 bge 2f 688#endif 689 ldr r5, [r4, r1] 690 add r5, r5, r0 691 str r5, [r4, r1] 692 6932: cmp r2, r3 694 bne 1b 695 696 pop {r4-r5} 697 bx lr 698END_FUNC relocate 699#endif 700 701/* 702 * void enable_mmu(unsigned long core_pos); 703 * 704 * This function depends on being mapped with in the identity map where 705 * physical address and virtual address is the same. After MMU has been 706 * enabled the instruction pointer will be updated to execute as the new 707 * offset instead. Stack pointers and the return address are updated. 708 */ 709LOCAL_FUNC enable_mmu , : , .identity_map 710 /* r0 = core pos */ 711 adr r1, boot_mmu_config 712 713#ifdef CFG_WITH_LPAE 714 ldm r1!, {r2, r3} 715 /* 716 * r2 = ttbcr 717 * r3 = mair0 718 */ 719 write_ttbcr r2 720 write_mair0 r3 721 722 ldm r1!, {r2, r3} 723 /* 724 * r2 = ttbr0_base 725 * r3 = ttbr0_core_offset 726 */ 727 728 /* 729 * ttbr0_el1 = ttbr0_base + ttbr0_core_offset * core_pos 730 */ 731 mla r12, r0, r3, r2 732 mov r0, #0 733 write_ttbr0_64bit r12, r0 734 write_ttbr1_64bit r0, r0 735#else 736 ldm r1!, {r2, r3} 737 /* 738 * r2 = prrr 739 * r3 = nmrr 740 */ 741 write_prrr r2 742 write_nmrr r3 743 744 ldm r1!, {r2, r3} 745 /* 746 * r2 = dacr 747 * r3 = ttbcr 748 */ 749 write_dacr r2 750 write_ttbcr r3 751 752 ldm r1!, {r2} 753 /* r2 = ttbr */ 754 write_ttbr0 r2 755 write_ttbr1 r2 756 757 mov r2, #0 758 write_contextidr r2 759#endif 760 ldm r1!, {r2} 761 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */ 762 isb 763 764 /* Invalidate TLB */ 765 write_tlbiall 766 767 /* 768 * Make sure translation table writes have drained into memory and 769 * the TLB invalidation is complete. 770 */ 771 dsb sy 772 isb 773 774 read_sctlr r0 775 orr r0, r0, #SCTLR_M 776#ifndef CFG_WITH_LPAE 777 /* Enable Access flag (simplified access permissions) and TEX remap */ 778 orr r0, r0, #(SCTLR_AFE | SCTLR_TRE) 779#endif 780 write_sctlr r0 781 isb 782 783 /* Update vbar */ 784 read_vbar r1 785 add r1, r1, r2 786 write_vbar r1 787 isb 788 789 /* Invalidate instruction cache and branch predictor */ 790 write_iciallu 791 write_bpiall 792 isb 793 794 read_sctlr r0 795 /* Enable I and D cache */ 796 orr r0, r0, #SCTLR_I 797 orr r0, r0, #SCTLR_C 798#if defined(CFG_ENABLE_SCTLR_Z) 799 /* 800 * This is only needed on ARMv7 architecture and hence conditionned 801 * by configuration directive CFG_ENABLE_SCTLR_Z. For recent 802 * architectures, the program flow prediction is automatically 803 * enabled upon MMU enablement. 804 */ 805 orr r0, r0, #SCTLR_Z 806#endif 807 write_sctlr r0 808 isb 809 810 /* Adjust stack pointer and return address */ 811 add sp, sp, r2 812 add lr, lr, r2 813 814 bx lr 815END_FUNC enable_mmu 816 817LOCAL_DATA stack_tmp_rel , : 818 .word stack_tmp - stack_tmp_rel - STACK_TMP_GUARD 819END_DATA stack_tmp_rel 820 821LOCAL_DATA stack_tmp_stride_rel , : 822 .word stack_tmp_stride - stack_tmp_stride_rel 823END_DATA stack_tmp_stride_rel 824 825DATA boot_mmu_config , : /* struct core_mmu_config */ 826 .skip CORE_MMU_CONFIG_SIZE 827END_DATA boot_mmu_config 828 829#if defined(CFG_WITH_ARM_TRUSTED_FW) 830FUNC cpu_on_handler , : , .identity_map 831UNWIND( .cantunwind) 832 mov r4, r0 833 mov r5, r1 834 mov r6, lr 835 836 set_sctlr 837 isb 838 839 adr r0, reset_vect_table 840 write_vbar r0 841 842 mov r4, lr 843 844 bl __get_core_pos 845 bl enable_mmu 846 847 set_sp 848 849 mov r0, r4 850 mov r1, r5 851 bl boot_cpu_on_handler 852#ifdef CFG_CORE_FFA 853 b thread_ffa_msg_wait 854#else 855 bx r6 856#endif 857END_FUNC cpu_on_handler 858DECLARE_KEEP_PAGER cpu_on_handler 859 860#else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 861 862LOCAL_FUNC reset_secondary , : , .identity_map 863UNWIND( .cantunwind) 864 adr r0, reset_vect_table 865 write_vbar r0 866 867 wait_primary 868 869 set_sp 870 871#if defined (CFG_BOOT_SECONDARY_REQUEST) 872 /* if L1 is not invalidated before, do it here */ 873 mov r0, #DCACHE_OP_INV 874 bl dcache_op_level1 875#endif 876 877 bl __get_core_pos 878 bl enable_mmu 879 880 cpu_is_ready 881 882#if defined (CFG_BOOT_SECONDARY_REQUEST) 883 /* 884 * boot_core_hpen() return value (r0) is address of 885 * ns entry context structure 886 */ 887 bl boot_core_hpen 888 ldm r0, {r0, r6} 889#else 890 mov r0, r8 /* ns-entry address */ 891 mov r6, #0 892#endif 893 bl boot_init_secondary 894 895 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 896 mov r1, r6 897 mov r2, #0 898 mov r3, #0 899 mov r4, #0 900 smc #0 901 /* SMC should not return */ 902 panic_at_smc_return 903END_FUNC reset_secondary 904DECLARE_KEEP_PAGER reset_secondary 905#endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 906