1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, Linaro Limited 4 * Copyright (c) 2021, Arm Limited 5 */ 6 7#include <arm32_macros.S> 8#include <arm.h> 9#include <asm.S> 10#include <generated/asm-defines.h> 11#include <keep.h> 12#include <kernel/asan.h> 13#include <kernel/cache_helpers.h> 14#include <platform_config.h> 15#include <sm/optee_smc.h> 16#include <sm/teesmc_opteed.h> 17#include <sm/teesmc_opteed_macros.h> 18 19#include "thread_private.h" 20 21.arch_extension sec 22 23.section .data 24.balign 4 25 26#ifdef CFG_BOOT_SYNC_CPU 27.equ SEM_CPU_READY, 1 28#endif 29 30#ifdef CFG_PL310 31.section .rodata.init 32panic_boot_file: 33 .asciz __FILE__ 34 35/* 36 * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) 37 */ 38LOCAL_FUNC __assert_flat_mapped_range , : 39UNWIND( .cantunwind) 40 push { r4-r6, lr } 41 mov r4, r0 42 mov r5, r1 43 bl cpu_mmu_enabled 44 cmp r0, #0 45 beq 1f 46 mov r0, r4 47 bl virt_to_phys 48 cmp r0, r4 49 beq 1f 50 /* 51 * this must be compliant with the panic generic routine: 52 * __do_panic(__FILE__, __LINE__, __func__, str) 53 */ 54 ldr r0, =panic_boot_file 55 mov r1, r5 56 mov r2, #0 57 mov r3, #0 58 bl __do_panic 59 b . /* should NOT return */ 601: pop { r4-r6, pc } 61END_FUNC __assert_flat_mapped_range 62 63 /* panic if mmu is enable and vaddr != paddr (scratch lr) */ 64 .macro assert_flat_mapped_range va, line 65 ldr r0, \va 66 ldr r1, =\line 67 bl __assert_flat_mapped_range 68 .endm 69#endif /* CFG_PL310 */ 70 71WEAK_FUNC plat_cpu_reset_early , : 72 bx lr 73END_FUNC plat_cpu_reset_early 74DECLARE_KEEP_PAGER plat_cpu_reset_early 75 76 .section .identity_map, "ax" 77 .align 5 78LOCAL_FUNC reset_vect_table , : , .identity_map 79 b . 80 b . /* Undef */ 81 b . /* Syscall */ 82 b . /* Prefetch abort */ 83 b . /* Data abort */ 84 b . /* Reserved */ 85 b . /* IRQ */ 86 b . /* FIQ */ 87END_FUNC reset_vect_table 88 89 .macro cpu_is_ready 90#ifdef CFG_BOOT_SYNC_CPU 91 bl __get_core_pos 92 lsl r0, r0, #2 93 ldr r1,=sem_cpu_sync 94 ldr r2, =SEM_CPU_READY 95 str r2, [r1, r0] 96 dsb 97 sev 98#endif 99 .endm 100 101 .macro wait_primary 102#ifdef CFG_BOOT_SYNC_CPU 103 ldr r0, =sem_cpu_sync 104 mov r2, #SEM_CPU_READY 105 sev 1061: 107 ldr r1, [r0] 108 cmp r1, r2 109 wfene 110 bne 1b 111#endif 112 .endm 113 114 .macro wait_secondary 115#ifdef CFG_BOOT_SYNC_CPU 116 ldr r0, =sem_cpu_sync 117 mov r3, #CFG_TEE_CORE_NB_CORE 118 mov r2, #SEM_CPU_READY 119 sev 1201: 121 subs r3, r3, #1 122 beq 3f 123 add r0, r0, #4 1242: 125 ldr r1, [r0] 126 cmp r1, r2 127 wfene 128 bne 2b 129 b 1b 1303: 131#endif 132 .endm 133 134 /* 135 * set_sctlr : Setup some core configuration in CP15 SCTLR 136 * 137 * Setup required by current implementation of the OP-TEE core: 138 * - Disable data and instruction cache. 139 * - MMU is expected off and exceptions trapped in ARM mode. 140 * - Enable or disable alignment checks upon platform configuration. 141 * - Optionally enable write-implies-execute-never. 142 * - Optionally enable round robin strategy for cache replacement. 143 * 144 * Clobbers r0. 145 */ 146 .macro set_sctlr 147 read_sctlr r0 148 bic r0, r0, #(SCTLR_M | SCTLR_C) 149 bic r0, r0, #SCTLR_I 150 bic r0, r0, #SCTLR_TE 151 orr r0, r0, #SCTLR_SPAN 152#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 153 orr r0, r0, #SCTLR_A 154#else 155 bic r0, r0, #SCTLR_A 156#endif 157#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC) 158 orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN) 159#endif 160#if defined(CFG_ENABLE_SCTLR_RR) 161 orr r0, r0, #SCTLR_RR 162#endif 163 write_sctlr r0 164 .endm 165 166#if defined(CFG_CORE_SEL1_SPMC) && defined(CFG_WITH_ARM_TRUSTED_FW) 167 /* 168 * With OP-TEE as SPMC at S-EL1 the SPMD (SPD_spmd) in TF-A passes 169 * the DTB in r0, pagable part in r1, and the rest of the registers 170 * are unused 171 * 172 * Save boot arguments passed 173 * entry r0, saved r6: device tree address 174 * entry r1, saved r4: pagestore 175 * saved r5, r7: Zero 176 */ 177 .macro bootargs_entry 178 mov r6, r0 179 mov r4, r1 180 mov r5, #0 181 mov r7, #0 182 .endm 183#else 184 /* 185 * Save boot arguments 186 * entry r0, saved r4: pagestore 187 * entry r1, saved r7: (ARMv7 standard bootarg #1) 188 * entry r2, saved r6: device tree address, (ARMv7 standard bootarg #2) 189 * entry lr, saved r5: non-secure entry address (ARMv7 bootarg #0) 190 */ 191 .macro bootargs_entry 192#if defined(CFG_NS_ENTRY_ADDR) 193 ldr r5, =CFG_NS_ENTRY_ADDR 194#else 195 mov r5, lr 196#endif 197#if defined(CFG_PAGEABLE_ADDR) 198 ldr r4, =CFG_PAGEABLE_ADDR 199#else 200 mov r4, r0 201#endif 202#if defined(CFG_DT_ADDR) 203 ldr r6, =CFG_DT_ADDR 204#else 205 mov r6, r2 206#endif 207 mov r7, r1 208 .endm 209#endif 210 211 .macro maybe_init_spectre_workaround 212#if !defined(CFG_WITH_ARM_TRUSTED_FW) && \ 213 (defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \ 214 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)) 215 read_midr r0 216 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH 217 cmp r1, #MIDR_IMPLEMENTER_ARM 218 bne 1f 219 ubfx r1, r0, #MIDR_PRIMARY_PART_NUM_SHIFT, \ 220 #MIDR_PRIMARY_PART_NUM_WIDTH 221 222 movw r2, #CORTEX_A8_PART_NUM 223 cmp r1, r2 224 moveq r2, #ACTLR_CA8_ENABLE_INVALIDATE_BTB 225 beq 2f 226 227 movw r2, #CORTEX_A15_PART_NUM 228 cmp r1, r2 229 moveq r2, #ACTLR_CA15_ENABLE_INVALIDATE_BTB 230 bne 1f /* Skip it for all other CPUs */ 2312: 232 read_actlr r0 233 orr r0, r0, r2 234 write_actlr r0 235 isb 2361: 237#endif 238 .endm 239 240FUNC _start , : 241UNWIND( .cantunwind) 242 243 bootargs_entry 244 245 /* 246 * 32bit entry is expected to execute Supervisor mode, 247 * some bootloader may enter in Supervisor or Monitor 248 */ 249 cps #CPSR_MODE_SVC 250 251 /* Early ARM secure MP specific configuration */ 252 bl plat_cpu_reset_early 253 maybe_init_spectre_workaround 254 255 set_sctlr 256 isb 257 258 ldr r0, =reset_vect_table 259 write_vbar r0 260 261#if defined(CFG_WITH_ARM_TRUSTED_FW) 262 b reset_primary 263#else 264 bl __get_core_pos 265 cmp r0, #0 266 beq reset_primary 267 b reset_secondary 268#endif 269END_FUNC _start 270DECLARE_KEEP_INIT _start 271 272 /* 273 * Setup sp to point to the top of the tmp stack for the current CPU: 274 * sp is assigned stack_tmp_export + cpu_id * stack_tmp_stride 275 */ 276 .macro set_sp 277 bl __get_core_pos 278 cmp r0, #CFG_TEE_CORE_NB_CORE 279 /* Unsupported CPU, park it before it breaks something */ 280 bge unhandled_cpu 281 282 /* 283 * stack_tmp_stride and stack_tmp_stride_rel are the 284 * equivalent of: 285 * extern const u32 stack_tmp_stride; 286 * u32 stack_tmp_stride_rel = (u32)&stack_tmp_stride - 287 * (u32)&stack_tmp_stride_rel 288 * 289 * To load the value of stack_tmp_stride we do the equivalent 290 * of: 291 * *(u32 *)(stack_tmp_stride + (u32)&stack_tmp_stride_rel) 292 */ 293 adr r3, stack_tmp_stride_rel 294 ldr r1, [r3] 295 ldr r1, [r1, r3] 296 297 /* Same pattern as for stack_tmp_stride above */ 298 adr r3, stack_tmp_export_rel 299 ldr r2, [r3] 300 ldr r2, [r2, r3] 301 302 /* 303 * r0 is core pos 304 * r1 is value of stack_tmp_stride 305 * r2 is value of stack_tmp_export 306 */ 307 mul r1, r0, r1 308 add sp, r1, r2 309 .endm 310 311 /* 312 * Cache maintenance during entry: handle outer cache. 313 * End address is exclusive: first byte not to be changed. 314 * Note however arm_clX_inv/cleanbyva operate on full cache lines. 315 * 316 * Use ANSI #define to trap source file line number for PL310 assertion 317 */ 318 .macro __inval_cache_vrange vbase, vend, line 319#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 320 assert_flat_mapped_range (\vbase), (\line) 321 bl pl310_base 322 ldr r1, \vbase 323 ldr r2, \vend 324 bl arm_cl2_invbypa 325#endif 326 ldr r0, \vbase 327 ldr r1, \vend 328 sub r1, r1, r0 329 bl dcache_inv_range 330 .endm 331 332 .macro __flush_cache_vrange vbase, vend, line 333#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 334 assert_flat_mapped_range (\vbase), (\line) 335 ldr r0, \vbase 336 ldr r1, \vend 337 sub r1, r1, r0 338 bl dcache_clean_range 339 bl pl310_base 340 ldr r1, \vbase 341 ldr r2, \vend 342 bl arm_cl2_cleaninvbypa 343#endif 344 ldr r0, \vbase 345 ldr r1, \vend 346 sub r1, r1, r0 347 bl dcache_cleaninv_range 348 .endm 349 350#define inval_cache_vrange(vbase, vend) \ 351 __inval_cache_vrange vbase, vend, __LINE__ 352 353#define flush_cache_vrange(vbase, vend) \ 354 __flush_cache_vrange vbase, vend, __LINE__ 355 356#ifdef CFG_BOOT_SYNC_CPU 357#define flush_cpu_semaphores \ 358 flush_cache_vrange(sem_cpu_sync_start, sem_cpu_sync_end) 359#else 360#define flush_cpu_semaphores 361#endif 362 363LOCAL_FUNC reset_primary , : , .identity_map 364UNWIND( .cantunwind) 365 366 /* preserve r4-r7: bootargs */ 367 368#ifdef CFG_WITH_PAGER 369 /* 370 * Move init code into correct location and move hashes to a 371 * temporary safe location until the heap is initialized. 372 * 373 * The binary is built as: 374 * [Pager code, rodata and data] : In correct location 375 * [Init code and rodata] : Should be copied to __init_start 376 * [struct boot_embdata + data] : Should be saved before 377 * initializing pager, first uint32_t tells the length of the data 378 */ 379 ldr r0, =__init_start /* dst */ 380 ldr r1, =__data_end /* src */ 381 ldr r2, =__init_end 382 sub r2, r2, r0 /* init len */ 383 ldr r12, [r1, r2] /* length of hashes etc */ 384 add r2, r2, r12 /* length of init and hashes etc */ 385 /* Copy backwards (as memmove) in case we're overlapping */ 386 add r0, r0, r2 /* __init_start + len */ 387 add r1, r1, r2 /* __data_end + len */ 388 str r0, cached_mem_end 389 ldr r2, =__init_start 390copy_init: 391 ldmdb r1!, {r3, r8-r12} 392 stmdb r0!, {r3, r8-r12} 393 cmp r0, r2 394 bgt copy_init 395#else 396 /* 397 * The binary is built as: 398 * [Core, rodata and data] : In correct location 399 * [struct boot_embdata + data] : Should be moved to __end, first 400 * uint32_t tells the length of the struct + data 401 */ 402 ldr r0, =__end /* dst */ 403 ldr r1, =__data_end /* src */ 404 ldr r2, [r1] /* struct boot_embdata::total_len */ 405 /* Copy backwards (as memmove) in case we're overlapping */ 406 add r0, r0, r2 407 add r1, r1, r2 408 str r0, cached_mem_end 409 ldr r2, =__end 410 411copy_init: 412 ldmdb r1!, {r3, r8-r12} 413 stmdb r0!, {r3, r8-r12} 414 cmp r0, r2 415 bgt copy_init 416#endif 417 418 /* 419 * Clear .bss, this code obviously depends on the linker keeping 420 * start/end of .bss at least 8 byte aligned. 421 */ 422 ldr r0, =__bss_start 423 ldr r1, =__bss_end 424 mov r2, #0 425 mov r3, #0 426clear_bss: 427 stmia r0!, {r2, r3} 428 cmp r0, r1 429 bls clear_bss 430 431#ifdef CFG_VIRTUALIZATION 432 /* 433 * Clear .nex_bss, this code obviously depends on the linker keeping 434 * start/end of .bss at least 8 byte aligned. 435 */ 436 ldr r0, =__nex_bss_start 437 ldr r1, =__nex_bss_end 438 mov r2, #0 439 mov r3, #0 440clear_nex_bss: 441 stmia r0!, {r2, r3} 442 cmp r0, r1 443 bls clear_nex_bss 444#endif 445 446#ifdef CFG_CORE_SANITIZE_KADDRESS 447 /* First initialize the entire shadow area with no access */ 448 ldr r0, =__asan_shadow_start /* start */ 449 ldr r1, =__asan_shadow_end /* limit */ 450 mov r2, #ASAN_DATA_RED_ZONE 451shadow_no_access: 452 str r2, [r0], #4 453 cmp r0, r1 454 bls shadow_no_access 455 456 /* Mark the entire stack area as OK */ 457 ldr r2, =CFG_ASAN_SHADOW_OFFSET 458 ldr r0, =__nozi_stack_start /* start */ 459 lsr r0, r0, #ASAN_BLOCK_SHIFT 460 add r0, r0, r2 461 ldr r1, =__nozi_stack_end /* limit */ 462 lsr r1, r1, #ASAN_BLOCK_SHIFT 463 add r1, r1, r2 464 mov r2, #0 465shadow_stack_access_ok: 466 strb r2, [r0], #1 467 cmp r0, r1 468 bls shadow_stack_access_ok 469#endif 470 471 set_sp 472 473 bl thread_init_thread_core_local 474 475 /* complete ARM secure MP common configuration */ 476 bl plat_primary_init_early 477 478 /* Enable Console */ 479 bl console_init 480 481#ifdef CFG_PL310 482 bl pl310_base 483 bl arm_cl2_config 484#endif 485 486 /* 487 * Invalidate dcache for all memory used during initialization to 488 * avoid nasty surprices when the cache is turned on. We must not 489 * invalidate memory not used by OP-TEE since we may invalidate 490 * entries used by for instance ARM Trusted Firmware. 491 */ 492 inval_cache_vrange(cached_mem_start, cached_mem_end) 493 494#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 495 /* Enable PL310 if not yet enabled */ 496 bl pl310_base 497 bl arm_cl2_enable 498#endif 499 500#ifdef CFG_CORE_ASLR 501 mov r0, r6 502 bl get_aslr_seed 503#else 504 mov r0, #0 505#endif 506 507 ldr r1, =boot_mmu_config 508 bl core_init_mmu_map 509 510#ifdef CFG_CORE_ASLR 511 /* 512 * Process relocation information for updating with the new offset. 513 * We're doing this now before MMU is enabled as some of the memory 514 * will become write protected. 515 */ 516 ldr r0, =boot_mmu_config 517 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 518 /* 519 * Update cached_mem_end address with load offset since it was 520 * calculated before relocation. 521 */ 522 ldr r2, cached_mem_end 523 add r2, r2, r0 524 str r2, cached_mem_end 525 526 bl relocate 527#endif 528 529 bl __get_core_pos 530 bl enable_mmu 531#ifdef CFG_CORE_ASLR 532 /* 533 * Reinitialize console, since register_serial_console() has 534 * previously registered a PA and with ASLR the VA is different 535 * from the PA. 536 */ 537 bl console_init 538#endif 539 540#ifdef CFG_VIRTUALIZATION 541 /* 542 * Initialize partition tables for each partition to 543 * default_partition which has been relocated now to a different VA 544 */ 545 bl core_mmu_set_default_prtn_tbl 546#endif 547 548 mov r0, r4 /* pageable part address */ 549 mov r1, r5 /* ns-entry address */ 550 bl boot_init_primary_early 551#ifndef CFG_VIRTUALIZATION 552 mov r9, sp 553 ldr r0, =threads 554 ldr r0, [r0, #THREAD_CTX_STACK_VA_END] 555 mov sp, r0 556 bl thread_get_core_local 557 mov r8, r0 558 mov r0, #0 559 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 560#endif 561 mov r0, r6 /* DT address */ 562 bl boot_init_primary_late 563#ifndef CFG_VIRTUALIZATION 564 mov r0, #THREAD_CLF_TMP 565 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 566 mov sp, r9 567#endif 568 569 /* 570 * In case we've touched memory that secondary CPUs will use before 571 * they have turned on their D-cache, clean and invalidate the 572 * D-cache before exiting to normal world. 573 */ 574 flush_cache_vrange(cached_mem_start, cached_mem_end) 575 576 /* release secondary boot cores and sync with them */ 577 cpu_is_ready 578 flush_cpu_semaphores 579 wait_secondary 580 581#ifdef CFG_PL310_LOCKED 582#ifdef CFG_PL310_SIP_PROTOCOL 583#error "CFG_PL310_LOCKED must not be defined when CFG_PL310_SIP_PROTOCOL=y" 584#endif 585 /* lock/invalidate all lines: pl310 behaves as if disable */ 586 bl pl310_base 587 bl arm_cl2_lockallways 588 bl pl310_base 589 bl arm_cl2_cleaninvbyway 590#endif 591 592 /* 593 * Clear current thread id now to allow the thread to be reused on 594 * next entry. Matches the thread_init_boot_thread() in 595 * boot.c. 596 */ 597#ifndef CFG_VIRTUALIZATION 598 bl thread_clr_boot_thread 599#endif 600 601#ifdef CFG_CORE_FFA 602 ldr r0, =cpu_on_handler 603 /* 604 * Compensate for the load offset since cpu_on_handler() is 605 * called with MMU off. 606 */ 607 ldr r1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 608 sub r0, r0, r1 609 bl ffa_secondary_cpu_ep_register 610 b thread_ffa_msg_wait 611#else /* CFG_CORE_FFA */ 612 613#if defined(CFG_WITH_ARM_TRUSTED_FW) 614 ldr r0, =boot_mmu_config 615 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 616 ldr r1, =thread_vector_table 617 /* Pass the vector address returned from main_init */ 618 sub r1, r1, r0 619#else 620 /* realy standard bootarg #1 and #2 to non secure entry */ 621 mov r4, #0 622 mov r3, r6 /* std bootarg #2 for register R2 */ 623 mov r2, r7 /* std bootarg #1 for register R1 */ 624 mov r1, #0 625#endif /* CFG_WITH_ARM_TRUSTED_FW */ 626 627 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 628 smc #0 629 b . /* SMC should not return */ 630#endif /* CFG_CORE_FFA */ 631END_FUNC reset_primary 632 633#ifdef CFG_BOOT_SYNC_CPU 634LOCAL_DATA sem_cpu_sync_start , : 635 .word sem_cpu_sync 636END_DATA sem_cpu_sync_start 637 638LOCAL_DATA sem_cpu_sync_end , : 639 .word sem_cpu_sync + (CFG_TEE_CORE_NB_CORE << 2) 640END_DATA sem_cpu_sync_end 641#endif 642 643LOCAL_DATA cached_mem_start , : 644 .word __text_start 645END_DATA cached_mem_start 646 647LOCAL_DATA cached_mem_end , : 648 .skip 4 649END_DATA cached_mem_end 650 651LOCAL_FUNC unhandled_cpu , : 652 wfi 653 b unhandled_cpu 654END_FUNC unhandled_cpu 655 656#ifdef CFG_CORE_ASLR 657LOCAL_FUNC relocate , : 658 push {r4-r5} 659 /* r0 holds load offset */ 660#ifdef CFG_WITH_PAGER 661 ldr r12, =__init_end 662#else 663 ldr r12, =__end 664#endif 665 ldr r2, [r12, #BOOT_EMBDATA_RELOC_OFFSET] 666 ldr r3, [r12, #BOOT_EMBDATA_RELOC_LEN] 667 668 mov_imm r1, TEE_RAM_START 669 add r2, r2, r12 /* start of relocations */ 670 add r3, r3, r2 /* end of relocations */ 671 672 /* 673 * Relocations are not formatted as Rel32, instead they are in a 674 * compressed format created by get_reloc_bin() in 675 * scripts/gen_tee_bin.py 676 * 677 * All the R_ARM_RELATIVE relocations are translated into a list 678 * list of 32-bit offsets from TEE_RAM_START. At each address a 679 * 32-bit value pointed out which increased with the load offset. 680 */ 681 682#ifdef CFG_WITH_PAGER 683 /* 684 * With pager enabled we can only relocate the pager and init 685 * parts, the rest has to be done when a page is populated. 686 */ 687 sub r12, r12, r1 688#endif 689 690 b 2f 691 /* Loop over the relocation addresses and process all entries */ 6921: ldr r4, [r2], #4 693#ifdef CFG_WITH_PAGER 694 /* Skip too large addresses */ 695 cmp r4, r12 696 bge 2f 697#endif 698 ldr r5, [r4, r1] 699 add r5, r5, r0 700 str r5, [r4, r1] 701 7022: cmp r2, r3 703 bne 1b 704 705 pop {r4-r5} 706 bx lr 707END_FUNC relocate 708#endif 709 710/* 711 * void enable_mmu(unsigned long core_pos); 712 * 713 * This function depends on being mapped with in the identity map where 714 * physical address and virtual address is the same. After MMU has been 715 * enabled the instruction pointer will be updated to execute as the new 716 * offset instead. Stack pointers and the return address are updated. 717 */ 718LOCAL_FUNC enable_mmu , : , .identity_map 719 /* r0 = core pos */ 720 adr r1, boot_mmu_config 721 722#ifdef CFG_WITH_LPAE 723 ldm r1!, {r2, r3} 724 /* 725 * r2 = ttbcr 726 * r3 = mair0 727 */ 728 write_ttbcr r2 729 write_mair0 r3 730 731 ldm r1!, {r2, r3} 732 /* 733 * r2 = ttbr0_base 734 * r3 = ttbr0_core_offset 735 */ 736 737 /* 738 * ttbr0_el1 = ttbr0_base + ttbr0_core_offset * core_pos 739 */ 740 mla r12, r0, r3, r2 741 mov r0, #0 742 write_ttbr0_64bit r12, r0 743 write_ttbr1_64bit r0, r0 744#else 745 ldm r1!, {r2, r3} 746 /* 747 * r2 = prrr 748 * r3 = nmrr 749 */ 750 write_prrr r2 751 write_nmrr r3 752 753 ldm r1!, {r2, r3} 754 /* 755 * r2 = dacr 756 * r3 = ttbcr 757 */ 758 write_dacr r2 759 write_ttbcr r3 760 761 ldm r1!, {r2} 762 /* r2 = ttbr */ 763 write_ttbr0 r2 764 write_ttbr1 r2 765 766 mov r2, #0 767 write_contextidr r2 768#endif 769 ldm r1!, {r2} 770 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */ 771 isb 772 773 /* Invalidate TLB */ 774 write_tlbiall 775 776 /* 777 * Make sure translation table writes have drained into memory and 778 * the TLB invalidation is complete. 779 */ 780 dsb sy 781 isb 782 783 read_sctlr r0 784 orr r0, r0, #SCTLR_M 785#ifndef CFG_WITH_LPAE 786 /* Enable Access flag (simplified access permissions) and TEX remap */ 787 orr r0, r0, #(SCTLR_AFE | SCTLR_TRE) 788#endif 789 write_sctlr r0 790 isb 791 792 /* Update vbar */ 793 read_vbar r1 794 add r1, r1, r2 795 write_vbar r1 796 isb 797 798 /* Invalidate instruction cache and branch predictor */ 799 write_iciallu 800 write_bpiall 801 isb 802 803 read_sctlr r0 804 /* Enable I and D cache */ 805 orr r0, r0, #SCTLR_I 806 orr r0, r0, #SCTLR_C 807#if defined(CFG_ENABLE_SCTLR_Z) 808 /* 809 * This is only needed on ARMv7 architecture and hence conditionned 810 * by configuration directive CFG_ENABLE_SCTLR_Z. For recent 811 * architectures, the program flow prediction is automatically 812 * enabled upon MMU enablement. 813 */ 814 orr r0, r0, #SCTLR_Z 815#endif 816 write_sctlr r0 817 isb 818 819 /* Adjust stack pointer and return address */ 820 add sp, sp, r2 821 add lr, lr, r2 822 823 bx lr 824END_FUNC enable_mmu 825 826LOCAL_DATA stack_tmp_export_rel , : 827 .word stack_tmp_export - stack_tmp_export_rel 828END_DATA stack_tmp_export_rel 829 830LOCAL_DATA stack_tmp_stride_rel , : 831 .word stack_tmp_stride - stack_tmp_stride_rel 832END_DATA stack_tmp_stride_rel 833 834DATA boot_mmu_config , : /* struct core_mmu_config */ 835 .skip CORE_MMU_CONFIG_SIZE 836END_DATA boot_mmu_config 837 838#if defined(CFG_WITH_ARM_TRUSTED_FW) 839FUNC cpu_on_handler , : , .identity_map 840UNWIND( .cantunwind) 841 mov r4, r0 842 mov r5, r1 843 mov r6, lr 844 845 set_sctlr 846 isb 847 848 adr r0, reset_vect_table 849 write_vbar r0 850 851 mov r4, lr 852 853 bl __get_core_pos 854 bl enable_mmu 855 856 set_sp 857 858 mov r0, r4 859 mov r1, r5 860 bl boot_cpu_on_handler 861#ifdef CFG_CORE_FFA 862 b thread_ffa_msg_wait 863#else 864 bx r6 865#endif 866END_FUNC cpu_on_handler 867DECLARE_KEEP_PAGER cpu_on_handler 868 869#else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 870 871LOCAL_FUNC reset_secondary , : , .identity_map 872UNWIND( .cantunwind) 873 adr r0, reset_vect_table 874 write_vbar r0 875 876 wait_primary 877 878 set_sp 879#ifdef CFG_CORE_ASLR 880 /* 881 * stack_tmp_export which is used as base when initializing sp has 882 * been relocated to the new offset. Since MMU isn't enabled on 883 * this CPU yet we need to restore the corresponding physical 884 * address. 885 */ 886 adr r0, boot_mmu_config 887 ldr r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET] 888 sub sp, sp, r0 889#endif 890 891#if defined (CFG_BOOT_SECONDARY_REQUEST) 892 /* if L1 is not invalidated before, do it here */ 893 mov r0, #DCACHE_OP_INV 894 bl dcache_op_level1 895#endif 896 897 bl __get_core_pos 898 bl enable_mmu 899 900 cpu_is_ready 901 902#if defined (CFG_BOOT_SECONDARY_REQUEST) 903 /* 904 * boot_core_hpen() return value (r0) is address of 905 * ns entry context structure 906 */ 907 bl boot_core_hpen 908 ldm r0, {r0, r6} 909#else 910 mov r0, r5 /* ns-entry address */ 911 mov r6, #0 912#endif 913 bl boot_init_secondary 914 915 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 916 mov r1, r6 917 mov r2, #0 918 mov r3, #0 919 mov r4, #0 920 smc #0 921 b . /* SMC should not return */ 922END_FUNC reset_secondary 923DECLARE_KEEP_PAGER reset_secondary 924#endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 925