1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, Linaro Limited 4 * Copyright (c) 2021-2023, Arm Limited 5 */ 6 7#include <arm.h> 8#include <arm32_macros.S> 9#include <asm.S> 10#include <generated/asm-defines.h> 11#include <keep.h> 12#include <kernel/asan.h> 13#include <kernel/cache_helpers.h> 14#include <kernel/thread.h> 15#include <kernel/thread_private.h> 16#include <mm/core_mmu.h> 17#include <platform_config.h> 18#include <sm/optee_smc.h> 19#include <sm/teesmc_opteed.h> 20#include <sm/teesmc_opteed_macros.h> 21 22.arch_extension sec 23 24.section .data 25.balign 4 26 27#ifdef CFG_BOOT_SYNC_CPU 28.equ SEM_CPU_READY, 1 29#endif 30 31#ifdef CFG_PL310 32.section .rodata.init 33panic_boot_file: 34 .asciz __FILE__ 35 36/* 37 * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) 38 */ 39LOCAL_FUNC __assert_flat_mapped_range , : 40UNWIND( .cantunwind) 41 push { r4-r6, lr } 42 mov r4, r0 43 mov r5, r1 44 bl cpu_mmu_enabled 45 cmp r0, #0 46 beq 1f 47 mov r0, r4 48 bl virt_to_phys 49 cmp r0, r4 50 beq 1f 51 /* 52 * this must be compliant with the panic generic routine: 53 * __do_panic(__FILE__, __LINE__, __func__, str) 54 */ 55 ldr r0, =panic_boot_file 56 mov r1, r5 57 mov r2, #0 58 mov r3, #0 59 bl __do_panic 60 b . /* should NOT return */ 611: pop { r4-r6, pc } 62END_FUNC __assert_flat_mapped_range 63 64 /* panic if mmu is enable and vaddr != paddr (scratch lr) */ 65 .macro assert_flat_mapped_range va, line 66 ldr r0, \va 67 ldr r1, =\line 68 bl __assert_flat_mapped_range 69 .endm 70#endif /* CFG_PL310 */ 71 72WEAK_FUNC plat_cpu_reset_early , : 73 bx lr 74END_FUNC plat_cpu_reset_early 75DECLARE_KEEP_PAGER plat_cpu_reset_early 76 77 .section .identity_map, "ax" 78 .align 5 79LOCAL_FUNC reset_vect_table , : , .identity_map 80 b . 81 b . /* Undef */ 82 b . /* Syscall */ 83 b . /* Prefetch abort */ 84 b . /* Data abort */ 85 b . /* Reserved */ 86 b . /* IRQ */ 87 b . /* FIQ */ 88END_FUNC reset_vect_table 89 90 .macro cpu_is_ready 91#ifdef CFG_BOOT_SYNC_CPU 92 bl __get_core_pos 93 lsl r0, r0, #2 94 ldr r1,=sem_cpu_sync 95 ldr r2, =SEM_CPU_READY 96 str r2, [r1, r0] 97 dsb 98 sev 99#endif 100 .endm 101 102 .macro wait_primary 103#ifdef CFG_BOOT_SYNC_CPU 104 ldr r0, =sem_cpu_sync 105 mov r2, #SEM_CPU_READY 106 sev 1071: 108 ldr r1, [r0] 109 cmp r1, r2 110 wfene 111 bne 1b 112#endif 113 .endm 114 115 .macro wait_secondary 116#ifdef CFG_BOOT_SYNC_CPU 117 ldr r0, =sem_cpu_sync 118 mov r3, #CFG_TEE_CORE_NB_CORE 119 mov r2, #SEM_CPU_READY 120 sev 1211: 122 subs r3, r3, #1 123 beq 3f 124 add r0, r0, #4 1252: 126 ldr r1, [r0] 127 cmp r1, r2 128 wfene 129 bne 2b 130 b 1b 1313: 132#endif 133 .endm 134 135 /* 136 * set_sctlr : Setup some core configuration in CP15 SCTLR 137 * 138 * Setup required by current implementation of the OP-TEE core: 139 * - Disable data and instruction cache. 140 * - MMU is expected off and exceptions trapped in ARM mode. 141 * - Enable or disable alignment checks upon platform configuration. 142 * - Optionally enable write-implies-execute-never. 143 * - Optionally enable round robin strategy for cache replacement. 144 * 145 * Clobbers r0. 146 */ 147 .macro set_sctlr 148 read_sctlr r0 149 bic r0, r0, #(SCTLR_M | SCTLR_C) 150 bic r0, r0, #SCTLR_I 151 bic r0, r0, #SCTLR_TE 152 orr r0, r0, #SCTLR_SPAN 153#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 154 orr r0, r0, #SCTLR_A 155#else 156 bic r0, r0, #SCTLR_A 157#endif 158#if defined(CFG_HWSUPP_MEM_PERM_WXN) && defined(CFG_CORE_RWDATA_NOEXEC) 159 orr r0, r0, #(SCTLR_WXN | SCTLR_UWXN) 160#endif 161#if defined(CFG_ENABLE_SCTLR_RR) 162 orr r0, r0, #SCTLR_RR 163#endif 164 write_sctlr r0 165 .endm 166 167 .macro maybe_init_spectre_workaround 168#if !defined(CFG_WITH_ARM_TRUSTED_FW) && \ 169 (defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \ 170 defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)) 171 read_midr r0 172 ubfx r1, r0, #MIDR_IMPLEMENTER_SHIFT, #MIDR_IMPLEMENTER_WIDTH 173 cmp r1, #MIDR_IMPLEMENTER_ARM 174 bne 1f 175 ubfx r1, r0, #MIDR_PRIMARY_PART_NUM_SHIFT, \ 176 #MIDR_PRIMARY_PART_NUM_WIDTH 177 178 movw r2, #CORTEX_A8_PART_NUM 179 cmp r1, r2 180 moveq r2, #ACTLR_CA8_ENABLE_INVALIDATE_BTB 181 beq 2f 182 183 movw r2, #CORTEX_A15_PART_NUM 184 cmp r1, r2 185 moveq r2, #ACTLR_CA15_ENABLE_INVALIDATE_BTB 186 bne 1f /* Skip it for all other CPUs */ 1872: 188 read_actlr r0 189 orr r0, r0, r2 190 write_actlr r0 191 isb 1921: 193#endif 194 .endm 195 196FUNC _start , : 197UNWIND( .cantunwind) 198 /* 199 * Temporary copy of boot argument registers, will be passed to 200 * boot_save_args() further down. 201 */ 202 mov r4, r0 203 mov r5, r1 204 mov r6, r2 205 mov r7, r3 206 mov r8, lr 207 208 /* 209 * 32bit entry is expected to execute Supervisor mode, 210 * some bootloader may enter in Supervisor or Monitor 211 */ 212 cps #CPSR_MODE_SVC 213 214 /* Early ARM secure MP specific configuration */ 215 bl plat_cpu_reset_early 216 maybe_init_spectre_workaround 217 218 set_sctlr 219 isb 220 221 ldr r0, =reset_vect_table 222 write_vbar r0 223 224#if defined(CFG_WITH_ARM_TRUSTED_FW) 225 b reset_primary 226#else 227 bl __get_core_pos 228 cmp r0, #0 229 beq reset_primary 230 b reset_secondary 231#endif 232END_FUNC _start 233DECLARE_KEEP_INIT _start 234 235 /* 236 * Setup sp to point to the top of the tmp stack for the current CPU: 237 * sp is assigned: 238 * stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD 239 */ 240 .macro set_sp 241 bl __get_core_pos 242 cmp r0, #CFG_TEE_CORE_NB_CORE 243 /* Unsupported CPU, park it before it breaks something */ 244 bge unhandled_cpu 245 add r0, r0, #1 246 247 /* r2 = stack_tmp - STACK_TMP_GUARD */ 248 adr r3, stack_tmp_rel 249 ldr r2, [r3] 250 add r2, r2, r3 251 252 /* 253 * stack_tmp_stride and stack_tmp_stride_rel are the 254 * equivalent of: 255 * extern const u32 stack_tmp_stride; 256 * u32 stack_tmp_stride_rel = (u32)&stack_tmp_stride - 257 * (u32)&stack_tmp_stride_rel 258 * 259 * To load the value of stack_tmp_stride we do the equivalent 260 * of: 261 * *(u32 *)(stack_tmp_stride + (u32)&stack_tmp_stride_rel) 262 */ 263 adr r3, stack_tmp_stride_rel 264 ldr r1, [r3] 265 ldr r1, [r1, r3] 266 267 /* 268 * r0 is core pos + 1 269 * r1 is value of stack_tmp_stride 270 * r2 is value of stack_tmp + guard 271 */ 272 mul r1, r0, r1 273 add sp, r1, r2 274 .endm 275 276 /* 277 * Cache maintenance during entry: handle outer cache. 278 * End address is exclusive: first byte not to be changed. 279 * Note however arm_clX_inv/cleanbyva operate on full cache lines. 280 * 281 * Use ANSI #define to trap source file line number for PL310 assertion 282 */ 283 .macro __inval_cache_vrange vbase, vend, line 284#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 285 assert_flat_mapped_range (\vbase), (\line) 286 bl pl310_base 287 ldr r1, \vbase 288 ldr r2, =\vend 289 ldr r2, [r2] 290 bl arm_cl2_invbypa 291#endif 292 ldr r0, \vbase 293 ldr r1, =\vend 294 ldr r1, [r1] 295 sub r1, r1, r0 296 bl dcache_inv_range 297 .endm 298 299 .macro __flush_cache_vrange vbase, vend, line 300#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 301 assert_flat_mapped_range (\vbase), (\line) 302 ldr r0, \vbase 303 ldr r1, =\vend 304 ldr r1, [r1] 305 sub r1, r1, r0 306 bl dcache_clean_range 307 bl pl310_base 308 ldr r1, \vbase 309 ldr r2, =\vend 310 ldr r2, [r2] 311 bl arm_cl2_cleaninvbypa 312#endif 313 ldr r0, \vbase 314 ldr r1, =\vend 315 ldr r1, [r1] 316 sub r1, r1, r0 317 bl dcache_cleaninv_range 318 .endm 319 320#define inval_cache_vrange(vbase, vend) \ 321 __inval_cache_vrange vbase, vend, __LINE__ 322 323#define flush_cache_vrange(vbase, vend) \ 324 __flush_cache_vrange vbase, vend, __LINE__ 325 326#ifdef CFG_BOOT_SYNC_CPU 327#define flush_cpu_semaphores \ 328 flush_cache_vrange(sem_cpu_sync_start, sem_cpu_sync_end) 329#else 330#define flush_cpu_semaphores 331#endif 332 333LOCAL_FUNC reset_primary , : , .identity_map 334UNWIND( .cantunwind) 335 336 /* preserve r4-r8: bootargs */ 337 338#ifdef CFG_WITH_PAGER 339 /* 340 * Move init code into correct location and move hashes to a 341 * temporary safe location until the heap is initialized. 342 * 343 * The binary is built as: 344 * [Pager code, rodata and data] : In correct location 345 * [Init code and rodata] : Should be copied to __init_start 346 * [struct boot_embdata + data] : Should be saved before 347 * initializing pager, first uint32_t tells the length of the data 348 */ 349 ldr r0, =__init_start /* dst */ 350 ldr r1, =__data_end /* src */ 351 ldr r2, =__init_end 352 sub r2, r2, r0 /* init len */ 353 ldr r12, [r1, r2] /* length of hashes etc */ 354 add r2, r2, r12 /* length of init and hashes etc */ 355 /* Copy backwards (as memmove) in case we're overlapping */ 356 add r0, r0, r2 /* __init_start + len */ 357 add r1, r1, r2 /* __data_end + len */ 358 ldr r3, =boot_cached_mem_end 359 str r0, [r3] 360 ldr r2, =__init_start 361copy_init: 362 ldmdb r1!, {r3, r9-r12} 363 stmdb r0!, {r3, r9-r12} 364 cmp r0, r2 365 bgt copy_init 366#else 367 /* 368 * The binary is built as: 369 * [Core, rodata and data] : In correct location 370 * [struct boot_embdata + data] : Should be moved to right before 371 * __vcore_free_end, the first uint32_t tells the length of the 372 * struct + data 373 */ 374 ldr r1, =__data_end /* src */ 375 ldr r2, [r1] /* struct boot_embdata::total_len */ 376 /* dst */ 377 ldr r0, =__vcore_free_end 378 sub r0, r0, r2 379 /* round down to beginning of page */ 380 mov r3, #(SMALL_PAGE_SIZE - 1) 381 bic r0, r0, r3 382 ldr r3, =boot_embdata_ptr 383 str r0, [r3] 384 /* Copy backwards (as memmove) in case we're overlapping */ 385 add r1, r1, r2 386 add r2, r0, r2 387 ldr r3, =boot_cached_mem_end 388 str r2, [r3] 389 390copy_init: 391 ldmdb r1!, {r3, r9-r12} 392 stmdb r2!, {r3, r9-r12} 393 cmp r2, r0 394 bgt copy_init 395#endif 396 397 /* 398 * Clear .bss, this code obviously depends on the linker keeping 399 * start/end of .bss at least 8 byte aligned. 400 */ 401 ldr r0, =__bss_start 402 ldr r1, =__bss_end 403 mov r2, #0 404 mov r3, #0 405clear_bss: 406 stmia r0!, {r2, r3} 407 cmp r0, r1 408 bls clear_bss 409 410#ifdef CFG_NS_VIRTUALIZATION 411 /* 412 * Clear .nex_bss, this code obviously depends on the linker keeping 413 * start/end of .bss at least 8 byte aligned. 414 */ 415 ldr r0, =__nex_bss_start 416 ldr r1, =__nex_bss_end 417 mov r2, #0 418 mov r3, #0 419clear_nex_bss: 420 stmia r0!, {r2, r3} 421 cmp r0, r1 422 bls clear_nex_bss 423#endif 424 425#ifdef CFG_CORE_SANITIZE_KADDRESS 426 /* First initialize the entire shadow area with no access */ 427 ldr r0, =__asan_shadow_start /* start */ 428 ldr r1, =__asan_shadow_end /* limit */ 429 mov r2, #ASAN_DATA_RED_ZONE 430shadow_no_access: 431 str r2, [r0], #4 432 cmp r0, r1 433 bls shadow_no_access 434 435 /* Mark the entire stack area as OK */ 436 ldr r2, =CFG_ASAN_SHADOW_OFFSET 437 ldr r0, =__nozi_stack_start /* start */ 438 lsr r0, r0, #ASAN_BLOCK_SHIFT 439 add r0, r0, r2 440 ldr r1, =__nozi_stack_end /* limit */ 441 lsr r1, r1, #ASAN_BLOCK_SHIFT 442 add r1, r1, r2 443 mov r2, #0 444shadow_stack_access_ok: 445 strb r2, [r0], #1 446 cmp r0, r1 447 bls shadow_stack_access_ok 448#endif 449 450 set_sp 451 452 /* Initialize thread_core_local[current_cpu_id] for early boot */ 453 bl thread_get_core_local 454 push {r0,r1} 455 bl thread_get_abt_stack 456 pop {r1,r2} 457 mov r3, sp 458 459 cps #CPSR_MODE_IRQ 460 mov sp, r3 461 cps #CPSR_MODE_FIQ 462 mov sp, r3 463 cps #CPSR_MODE_ABT 464 mov sp, r1 465 cps #CPSR_MODE_UND 466 mov sp, r1 467 cps #CPSR_MODE_SVC 468 469 str sp, [r1, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 470 str r0, [r1, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 471 mov r0, #THREAD_ID_INVALID 472 str r0, [r1, #THREAD_CORE_LOCAL_CURR_THREAD] 473 mov r0, #THREAD_CLF_TMP 474 str r0, [r1, #THREAD_CORE_LOCAL_FLAGS] 475 476 /* complete ARM secure MP common configuration */ 477 bl plat_primary_init_early 478 479 /* Enable Console */ 480 bl console_init 481 482 mov r0, r8 483 mov r1, #0 484 push {r0, r1} 485 mov r0, r4 486 mov r1, r5 487 mov r2, r6 488 mov r3, r7 489 bl boot_save_args 490 add sp, sp, #(2 * 4) 491 492#ifdef CFG_WITH_PAGER 493 ldr r0, =__init_end /* pointer to boot_embdata */ 494 ldr r1, [r0] /* struct boot_embdata::total_len */ 495 add r0, r0, r1 496 mov_imm r1, 0xfff 497 add r0, r0, r1 /* round up */ 498 bic r0, r0, r1 /* to next page */ 499 mov_imm r1, (TEE_RAM_PH_SIZE + TEE_RAM_START) 500 mov r2, r1 501#else 502 ldr r0, =__vcore_free_start 503 ldr r1, =boot_embdata_ptr 504 ldr r1, [r1] 505 ldr r2, =__vcore_free_end 506#endif 507 bl boot_mem_init 508 509#ifdef CFG_PL310 510 bl pl310_base 511 bl arm_cl2_config 512#endif 513 514 /* 515 * Invalidate dcache for all memory used during initialization to 516 * avoid nasty surprices when the cache is turned on. We must not 517 * invalidate memory not used by OP-TEE since we may invalidate 518 * entries used by for instance ARM Trusted Firmware. 519 */ 520 inval_cache_vrange(cached_mem_start, boot_cached_mem_end) 521 522#if defined(CFG_PL310) && !defined(CFG_PL310_SIP_PROTOCOL) 523 /* Enable PL310 if not yet enabled */ 524 bl pl310_base 525 bl arm_cl2_enable 526#endif 527 528#ifdef CFG_CORE_ASLR 529 bl get_aslr_seed 530#ifdef CFG_CORE_ASLR_SEED 531 mov_imm r0, CFG_CORE_ASLR_SEED 532#endif 533#else 534 mov r0, #0 535#endif 536 537 ldr r1, =boot_mmu_config 538 bl core_init_mmu_map 539 540#ifdef CFG_CORE_ASLR 541 /* 542 * Save a pointer to thread_core_local[core_pos] since we can't 543 * call thread_get_core_local() again before the recorded end_va's 544 * have been updated below. 545 */ 546 bl thread_get_core_local 547 mov r4, r0 548 549 /* 550 * Process relocation information for updating with the virtual map 551 * offset. We're doing this now before MMU is enabled as some of 552 * the memory will become write protected. 553 */ 554 ldr r0, =boot_mmu_config 555 ldr r0, [r0, #CORE_MMU_CONFIG_MAP_OFFSET] 556 /* 557 * Update boot_cached_mem_end address with load offset since it was 558 * calculated before relocation. 559 */ 560 ldr r3, =boot_cached_mem_end 561 ldr r2, [r3] 562 add r2, r2, r0 563 str r2, [r3] 564 565 bl relocate 566#endif 567 568 bl __get_core_pos 569 bl enable_mmu 570#ifdef CFG_CORE_ASLR 571 ldr r0, =boot_mmu_config 572 ldr r0, [r0, #CORE_MMU_CONFIG_MAP_OFFSET] 573 bl boot_mem_relocate 574 /* 575 * Update recorded end_va, we depend on r4 pointing to the 576 * pre-relocated thread_core_local[core_pos]. 577 */ 578 ldr r1, =boot_mmu_config 579 ldr r1, [r1, #CORE_MMU_CONFIG_MAP_OFFSET] 580 add r4, r4, r1 581 ldr r0, [r4, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 582 add r0, r0, r1 583 str r0, [r4, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 584 ldr r0, [r4, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 585 add r0, r0, r1 586 str r0, [r4, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 587 588 cps #CPSR_MODE_IRQ 589 mov sp, r0 590 cps #CPSR_MODE_FIQ 591 mov sp, r0 592 cps #CPSR_MODE_ABT 593 mov sp, r4 594 cps #CPSR_MODE_UND 595 mov sp, r4 596 cps #CPSR_MODE_SVC 597 598 /* 599 * Reinitialize console, since register_serial_console() has 600 * previously registered a PA and with ASLR the VA is different 601 * from the PA. 602 */ 603 bl console_init 604#endif 605 606#ifdef CFG_NS_VIRTUALIZATION 607 /* 608 * Initialize partition tables for each partition to 609 * default_partition which has been relocated now to a different VA 610 */ 611 bl core_mmu_set_default_prtn_tbl 612#endif 613 614 bl boot_init_primary_early 615 bl boot_init_primary_late 616#ifndef CFG_NS_VIRTUALIZATION 617 mov r9, sp 618 ldr r0, =threads 619 ldr r0, [r0, #THREAD_CTX_STACK_VA_END] 620 mov sp, r0 621 bl thread_get_core_local 622 mov r8, r0 623 mov r0, #0 624 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 625#endif 626 bl boot_init_primary_runtime 627 bl boot_init_primary_final 628#ifndef CFG_NS_VIRTUALIZATION 629 mov r0, #THREAD_CLF_TMP 630 str r0, [r8, #THREAD_CORE_LOCAL_FLAGS] 631 mov sp, r9 632#endif 633 634#ifdef _CFG_CORE_STACK_PROTECTOR 635 /* Update stack canary value */ 636 sub sp, sp, #0x8 637 mov r0, sp 638 mov r1, #1 639 mov r2, #0x4 640 bl plat_get_random_stack_canaries 641 ldr r0, [sp] 642 ldr r1, =__stack_chk_guard 643 str r0, [r1] 644 add sp, sp, #0x8 645#endif 646 647 /* 648 * In case we've touched memory that secondary CPUs will use before 649 * they have turned on their D-cache, clean and invalidate the 650 * D-cache before exiting to normal world. 651 */ 652 flush_cache_vrange(cached_mem_start, boot_cached_mem_end) 653 654 /* release secondary boot cores and sync with them */ 655 cpu_is_ready 656 flush_cpu_semaphores 657 wait_secondary 658 659#ifdef CFG_PL310_LOCKED 660#ifdef CFG_PL310_SIP_PROTOCOL 661#error "CFG_PL310_LOCKED must not be defined when CFG_PL310_SIP_PROTOCOL=y" 662#endif 663 /* lock/invalidate all lines: pl310 behaves as if disable */ 664 bl pl310_base 665 bl arm_cl2_lockallways 666 bl pl310_base 667 bl arm_cl2_cleaninvbyway 668#endif 669 670 /* 671 * Clear current thread id now to allow the thread to be reused on 672 * next entry. Matches the thread_init_boot_thread() in 673 * boot.c. 674 */ 675#ifndef CFG_NS_VIRTUALIZATION 676 bl thread_clr_boot_thread 677#endif 678 679#ifdef CFG_CORE_FFA 680 ldr r0, =cpu_on_handler 681 /* 682 * Compensate for the virtual map offset since cpu_on_handler() is 683 * called with MMU off. 684 */ 685 ldr r1, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET 686 sub r0, r0, r1 687 bl thread_spmc_register_secondary_ep 688 b thread_ffa_msg_wait 689#else /* CFG_CORE_FFA */ 690 691#if defined(CFG_WITH_ARM_TRUSTED_FW) 692 ldr r0, =boot_mmu_config 693 ldr r0, [r0, #CORE_MMU_CONFIG_MAP_OFFSET] 694 ldr r1, =thread_vector_table 695 /* Pass the vector address returned from main_init */ 696 sub r1, r1, r0 697#else 698 /* Initialize secure monitor */ 699 add r0, sp, #__STACK_TMP_OFFS 700 bl sm_init 701 ldr r0, =boot_arg_nsec_entry 702 ldr r0, [r0] 703 bl init_sec_mon 704 705 /* Relay standard bootarg #1 and #2 to non-secure entry */ 706 mov r4, #0 707 mov r3, r6 /* std bootarg #2 for register R2 */ 708 mov r2, r5 /* std bootarg #1 for register R1 */ 709 mov r1, #0 710#endif /* CFG_WITH_ARM_TRUSTED_FW */ 711 712 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 713 smc #0 714 /* SMC should not return */ 715 panic_at_smc_return 716#endif /* CFG_CORE_FFA */ 717END_FUNC reset_primary 718 719#ifdef CFG_BOOT_SYNC_CPU 720LOCAL_DATA sem_cpu_sync_start , : 721 .word sem_cpu_sync 722END_DATA sem_cpu_sync_start 723 724LOCAL_DATA sem_cpu_sync_end , : 725 .word sem_cpu_sync + (CFG_TEE_CORE_NB_CORE << 2) 726END_DATA sem_cpu_sync_end 727#endif 728 729LOCAL_DATA cached_mem_start , : 730 .word __text_start 731END_DATA cached_mem_start 732 733#ifndef CFG_WITH_PAGER 734LOCAL_DATA boot_embdata_ptr , : 735 .skip 4 736END_DATA boot_embdata_ptr 737#endif 738 739LOCAL_FUNC unhandled_cpu , : 740 wfi 741 b unhandled_cpu 742END_FUNC unhandled_cpu 743 744#ifdef CFG_CORE_ASLR 745LOCAL_FUNC relocate , : 746 push {r4-r5} 747 /* r0 holds load offset */ 748#ifdef CFG_WITH_PAGER 749 ldr r12, =__init_end 750#else 751 ldr r12, =boot_embdata_ptr 752 ldr r12, [r12] 753#endif 754 ldr r2, [r12, #BOOT_EMBDATA_RELOC_OFFSET] 755 ldr r3, [r12, #BOOT_EMBDATA_RELOC_LEN] 756 757 mov_imm r1, TEE_LOAD_ADDR 758 add r2, r2, r12 /* start of relocations */ 759 add r3, r3, r2 /* end of relocations */ 760 761 /* 762 * Relocations are not formatted as Rel32, instead they are in a 763 * compressed format created by get_reloc_bin() in 764 * scripts/gen_tee_bin.py 765 * 766 * All the R_ARM_RELATIVE relocations are translated into a list of 767 * 32-bit offsets from TEE_LOAD_ADDR. At each address a 32-bit 768 * value pointed out which increased with the load offset. 769 */ 770 771#ifdef CFG_WITH_PAGER 772 /* 773 * With pager enabled we can only relocate the pager and init 774 * parts, the rest has to be done when a page is populated. 775 */ 776 sub r12, r12, r1 777#endif 778 779 b 2f 780 /* Loop over the relocation addresses and process all entries */ 7811: ldr r4, [r2], #4 782#ifdef CFG_WITH_PAGER 783 /* Skip too large addresses */ 784 cmp r4, r12 785 bge 2f 786#endif 787 ldr r5, [r4, r1] 788 add r5, r5, r0 789 str r5, [r4, r1] 790 7912: cmp r2, r3 792 bne 1b 793 794 pop {r4-r5} 795 bx lr 796END_FUNC relocate 797#endif 798 799/* 800 * void enable_mmu(unsigned long core_pos); 801 * 802 * This function depends on being mapped with in the identity map where 803 * physical address and virtual address is the same. After MMU has been 804 * enabled the instruction pointer will be updated to execute as the new 805 * offset instead. Stack pointers and the return address are updated. 806 */ 807LOCAL_FUNC enable_mmu , : , .identity_map 808 /* r0 = core pos */ 809 adr r1, boot_mmu_config 810 811#ifdef CFG_WITH_LPAE 812 ldm r1!, {r2, r3} 813 /* 814 * r2 = ttbcr 815 * r3 = mair0 816 */ 817 write_ttbcr r2 818 write_mair0 r3 819 820 ldm r1!, {r2, r3} 821 /* 822 * r2 = ttbr0_base 823 * r3 = ttbr0_core_offset 824 */ 825 826 /* 827 * ttbr0_el1 = ttbr0_base + ttbr0_core_offset * core_pos 828 */ 829 mla r12, r0, r3, r2 830 mov r0, #0 831 write_ttbr0_64bit r12, r0 832 write_ttbr1_64bit r0, r0 833#else 834 ldm r1!, {r2, r3} 835 /* 836 * r2 = prrr 837 * r3 = nmrr 838 */ 839 write_prrr r2 840 write_nmrr r3 841 842 ldm r1!, {r2, r3} 843 /* 844 * r2 = dacr 845 * r3 = ttbcr 846 */ 847 write_dacr r2 848 write_ttbcr r3 849 850 ldm r1!, {r2} 851 /* r2 = ttbr */ 852 write_ttbr0 r2 853 write_ttbr1 r2 854 855 mov r2, #0 856 write_contextidr r2 857#endif 858 ldm r1!, {r2} 859 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */ 860 isb 861 862 /* Invalidate TLB */ 863 write_tlbiall 864 865 /* 866 * Make sure translation table writes have drained into memory and 867 * the TLB invalidation is complete. 868 */ 869 dsb sy 870 isb 871 872 read_sctlr r0 873 orr r0, r0, #SCTLR_M 874#ifndef CFG_WITH_LPAE 875 /* Enable Access flag (simplified access permissions) and TEX remap */ 876 orr r0, r0, #(SCTLR_AFE | SCTLR_TRE) 877#endif 878 write_sctlr r0 879 isb 880 881 /* Update vbar */ 882 read_vbar r1 883 add r1, r1, r2 884 write_vbar r1 885 isb 886 887 /* Invalidate instruction cache and branch predictor */ 888 write_iciallu 889 write_bpiall 890 isb 891 892 read_sctlr r0 893 /* Enable I and D cache */ 894 orr r0, r0, #SCTLR_I 895 orr r0, r0, #SCTLR_C 896#if defined(CFG_ENABLE_SCTLR_Z) 897 /* 898 * This is only needed on ARMv7 architecture and hence conditionned 899 * by configuration directive CFG_ENABLE_SCTLR_Z. For recent 900 * architectures, the program flow prediction is automatically 901 * enabled upon MMU enablement. 902 */ 903 orr r0, r0, #SCTLR_Z 904#endif 905 write_sctlr r0 906 isb 907 908 /* Adjust stack pointer and return address */ 909 add sp, sp, r2 910 add lr, lr, r2 911 912 bx lr 913END_FUNC enable_mmu 914 915LOCAL_DATA stack_tmp_rel , : 916 .word stack_tmp - stack_tmp_rel - STACK_TMP_GUARD 917END_DATA stack_tmp_rel 918 919LOCAL_DATA stack_tmp_stride_rel , : 920 .word stack_tmp_stride - stack_tmp_stride_rel 921END_DATA stack_tmp_stride_rel 922 923DATA boot_mmu_config , : /* struct core_mmu_config */ 924 .skip CORE_MMU_CONFIG_SIZE 925END_DATA boot_mmu_config 926 927#if defined(CFG_WITH_ARM_TRUSTED_FW) 928FUNC cpu_on_handler , : , .identity_map 929UNWIND( .cantunwind) 930 mov r4, r0 931 mov r5, r1 932 mov r6, lr 933 934 set_sctlr 935 isb 936 937 ldr r0, =reset_vect_table 938 write_vbar r0 939 940 mov r4, lr 941 942 bl __get_core_pos 943 bl enable_mmu 944 945 set_sp 946 947 mov r0, r4 948 mov r1, r5 949 bl boot_cpu_on_handler 950#ifdef CFG_CORE_FFA 951 b thread_ffa_msg_wait 952#else 953 bx r6 954#endif 955END_FUNC cpu_on_handler 956DECLARE_KEEP_PAGER cpu_on_handler 957 958#else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 959 960LOCAL_FUNC reset_secondary , : , .identity_map 961UNWIND( .cantunwind) 962 ldr r0, =reset_vect_table 963 write_vbar r0 964 965 wait_primary 966 967 set_sp 968 969#if defined (CFG_BOOT_SECONDARY_REQUEST) 970 /* if L1 is not invalidated before, do it here */ 971 mov r0, #DCACHE_OP_INV 972 bl dcache_op_level1 973#endif 974 975 bl __get_core_pos 976 bl enable_mmu 977 978 cpu_is_ready 979 980#if defined (CFG_BOOT_SECONDARY_REQUEST) 981 /* 982 * boot_core_hpen() return value (r0) is address of 983 * ns entry context structure 984 */ 985 bl boot_core_hpen 986 ldm r0, {r0, r6} 987 mov r8, r0 988#else 989 mov r6, #0 990#endif 991 bl boot_init_secondary 992 993 /* Initialize secure monitor */ 994 add r0, sp, #__STACK_TMP_OFFS 995 bl sm_init 996 mov r0, r8 /* ns-entry address */ 997 bl init_sec_mon 998 999 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 1000 mov r1, r6 1001 mov r2, #0 1002 mov r3, #0 1003 mov r4, #0 1004 smc #0 1005 /* SMC should not return */ 1006 panic_at_smc_return 1007END_FUNC reset_secondary 1008DECLARE_KEEP_PAGER reset_secondary 1009#endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ 1010